JPS61100938A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the semiconductor element having special merits that the stray capacity is small, that the response to quick signal is superior, and that the minute circuit is obtainable, by composing the insulator substrate with the silicon single crystal substrate and the single crystal thin film of the semi- insulating semicondutor having the matched lattice to the silicon single crystal and the wider forbidden band than the silicon single crystal. CONSTITUTION:The insulator substrate is substrate 1 and the single crystal thin film 2 of the semi-insulating semiconductor having the matched lattice to the silicon single crystal and the wider forbidden band than the silicon single crystal. For example, the substrate 1 is made of p-type silicon single crystal whose surface orientation is (100) and impurity density is about 1X10<15>cm<-3>. On this surface the thin film 2 of the single crystal of the semi-insulating gallim phosphide is formed by epitaxial growth, on which the thin film 3 of the p-type silicon single crystal is formed. Installing the source and drain of MOSFET in the thin film 3 the silicon single crystal thin film transistor of SOI structure is formed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device manufactured on an insulating substrate.

[Conventional technology]

Insulating substrates are an effective means of overcoming signal transmission delays caused by various stray capacitances, such as parasitic capacitance existing in semiconductor elements fabricated on semiconductor single crystal substrates and wiring capacitance existing between wiring and substrate. MO8tNT (Metal-Oxle-
8emiconctor? 1eld'1ffe
ct, Tr), etc., the excess semiconductor thin film was removed or inactivated, and wiring was formed on the insulator substrate using an SO process (5emiconductor).
On Engineering 5uxator) There is a technology. Conventional S
O technology includes SOS (5ilicon on 8ap), which is a silicon single crystal thin film buried on the sapphire surface.
hive) technology, or by embedding polycrystalline silicon on a quartz substrate and turning it into a single crystal by heating, as shown in Proceedings of the Japan Society of Applied Physics, 1983, p-V-5, or by heating it to form a single crystal. SO technology (5ilicon on Ins-u) that crystallizes polycrystalline silicon on a silicon oxide film by laser annealing like
lator) technology was available.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional technology has the following problems.

In other words, those using sapphire as an insulator are unsuitable for use in general-purpose semiconductor devices because the sapphire substrate is expensive; those using a silicon oxide film as an insulator have the above-mentioned SO structure. In addition to its advantages, it is also expected to be applied to three-dimensional integrated circuits. However, new techniques such as laser annealing are required to grow single-crystal silicon on a silicon oxide film. Furthermore, the throughput of laser annealing is poor and it takes a long time to turn polycrystals over the entire surface into single crystals. Further, since single crystallization progresses on the surface of the amorphous silicon oxide film, many dislocations, lattice defects, etc. occur, resulting in problems such as poor crystallinity.

The present invention is intended to solve these problems.The purpose of the present invention is to fabricate a semiconductor substrate with an SOI structure that has good single crystallinity at low cost, and has low stray capacitance and high-speed response. The purpose of the present invention is to provide a semiconductor element with high efficiency and which can be miniaturized.

[Means for solving problems]

The insulating substrate used in the semiconductor device of the present invention is made of a silicon single crystal substrate and a potassium phosphide insulating semiconductor single crystal thin film that is lattice matched with the silicon single crystal substrate and has a larger forbidden band width than the silicon single crystal. It is characterized by becoming.

[Effect]

According to the above configuration of the present invention, since a commonly used silicon single crystal substrate is used as the substrate, it is cheaper than a sapphire substrate or the like. Since a gallium phosphide single crystal thin film that has good lattice matching with silicon single crystal is used as the insulator, a silicon single crystal with better crystallinity than single crystal silicon on silicon oxide can be grown on its surface. Gallium phosphide has a wide forbidden band, so it can be an insulator with very high resistivity. Furthermore, the melting point of gallium ninetonide is 14
Since the temperature is 67° C., which is as large as silicon, common silicon planar technology can be used.

〔Example〕

FIG. 1 shows a single-crystal silicon thin film transistor having an SO structure manufactured according to the present invention. 1, for example, the plane direction is (
100) and an impurity concentration of about 1×101′ scratch −3. 2 is a semi-insulating gallium phosphide single crystal thin film epitaxially grown on the surface of the single crystal silicon substrate. The lattice structure of gallium phosphide single crystal is a zinc oxide structure, and the lattice constant is 5.4495X at room temperature.
It is.

On the other hand, a silicon single crystal has a diamond structure and a lattice constant of s, 4s monoatonic at room temperature. These two types of crystals have a difference in lattice constant of only about 0.5%, so they are sufficiently lattice matched, and although they are different types of crystals, phosphorus with good crystallinity can be placed on a silicon single crystal substrate. A gallium oxide single crystal thin film is obtained. Methods for epitaxial growth of gallium phosphide include liquid phase growth, vapor phase growth, and molecular beam epitaxial growth. Among the vapor phase epitaxy methods, metal organic vapor phase epitaxy has the characteristic that crystals with good film quality can be obtained with good mass production. The forbidden band width of gallium phosphide single crystal is at room temperature,
25@V, and if there is no impurity mixed in, the carrier density that contributes to conduction would be extremely low, so the resistivity would be 1010 Ω or more, and it could be treated as a perfect insulator. The gallium phosphide single crystal thin film 2 in FIG. 1 has a resistivity sufficient to be treated as an insulator. The film thickness is from several hundred nanometers to several tens of microns. 3 in Figure 1
is a P-type silicon single crystal thin film formed on the surface of the gallium phosphide single crystal thin film. A vapor phase growth method or a molecular beam epitaxial method is suitable for the epitaxial growth method of this film. The impurity concentration of the silicon single crystal thin film of No. 5 is 1014 ~
10"cIr" is suitable, and the film thickness is from several hundred nanometers to several microns. 4 is an n-type layer formed in the P-type silicon single crystal thin film by thermal diffusion method or ion implantation method;
This corresponds to the source and drain portions of B11BT. 5
6 is a gate insulating film made of an insulator such as a silicon oxide film;
1 is a gate electrode made of metal, silicide, polysilicon, etc.; 7 is an insulating film for a badge page on the semiconductor surface; 8 is a gold electrode and an onion that can make ohmic contact with the transistor.

FIG. 2 shows an energy band diagram near the interface between a gallium phosphide single crystal thin film and a silicon single crystal thin film in the semiconductor device shown in FIG.

FIG. 2(4) is an energy band diagram near the interface between gallium phosphide and p-type silicon. At the heterojunction interface, band bending occurs on either side, with electrons accumulating on the gallium phosphide side and holes on the P-type silicon side. Figure 2 Cb)
In the energy band diagram near the interface between gallium phosphide and n+ type silicon, the band bending at the 0 heterojunction becomes steeper than that at (α), and more carriers are accumulated on both sides of the interface.

Figure 3 is based on the energy level diagram shown in Figure 2,
MO8 of the embodiment shown in FIG. ] This shows the carrier distribution for lCT. 1 to B in FIG. 3 are the same as those explained in FIG. 1. Reference numeral 9 denotes a surface inversion layer formed by applying a gate voltage 'Va, which becomes a channel portion. In a silicon single crystal thin film, electrons and holes exist on both sides via a depletion layer formed by forming a heterojunction. However, only the electrons gathered on the silicon surface side are involved in the transistor operation, and the holes and electrons near the heterojunction are not involved in the transistor operation, so the MOSFET manufactured in this way operates perfectly. The electron concentration induced on the gallium phosphide side of the heterojunction is very low, especially directly under the p-type silicon, so the resistance is large near the gallium phosphide heterointerface, and the source and drain are sufficiently isolated. is being done.

Consider the parasitic capacitance in the source or drain portion. Capacitance between the silicon substrate and the source or drain can be ignored because the intermediate gallium phosphide layer is sufficiently thick. Although the depletion layer capacitance in silicon induced by the formation of a heterojunction is large, since the hole side is electrically 70-tinged, charge transfer to the depletion layer does not occur much and the capacitance is equivalently small. It's fine. Therefore, the parasitic capacitance at the source and drain is reduced by the MO
It is smaller than in the case of 5UET.

The capacitance between the wiring and the substrate, that is, the wiring layer ffi i2
Since the specific resistance of the substrate is very large, it is equivalently small.

As mentioned above, based on the embodiment shown in FIG.
OSFET' reduces parasitic capacitance and wiring capacitance.

If you do that, you won't be able to get something that can respond quickly.

FIG. 4 shows an example of a three-dimensional structure MO3-11iT using a gallium phosphide crystal thin film as an interlayer insulating film.

10 is a p-type silicon single crystal substrate, and 11 is an n+ type diffusion layer which becomes a source and drain region. 12 is a gate insulating film, 13 is a gate electrode, and 14 is a surface passivation insulating film. Bulk MO5FET with 10 to 13
is formed. Reference numeral 15 denotes a gallium phosphide single crystal thin film grown using the silicon single crystal exposed on the surface of a silicon single crystal substrate as a ridge. The crystal growth method and film quality are the same as those in the example shown in FIG. 16 is bulk MO
These are upper and lower conductors formed by diffusing sulfur or the like into gallium phosphide in order to bring out the electrodes of the 8IFET to the gallium phosphide surface. 17 to 22 correspond to those 5 to 8 shown in FIG. 1, and the upper layer silicon single crystal thin film MO8
? Form ICT. 25 is bulk MO3? This is a wiring layer that makes ohmic contact with the electrode in gallium phosphide drawn out from the ET and can be connected to the electrode of the thin film MO31FET.

If a three-dimensional device having a structure as shown in FIG. 4 is constructed using the present invention, an increase in the degree of integration can be expected.

The same effect can be obtained by using a bipolar transistor, an S-T, a resistor, a diode, etc. in place of MO8FE'l' in each embodiment.

〔Effect of the invention〕

Since a silicon single crystal substrate is used in SO technology, a substrate with a large area can be obtained at low cost. Since gallium phosphide, which can be epitaxially grown relatively easily, is used as the insulator, an insulator with good spinnability can be obtained.

Therefore, a silicon single crystal thin film can be easily grown without laser annealing or heat treatment. Gallium phosphide has a melting point as high as that of silicon, so it can withstand the temperatures used in typical silicon planar technology. Since gallium phosphide is a semiisomer, a low-resistance conductive layer can be obtained by introducing impurities, and it can also be used as a conductor when bonding elements. This SO Koryuzou MOf9FET
Compared to MO+37 fabricated in bulk silicon, the drain capacitance and wiring capacitance are smaller, so high-speed response is better. The gallium phosphide SO structure of the present invention can be used as a three-dimensionally structured glabella insulating film.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a single-crystal silicon thin film transistor with an SO trench structure. FIGS. 2(a) and 2(j) represent energy level diagrams near the heterojunction between a gallium phosphide single crystal and a silicon single crystal thin film in the structure shown in FIG. 1. FIG. 5 is a diagram showing the carrier distribution of the SO-structured thin film transistor of FIG. 1, with reference to the energy level diagram of the FG2 diagram. Figure 4 shows a three-dimensional structure MOI9? using a gallium phosphide single crystal thin film as an insulating film between the eyebrows. An example of ICT is shown. 1... Silicon single crystal substrate 2... Gallium phosphide semi-insulating single crystal thin film 17
．． 3...P-type silicon single crystal thin film 18.4...
...N-swelled diffusion layer (source, drain part 19.5...
...Gate insulating film 20.6...Gate electrode 21.7...Surface badge 1-layer film 22.8
...Metal electrode? --------・Surface inversion layer (channel part) 10・
...Silicon single crystal substrate 11・"""N swelling diffusion layer (source, drain part) 12-
...Gate insulating film 13...Gate electrode 14...Surface pattern w:/J[15...
...Gallium phosphide semi-insulating single crystal group 16...
... Upper and lower conductors 23 ... Electrode/wiring layer and above

Claims (2)

[Claims] (1) In a semiconductor device using a semiconductor substrate having a silicon single crystal thin film on an insulator substrate, the insulator substrate is
A semiconductor device comprising a silicon single crystal substrate and a semi-insulating semiconductor single crystal thin film that is lattice matched to the silicon single crystal substrate and has a larger forbidden band width than the silicon single crystal. (2) The semiconductor device according to claim 1, wherein a potassium phosphide single crystal thin film is used as the semi-insulating semiconductor thin film.