JPS61100154U - - Google Patents

Info

Publication number
JPS61100154U
JPS61100154U JP18457384U JP18457384U JPS61100154U JP S61100154 U JPS61100154 U JP S61100154U JP 18457384 U JP18457384 U JP 18457384U JP 18457384 U JP18457384 U JP 18457384U JP S61100154 U JPS61100154 U JP S61100154U
Authority
JP
Japan
Prior art keywords
integrated circuit
electrode
monolithic integrated
resistor
inductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18457384U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0412693Y2 (pl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18457384U priority Critical patent/JPH0412693Y2/ja
Publication of JPS61100154U publication Critical patent/JPS61100154U/ja
Application granted granted Critical
Publication of JPH0412693Y2 publication Critical patent/JPH0412693Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)
JP18457384U 1984-12-05 1984-12-05 Expired JPH0412693Y2 (pl)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18457384U JPH0412693Y2 (pl) 1984-12-05 1984-12-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18457384U JPH0412693Y2 (pl) 1984-12-05 1984-12-05

Publications (2)

Publication Number Publication Date
JPS61100154U true JPS61100154U (pl) 1986-06-26
JPH0412693Y2 JPH0412693Y2 (pl) 1992-03-26

Family

ID=30742059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18457384U Expired JPH0412693Y2 (pl) 1984-12-05 1984-12-05

Country Status (1)

Country Link
JP (1) JPH0412693Y2 (pl)

Also Published As

Publication number Publication date
JPH0412693Y2 (pl) 1992-03-26

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