JPS61100149U - - Google Patents

Info

Publication number
JPS61100149U
JPS61100149U JP18513584U JP18513584U JPS61100149U JP S61100149 U JPS61100149 U JP S61100149U JP 18513584 U JP18513584 U JP 18513584U JP 18513584 U JP18513584 U JP 18513584U JP S61100149 U JPS61100149 U JP S61100149U
Authority
JP
Japan
Prior art keywords
integrated circuit
wiring board
semiconductor device
printed wiring
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18513584U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18513584U priority Critical patent/JPS61100149U/ja
Publication of JPS61100149U publication Critical patent/JPS61100149U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例に係る半導体装置の
外観斜視図、第2図は第1図のA―A線に沿う縦
断面図、第3図は第2図矢視B部の部分拡大図、
そして、第4図a,bは各々従来例を示す外観斜
視図である。 1…接続端子、5…印刷配線基板、6…半導体
集積回路パツケージ、7…接続部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 集積回路の印刷配線基板への接続部に、着脱可
    能なソケツト状の接続端子を取付けてなる半導体
    装置。
JP18513584U 1984-12-06 1984-12-06 Pending JPS61100149U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18513584U JPS61100149U (ja) 1984-12-06 1984-12-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18513584U JPS61100149U (ja) 1984-12-06 1984-12-06

Publications (1)

Publication Number Publication Date
JPS61100149U true JPS61100149U (ja) 1986-06-26

Family

ID=30742614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18513584U Pending JPS61100149U (ja) 1984-12-06 1984-12-06

Country Status (1)

Country Link
JP (1) JPS61100149U (ja)

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