JPS6098867A - Protecting circuit of transistor chopper - Google Patents
Protecting circuit of transistor chopperInfo
- Publication number
- JPS6098867A JPS6098867A JP58207047A JP20704783A JPS6098867A JP S6098867 A JPS6098867 A JP S6098867A JP 58207047 A JP58207047 A JP 58207047A JP 20704783 A JP20704783 A JP 20704783A JP S6098867 A JPS6098867 A JP S6098867A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- voltage
- comparator
- main transistor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Control Of Direct Current Motors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、トランジスタチョッパくの制御装置、特に主
トランジスタの保の回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for a transistor chopper, and more particularly to a main transistor control circuit.
直流モータ駆動の・電気車などモータの速度制御にトラ
ンジスタチョッパを使用する場合、主トランジスタの保
護回路として従来から過電流制限回路が設けられている
。この保護回路は第１図に示す構成にされる。直流モー
タ１のアーマチュアＩＡとフィールドＩＢと主トランジ
スタ２の直列接続回路を形成してバッテリ等の直流電源
３に接続し、主トランジスタ２のオン・オフ比（導通率
）制御によって直流モータ１への平均電圧を制御して速
度制御するにおいて、主トランジスタ２に直列に設ける
シャント抵抗４でトランジスタ電流を検出し、該゛直流
が一定値を越えるときに主トランジスタ２のオン・オフ
比を速度指令に拘らず一定値にｉＤＵ限するようにして
いる。When a transistor chopper is used to control the speed of a motor such as a DC motor-driven electric vehicle, an overcurrent limiting circuit is conventionally provided as a protection circuit for the main transistor. This protection circuit has the configuration shown in FIG. A series connection circuit of the armature IA and field IB of the DC motor 1 and the main transistor 2 is formed and connected to a DC power source 3 such as a battery. In speed control by controlling the average voltage, the transistor current is detected by a shunt resistor 4 installed in series with the main transistor 2, and when the DC current exceeds a certain value, the on/off ratio of the main transistor 2 is used as a speed command. Regardless, the iDU is limited to a constant value.
図中、制御回路は発振器５の一定周期出力で抵抗６とコ
ンデンサ７の充電回路を周期的に放電させ、コンデンサ
７の鋸歯状波電圧をアクセルの踏み込み量等に連動する
ポテンショメーク８の出力電圧とを比較器９で比較し、
比較器９の出力オン・オフ比をポテンショメーク８の出
力に対応させ、この出力で電界効果トランジスタ１０を
オン参オンさせて王トランジスタ２をベースドライブす
る。In the figure, the control circuit periodically discharges a charging circuit consisting of a resistor 6 and a capacitor 7 using a constant periodic output from an oscillator 5, and changes the sawtooth wave voltage of the capacitor 7 to the output voltage of a potentiometer 8 that is linked to the amount of accelerator depression, etc. Compare with comparator 9,
The output on/off ratio of the comparator 9 is made to correspond to the output of the potentiometer 8, and this output turns on the field effect transistor 10 to drive the base of the main transistor 2.
保護回路は、シャント抵抗４の検出電圧を品入力インピ
ーダンスバツファ１１で取出し、このバッファ１１の出
力が比＃！器１２の比奴基準（設定値）／ａ′越えたと
ぎに該比較器１２のハイレベル出力で抵抗・２進してコ
ンデンサ７Ｊ−尤′αする４成にしている。従って、ト
ランジスタ２に過電流が流れようとすると、比較器１２
の出力でコンデンサ７の充電を早め、結果的しし主トラ
ンジスタ２０オン・オフ比を下げて過電流をｆｉｉｌｌ
限する。１３は制御型ひ、１４はフライホイールダイオ
ードである。The protection circuit takes out the detected voltage of the shunt resistor 4 with a product input impedance buffer 11, and the output of this buffer 11 is the ratio #! When the ratio reference (set value) /a' of the comparator 12 is exceeded, the high level output of the comparator 12 is converted into a resistor and binary to form a 4-component capacitor 7J - 4'. Therefore, when an overcurrent is about to flow through transistor 2, comparator 12
The output speeds up the charging of the capacitor 7, and as a result lowers the on/off ratio of the main transistor 20 to prevent overcurrent.
limit 13 is a control type diode, and 14 is a flywheel diode.
このように保護回路として過晟流制限回路を設けること
は、主トランジスタ２を過ｉａ流から保護できるが、主
トランジスタ２の完全な採出にはなり得７よいもので、
主トランジスタ２がその不飽和動作で熱破壊される處れ
があった。特に、Ｉｔ ＆ｊ、 ３としてバッテリを使
う場合、バッテリの充電不良や放電過多によってバッテ
リ重圧が異當に低下づ゛るとぎに熱破壊を起すＪｉすれ
があった。即ち、電ぶ３の電圧低下によりトランジスタ
１０を通した主トランジスタ２のオンベース電流が不足
して主トランジスタ２が不飽和領域で動作し、オン時に
もそのコレクタ・エミッタ間電圧ＶＣＥが高くなってコ
レクタ電圧Ｉｃとの積になる熱損失Ｐが過大になり、主
トランジスタ２の熱破壊になる。Providing the overcurrent limiting circuit as a protection circuit in this way can protect the main transistor 2 from overcurrent, but it is not a good idea to completely eliminate the main transistor 2.
There was a risk that the main transistor 2 would be thermally destroyed due to its unsaturated operation. In particular, when a battery is used as the It&J, 3, there is a risk of thermal breakdown when the battery pressure decreases excessively due to insufficient charging or excessive discharging of the battery. That is, due to the voltage drop in the voltage 3, the on-base current of the main transistor 2 through the transistor 10 is insufficient, and the main transistor 2 operates in the unsaturated region, and its collector-emitter voltage VCE increases even when it is on. The heat loss P, which is the product of the collector voltage Ic, becomes excessive, resulting in thermal destruction of the main transistor 2.
本発明は上述までの事情に鑑みてなされたもので、屯諒
′４圧の低下による主トランジスタの熱破壊を確実、容
易に防止できる保護回路を提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a protection circuit that can reliably and easily prevent thermal destruction of the main transistor due to a drop in the voltage.
本発明は、主トランジスタのオン期間のみそのコレクタ
電圧を検出し、この電圧が設定値を越えるときに主トラ
ンジスタのオン期間を絞るようそのトンイア゛１Ｊ号の
オン期間を１ｉｌＪ限することを特徴とする。The present invention is characterized in that the collector voltage is detected only during the ON period of the main transistor, and when this voltage exceeds a set value, the ON period of the main transistor is limited to 1ilJ to narrow down the ON period of the main transistor. do.
第２図は本発明の一実論例を示す回路図を示し、第１図
と同じものあるいは同じ性能を有するものは同一符号で
示す。主トランジスタ２のコレクタ電圧は抵抗２１を通
して比較器２２の比較入力される。比較器２２はその比
較基準電圧を越える電圧入力で比較器１２の出力とは論
理相関係を持ってコンデンサ７を充電する出力を得る。FIG. 2 shows a circuit diagram illustrating a practical example of the present invention, and parts that are the same as those in FIG. 1 or have the same performance are designated by the same reference numerals. The collector voltage of the main transistor 2 is input through a resistor 21 to a comparator 22 for comparison. Comparator 22 obtains an output that charges capacitor 7 with a logical correlation with the output of comparator 12 at a voltage input exceeding its comparison reference voltage.
一方、比較器９の出力信号を入力とラーるインターロッ
ク回路２３は主トランジスタ２をオフドライブするＮＪ
１信号を得て鈑信号期間にはタイオード２４を通して比
較器２２の入力を基卑電位に強制する。On the other hand, an interlock circuit 23 which receives the output signal of the comparator 9 as an input turns off the main transistor 2.
1 signal is obtained, and during the blank signal period, the input of the comparator 22 is forced to the base potential through the diode 24.
こうした回路により、トランジスタ２０オン時のコレク
タ電圧が抵抗２工を通して比較器２２で監視され、コレ
クタ電圧が比較器２２０′−圧を越エルトコンデン？７
の充電を早め、主トランジスタのオン期間をポテンショ
メーク８の制御電圧に拘らず一定値以下に１ｂｌｌ Ｐ
Ｈづる。これにより、主トランジスタ２の導通率が下げ
られ、その電力損失が低くなって熱破廐を防止する。With such a circuit, the collector voltage when the transistor 20 is on is monitored by the comparator 22 through two resistors, and the collector voltage exceeds the voltage of the comparator 220'. 7
Accelerates the charging of the main transistor and keeps the on period of the main transistor below a certain value regardless of the control voltage of the potentiometer 8.
Hzuru. This lowers the conductivity of the main transistor 2, lowers its power loss, and prevents thermal breakdown.
第３図はインターロック回路２３の一実施例を示す。比
較器２５は比較器９の出力電圧を逆方向ダイオード２６
を通して比較入力とし、この比較人力には抵抗ＲＡとコ
ンデンサＣＡの時定数回路が接続される。比較器２７は
比較！ａ２８の比較入力にされ、比較器２８の出力がイ
ンターロック出力とし−（ダイオード２４に接続される
。こり給酸において、比較器９の出力がローレベルにな
る主トランジスタ２のオフ期間にはダイオード２６を通
してコンデンサＣＡが放電されており、比較器２５の出
力がローレベルになって比較器２７の出力もローレベル
になり、ダイオード２４を通して主トランジスタ２のコ
レクタ電圧検出信号を基準電位に強制して比較器２２へ
の入力をロックする。FIG. 3 shows one embodiment of the interlock circuit 23. A comparator 25 connects the output voltage of the comparator 9 to a reverse diode 26.
A time constant circuit including a resistor RA and a capacitor CA is connected to this comparison input. Comparator 27 compares! A28 is used as a comparison input, and the output of the comparator 28 is used as an interlock output. Capacitor CA is discharged through 26, the output of comparator 25 becomes low level, and the output of comparator 27 also becomes low level, forcing the collector voltage detection signal of main transistor 2 to the reference potential through diode 24. Lock the input to comparator 22.
この状態から、比較器９の出力がハイレベルに変るとき
、比較器２５の人力は抵抗ＲＡとコンデンサＣＡの時定
数で少しの遅れを持ってハイレベルになり、比較器２７
の出力もこの遅れを持ってハイレベルになり、主トラン
ジスタ２のコレクク′屯圧信号を比較器２２の比較人力
にする。このタイムチャート？：第４図にボし、Ｔａが
遅れ時間である信号を比較器２２り比較人力にする。From this state, when the output of comparator 9 changes to high level, the human power of comparator 25 becomes high level with a slight delay due to the time constant of resistor RA and capacitor CA, and comparator 27
The output of the main transistor 2 also becomes high level with this delay, and the collector's pressure signal of the main transistor 2 is used as the comparison signal of the comparator 22. This time chart? : As shown in FIG. 4, the signal where Ta is the delay time is input to the comparator 22 for comparison.
従って、主トランジスタ２０オン期間の４のコレクタ１
Ｌ圧監視になり、しかも比戟開妃を少し遅らせてドライ
ブ悟号と主トランジスタ２の笑除のオン動作との時間遅
れを含めた確実な監視を図っている。Therefore, the collector 1 of the main transistor 20 on-period 4
The L pressure is monitored, and the Higeki Kaihi is delayed a little to ensure reliable monitoring, including the time delay between the turn-on operation of the drive Gogo and the main transistor 2.
以上のと２９、本発明によれは、主トシンジうりの過電
流保設に加えてオン時コレクタ電圧の上昇で熱破壊され
ることから保菌でき、電源３の電圧降下による故障を未
然に防ぐことができる効果がある。また、（１′ケ成上
は過電流保護回路による尋通率絞り制御を利用でき、少
ない回路素子によって実現される。According to the above and 29, according to the present invention, in addition to overcurrent preservation of the main power supply, it is thermally destroyed by the rise in collector voltage when turned on, so that it is possible to preserve the battery, and to prevent failures due to voltage drops in the power supply 3. There is an effect that can be done. In addition, the (1' configuration) allows the use of an overcurrent protection circuit to control the throughput ratio, and is realized with a small number of circuit elements.
第１図は従来の係数回路図、第２図は本発明の一実施例
を示す回路図、第３図は第２図におけるインターロック
回路の一実施例を示す回路図、第４図は第３図の動作説
明のためのタイムチャートである。
１・・・直流モータ、２・・・主トランジスタ、３°゛
°電諒、４・・・シャント抵抗、５・・・発振器、８・
・・ポテンショメータ、９，１２，２２，２５，２７・
・・比較器、１１・・・バッファ、２３・・・インター
ロック回路。Fig. 1 is a conventional coefficient circuit diagram, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a circuit diagram showing an embodiment of the interlock circuit in Fig. 2, and Fig. 4 is a circuit diagram showing an embodiment of the interlock circuit in Fig. 2. 3 is a time chart for explaining the operation of FIG. 3. FIG. DESCRIPTION OF SYMBOLS 1... DC motor, 2... Main transistor, 3°゛° electrical connection, 4... Shunt resistor, 5... Oscillator, 8...
・Potentiometer, 9, 12, 22, 25, 27・
... Comparator, 11... Buffer, 23... Interlock circuit.
Claims (1)
に応じたオン・オフ比でドライブするトランジスタチョ
ッパにおいて、上記主トランジスタのオン電流が設定値
を越えるときに該主トランジスタのオン期間を制限する
過電流制限回路と、上記主トランジスタのオン時コレク
タ電圧が設定値を越えるときに該主トランジスタのオン
期間を制限して該主トランジスタの熱破壊を防止する回
路とを備えたことを特徴とするトランジスタチョッパの
保護回路。In a transistor chopper that drives a main transistor connected in series with a DC motor with an on/off ratio according to a speed command, an overcurrent that limits the on period of the main transistor when the on-current of the main transistor exceeds a set value. A transistor chopper comprising: a limiting circuit; and a circuit that limits the on-period of the main transistor to prevent thermal breakdown of the main transistor when the collector voltage of the main transistor exceeds a set value. protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58207047A JPS6098867A (en) | 1983-11-04 | 1983-11-04 | Protecting circuit of transistor chopper |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58207047A JPS6098867A (en) | 1983-11-04 | 1983-11-04 | Protecting circuit of transistor chopper |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6098867A true JPS6098867A (en) | 1985-06-01 |
| JPH056425B2 JPH056425B2 (en) | 1993-01-26 |
Family
ID=16533322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58207047A Granted JPS6098867A (en) | 1983-11-04 | 1983-11-04 | Protecting circuit of transistor chopper |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6098867A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62175263A (en) * | 1986-01-30 | 1987-07-31 | Hitachi Ltd | Motor-driven power steering control device |
| JPS63190592A (en) * | 1987-02-03 | 1988-08-08 | Matsushita Electric Ind Co Ltd | Safeguard circuit |
-
1983
- 1983-11-04 JP JP58207047A patent/JPS6098867A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62175263A (en) * | 1986-01-30 | 1987-07-31 | Hitachi Ltd | Motor-driven power steering control device |
| JPS63190592A (en) * | 1987-02-03 | 1988-08-08 | Matsushita Electric Ind Co Ltd | Safeguard circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH056425B2 (en) | 1993-01-26 |
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