JPS6098596A - Memory access method - Google Patents

Abstract

PURPOSE:To reduce power consumption by generating an indication signal only immediately before memory access and setting up the potential of a data line to a prescribed value. CONSTITUTION:When the contents of a local memory 12 are to be stored in a read data register 13 by reading out a microinstruction from a control memory 10 and accessing the local memory 12 on the basis of the indication a pre-charge indication signal is applied to a pre-charge indication terminal B of the local memory 12 when the operation code of the microinstruction sent from the control memory 10 is decoded by a decoder 14 and ''READ'' is decided and detected as the decoded result. Consequently, the 1st pulse signal is sent from a pre- charge pulse generating circuit 1, a data line 4 is set up to low potential and a data line 5 is set up to high potential. Then, the 2nd pulse signal is sent from the pre-charge pulse generating circuit 1 to a signal line 3. The 2nd pulse shorts between the data lines 4, 5 and both the data lines 4, 5 are set up to a fixed potential.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory access method for an electronic computer, and particularly to a memory access method that enables memory access with low power consumption.

[Background of the invention]

A method in which memory is accessed after the potential of a data line through which data from a memory cell is output is set to a constant potential in advance is called a precharge method. FIG. 1 shows an example of the configuration of an internal circuit of a memory element using this precharge method. In the figure, when a precharge instruction signal is first input to terminal B, a first pulse is sent from precharge pulse generation circuit 1 to signal line 2. This turns the switch Sl and the switch S2 on and off, causing the data line 4 to be at a low potential (OV in this figure) and the data line 5 to be at a high potential (5V in this figure).
) is set. Next, precharge pulse generation circuit 1
A second pulse is then sent to the signal line 3. This second pulse turns the switch S5 on and off, momentarily shorting the data line 4 and the data line 5. When the data lines 4 and 5 are short-circuited, charge is discharged from the data line 5 to the data 84, and the voltage is neutralized to a predetermined intermediate level (in this example, the capacitance of the data lines 4 and 5 is equal, so it is 2.5V). Become),,
After that, an address is input to the terminal A group, decoded by the address decoder 8, and the corresponding address [9 is activated. This activation causes switch 33. Switch S4 is closed and data line 4. The potential of the data line 5 becomes a potential slightly higher than the predetermined potential or a potential slightly lower than the predetermined potential depending on the amount of charge accumulated in the memory cell 6. This potential is sensed and amplified by the sense amplifier 7, and the memory cell 6
The data value of is output from output terminal C.

When using the above-mentioned precharge type memory, conventionally, as shown in the timing chart of FIG. 3, a precharge instruction signal Pr was sent out from the main body every cycle by a microinstruction MC, regardless of memory access. However, in this conventional method, there are cases where there is no memory access to the data storage register DR by the address signal Ad.

Since electric charges are moved and power is consumed during precharging in each cycle, there is a drawback that power is wasted.

(Object of the Invention) The present invention has been made in view of the above-mentioned points, and therefore, it is an object of the present invention to provide a low power consumption memory access method in which precharging is performed only immediately before memory access.

[Summary of the invention]

The main point of the present invention is that in a precharge type memory,
When a certain memory is accessed and data is read by an instruction, a precharge instruction signal is generated from the instruction's memory access instruction to the sending of the memory address, and precharging is performed only immediately before the memory access. It is in.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 2 is a block diagram showing an embodiment of the memory access method according to the present invention, particularly showing the flow of control signals and data when reading from a local memory under microinstruction control. In the figure, 10 is a control memory;
11 is a microinstruction control logic circuit, and 12 is a local memory consisting of a work register memory. The local memory 12 is a memory having the same configuration as the internal circuit of the memory element shown in FIG.

Now, consider the case where a microinstruction is read from the control memory IO, the local memory 12 is accessed according to the instruction, and the microinstruction is stored in the read data register 13. The operation code of the microinstruction sent from the control memory 10 is decoded by the decoder 14, and is sent to the precharge instruction terminal B of the local memory 12.
As a result, when "read" is determined/detected, a precharge instruction signal is given. As a result, as explained in the operation of FIG. 1, the precharge pulse generation circuit l
A first pulse signal is sent from , and the data line 4 is set to a low potential and the data line 5 is set to a high potential. Next, a second pulse is sent from the precharge pulse generation circuit 1 to the signal line 3.

This second pulse short-circuits data line 4 and data line 5, and sets both data lines 4 and 5 to a constant potential. In other words, the local memory 12 is precharged only when the memory is accessed. After precharging, an address signal is sent from the address register 15 to the local memory 12 to access the memory. The microinstruction MC and the precharge instruction signal Pr from the decoder 14
, a timing chart of the address signal Ad from the address register 15 is shown in FIG. As clearly shown in the figure, the precharge signal Pr is sent only in the cycle in which the microinstruction Me is issued. In the above example, only reading was taken up, but for writing, there is no need to precharge before writing.

Although the above embodiment has been described using a local memory consisting of a work register memory as an example, it is obvious that the present invention is not limited to such a memory.

As described above, according to the above embodiment, since precharging is performed only immediately before memory access, compared to the conventional method of sending out a precharge instruction signal every cycle regardless of memory access, the computer memory The power consumption required for precharging is extremely low. Furthermore, the cooling device can be made smaller due to the reduction in heat generated due to lower power consumption, and the reduction in noise associated with the smaller cooling device can also be achieved.

Furthermore, as computers become more compact and highly integrated precharge type memories are used more frequently, the above embodiments are expected to be more effective.

〔Effect of the invention〕

As explained above, the memory access method according to the present invention issues an instruction signal only immediately before memory access to set the potential of the data line to a predetermined value, so the power consumption is lower than that of the conventional method. It has the excellent effect of being able to

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the internal circuit of a precharge type memory element, Figure 2 is a block diagram showing the flow of control signals and data when reading local memory using a microinstruction, and Figure 3 is a block diagram showing the flow of control signals and data when reading local memory using a microinstruction. Timing diagram of memory access method FIG. 4 is a timing diagram of the memory access method according to the present invention. 1... Pulse generation circuit for precharge, 2, 3...
Precharge pulse signal line, 4, 5...data line, 6...memory cell, 7...sense amplifier, 8...
・Address decoder, 9...Address line, 10...
Control memory, 11... Micro instruction control logic circuit, 12... Local memory, 13... Data register 14... Micro instruction decoder, 15...
・Local memory address register 5

Claims (1)

[Claims] (1) In a memory access method in which the potential of the data line through which the data of the memory cell is outputted is set to a constant voltage in advance, and then the memory access is performed, a signal that starts the memory access is used to generate the data immediately before the memory access. A memory access method characterized by setting the line potential to a constant potential.