JPS609833Y2 - electronic timer device - Google Patents
electronic timer deviceInfo
- Publication number
- JPS609833Y2 JPS609833Y2 JP16054775U JP16054775U JPS609833Y2 JP S609833 Y2 JPS609833 Y2 JP S609833Y2 JP 16054775 U JP16054775 U JP 16054775U JP 16054775 U JP16054775 U JP 16054775U JP S609833 Y2 JPS609833 Y2 JP S609833Y2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- timer circuit
- discharge tube
- circuit
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electric Clocks (AREA)
- Measurement Of Predetermined Time Intervals (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
【考案の詳細な説明】
本考案は５０Ｈｚ或いは６０Ｈｚ等の低周波駆動信号に
よって電気的に時間設定を行うべくレジスタ及びメモリ
等を含むタイマ回路と、該タイマ回路による設定時間を
発光表示する放電管とを備えたタイマ装置に関するもの
である。[Detailed Description of the Invention] The present invention includes a timer circuit including a register, memory, etc. to electrically set time using a low frequency drive signal such as 50Hz or 60Hz, and a discharge tube that displays the set time by the timer circuit. The present invention relates to a timer device comprising:
上記放電管としてアノード電極及びカソード電極を有し
、ネオンガス等の励起発光ガスを密封入してなるガス放
電管を用いると、放電発光初期における前記の各電極間
の電圧−電流特性が不安定であり、放電開始時にスイッ
チングノイズを発生する。If a gas discharge tube is used as the discharge tube, which has an anode electrode and a cathode electrode and is sealed with an excited luminescent gas such as neon gas, the voltage-current characteristics between the electrodes at the initial stage of discharge light emission are unstable. Yes, switching noise is generated at the start of discharge.
そのため例えばタイマ回路の出力即ち前記の各電極のド
ライバをＭＯＳ （金属−酸化物一半導体）型電界効果
トランジスタ（ＦＥＴ）によって構成した場合、前記放
電管の放電開始時にこのスイッチングノイズがＭＯ３型
トランジスタに入力され、該トランジスタ即ちタイマ回
路が破壊されることとなり、従ってタイマ回路にガス放
電管を接続する手段が煩雑になると共に、希望するガス
放電管を選択的に使用できず、不経済であった。Therefore, for example, if the output of the timer circuit, that is, the driver of each of the electrodes described above, is configured with a MOS (metal-oxide-semiconductor) type field effect transistor (FET), this switching noise will be transmitted to the MO3 type transistor when the discharge tube starts discharging. The transistor, that is, the timer circuit, would be destroyed, and the means for connecting the gas discharge tube to the timer circuit would be complicated, and the desired gas discharge tube could not be selectively used, which was uneconomical. .
本考案は上記欠点に対処し、電圧−電流特性の良くない
ガス放電管を簡便に組込み得る様にしたものであり、以
下この一実施例を図面に基づいて詳述する。The present invention addresses the above-mentioned drawbacks and makes it possible to easily incorporate a gas discharge tube with poor voltage-current characteristics.One embodiment of this invention will be described in detail below with reference to the drawings.
図に示す如く商用電源（５０Ｈｚ或いは６０Ｈ２）を入
力する電源回路１を設けると共に、前記商用電源の周波
数によって電気的に時間設定を行う如く形成して成る集
積回路体（ＬＳＩ）製タイマ回路２を設け、例えば前記
電源回路１によって商用電源を半波整流して脈動電流に
変換し、これを低周波の駆動信号（時間進行パルス波）
としてライン３を介してタイマ回路２に入力せしめ、時
刻選定時間（目ざめ及び眠り時間等）を出力する複数の
レジスタを含むタイマ回路２を駆動する様に形成する。As shown in the figure, a power supply circuit 1 that inputs a commercial power source (50Hz or 60H2) is provided, and a timer circuit 2 made of an integrated circuit (LSI) formed to electrically set time according to the frequency of the commercial power source is provided. For example, the power supply circuit 1 half-wave rectifies the commercial power supply and converts it into a pulsating current, which is then used as a low-frequency drive signal (time-progressing pulse wave).
The signal is input to the timer circuit 2 via the line 3, and is formed to drive the timer circuit 2 including a plurality of registers that output time selection times (wake-up and sleep times, etc.).
また上記タイマ回路２の時間設定内容及び出力を調整す
るスイッチ回路４を設け、前記タイマ回路２中の複数レ
ジスタを進行制御して時刻並びに選定時間を出力制御す
る。Further, a switch circuit 4 is provided for adjusting the time setting contents and output of the timer circuit 2, and controls the progress of a plurality of registers in the timer circuit 2 to control the output of the time and selected time.
更にアノード電極用入力端子５・・・・・・並びに８字
状セブンセグメント形カソード電極用入力端子６・・・
・・・を有し且つアノード電極及びカソード電極をネオ
ンガス等の励起発光ガスと共に封入して成るガス放電管
７を設け、上記タイマ回路２のアノード出力（アノード
ドライバ）であるＭＯ３型トランジスタ８・・・・・・
に各端子５・・・・・・を接続し、且つアノード用電源
Ｅｌ、Ｅ２に各アノード端子５・・・・・・を接続する
と共に、前記タイマ回路２のカソード出力（カソードド
ライバ）であるＭＯ３型トランジスタ９・・・・・・に
前記カソード端子６・・・・・・も同様に接続し、且つ
各端子６・・・・・・に電源Ｅ３を抵抗１０・・・・・
・を介して印加して戊る。Furthermore, an input terminal 5 for the anode electrode, and an input terminal 6 for the 8-shaped seven segment cathode electrode.
A gas discharge tube 7 having an anode electrode and a cathode electrode sealed together with an excited light-emitting gas such as neon gas is provided, and an MO3 type transistor 8 serving as an anode output (anode driver) of the timer circuit 2 is provided.・・・・・・
, and connect each anode terminal 5 to the anode power supplies El and E2, and serve as the cathode output (cathode driver) of the timer circuit 2. The cathode terminal 6 is also connected to the MO3 type transistor 9 in the same way, and the power source E3 is connected to each terminal 6 through the resistor 10.
・Apply via .
また各トランジスタ９・・・・・・及び電源Ｅ３は各端
子６に保護抵抗１１・・・・・・を介して接続して威り
、前記の各端子６・・・・・・に発生する逆方向電流を
抵抗１０・・・・・・及び１１・・・・・・によって分
割し、該電流がトランジスタ９に流入するのを阻止する
様に形成して成る。Further, each transistor 9... and power source E3 are connected to each terminal 6 via a protective resistor 11... The resistors 10 and 11 divide the reverse current and are formed to prevent the current from flowing into the transistor 9.
そして前記の各トランジスタ８・・・・・・及び９・・
・・・・のゲートにタイマ回路２のレジスタ出力を公知
手段（図示省略）にて入力せしめると共に、各トランジ
スタ８・・・・・・及び９・・・・・・をタイマ回路２
の電源（Ｖｓｓ）に接続する。And each of the transistors 8... and 9...
The register output of the timer circuit 2 is input to the gate of the timer circuit 2 by known means (not shown), and each transistor 8... and 9... is connected to the timer circuit 2.
Connect to the power supply (Vss) of
而して各トランジスタ８・・・・・・及び９・・・・・
・のスイッチングによってアノード端子５・・・・・・
並びにカソード端子６・・・・・・との間即ちアノード
電極とカソード電極間に各電源Ｅｌ、Ｅ２．Ｅ３による
電位差を生じせしめ、時間を表わす数字を発光表示させ
るもので、例えばタイマ回路２の電極（Ｖｓｓ）を０ボ
ルト、電源Ｅ１を１５０ボルト、電源Ｅ２．Ｅ３を一５
０ボルトに設定し、上述の如く発光表示作動させる。Then, each transistor 8... and 9...
・By switching the anode terminal 5...
and between the cathode terminals 6..., that is, between the anode electrode and the cathode electrode, each power source El, E2. E3 generates a potential difference and displays a number representing time by emitting light.For example, the electrode (Vss) of the timer circuit 2 is 0 volts, the power source E1 is 150 volts, the power source E2 . E3 to 5
Set to 0 volts and activate the light emitting display as described above.
この場合、前記タイマ回路２において各トランジスタ８
・・・・・・及び９・・・・・・のゲートにドライブ信
号が出力されると共に、各トランジスタ８・・・・・・
及び９・・・・・・のスイッチングによって電源Ｅ１が
アノード端子５・・・・・・を介してアノード電極に印
加され、またカソード端子６・・・・・・を介してカソ
ード電極が電源Ｅ３に導通され、放電管７のアノード電
極及びカソード電極間に放電電位差が生じ、時間を表わ
す数字を発光表示するもので、この放電発光開始時、放
電管７の各電極間の電圧が電流に対して不規則変化し、
スイッチングノイズを発生する。In this case, each transistor 8 in the timer circuit 2
A drive signal is output to the gate of each transistor 8... and 9...
and 9..., the power source E1 is applied to the anode electrode via the anode terminal 5..., and the cathode electrode is applied to the power source E3 via the cathode terminal 6... conduction, a discharge potential difference is generated between the anode electrode and the cathode electrode of the discharge tube 7, and the number representing the time is displayed by light emission.When this discharge light emission starts, the voltage between each electrode of the discharge tube 7 is changes irregularly,
Generates switching noise.
そしてこのスイッチングノイズによって各トランジスタ
８・・・・・・及び９・・・・・・の電源（Ｖｓｓ）の
電圧が変化し、例えば０ボルトに設定している場合にこ
の値でなくなり、各トランジスタ８・・・・・・及び９
・・・・・・に逆方向の電流が流れる状態となるが、こ
の時、各抵抗１０・・・・・・及び１１・・・・・・に
よってその電流を分割し、減衰せしめることにより各ト
ランジスタ８・・・・・・及び９・・・・・・が破壊さ
れるのを阻止するものである。Then, due to this switching noise, the voltage of the power supply (Vss) of each transistor 8... and 9... changes, and if it is set to 0 volts, for example, it will no longer be this value, and each transistor 8...and 9
A current flows in the opposite direction to . . . , but at this time, each resistor 10 . This is to prevent the transistors 8... and 9... from being destroyed.
以上実施例に示す如く本考案に依ると、放電管７に発生
するスイッチングノイズを保護抵抗１１・・・・・・・
・・によって減衰するので、タイマ回路２を構成する各
トランジスタ８・・・・・・及び９・・・・・・の破壊
を防止でき、放電管７をタイマ回路２に簡潔に接続でき
、また電圧−電流特性の良くない放電管を簡易に組込む
ことができ、頗る経済的で且つ実用的である等の顕著な
効果を奏するものである。As shown in the embodiments above, according to the present invention, the switching noise generated in the discharge tube 7 is suppressed by the protective resistor 11...
Since the attenuation is caused by ..., it is possible to prevent the destruction of each transistor 8 ... and 9 ... which constitutes the timer circuit 2, and to connect the discharge tube 7 to the timer circuit 2 simply. It is possible to easily incorporate a discharge tube with poor voltage-current characteristics, and it has remarkable effects such as being extremely economical and practical.
図面は本考案の一実施例を示す電気回路図である。
２・・・・・・タイマ回路、７・・・・・・放電管、１
１・・・・・・保護抵抗。The drawing is an electrical circuit diagram showing an embodiment of the present invention. 2...Timer circuit, 7...Discharge tube, 1
1...Protective resistance.
Claims (1)
すると共に、前記電源回路１とタイマ回路２との間にス
イッチング回路４を介設し、前記タイマ回路２は複数の
トランジスタ訃・・、９・・・を備え、前記一方のトラ
ンジスタ８に放電管７のアノード電極用入力端子５・・
・を接続する一方、前記他方のトランジスタ９に放電管
７のカソード電極用入力端子６・・・を接続し、さらに
前記他方のトランジスタ９とカソード電極用入力端子６
との間には保護低抗１１を、また前記他方のトランジス
タ９と電源Ｅ３との間には別の低抗１０をそれぞれ接続
して、前記放電管７に発生する放電開始時のスイッチン
グノイズを前記各低抗９，１０によって減衰させてタイ
マ回路２に逆電流が印加されるのを阻止すべく威した電
子タイマ装置。A timer circuit 2 is connected to the commercial power supply circuit 1 via a line 3, and a switching circuit 4 is interposed between the power supply circuit 1 and the timer circuit 2, and the timer circuit 2 includes a plurality of transistors... 9..., and the input terminal 5 for the anode electrode of the discharge tube 7 is connected to the one transistor 8.
· are connected to the other transistor 9, and the cathode electrode input terminal 6 of the discharge tube 7 is connected to the other transistor 9, and the cathode electrode input terminal 6 is connected to the other transistor 9.
A protective low resistor 11 is connected between the other transistor 9 and the power source E3, and another low resistor 10 is connected between the other transistor 9 and the power source E3 to reduce switching noise generated in the discharge tube 7 at the start of discharge. An electronic timer device in which a reverse current is attenuated by the resistors 9 and 10 to prevent the reverse current from being applied to the timer circuit 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16054775U JPS609833Y2 (en) | 1975-11-27 | 1975-11-27 | electronic timer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16054775U JPS609833Y2 (en) | 1975-11-27 | 1975-11-27 | electronic timer device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5272455U JPS5272455U (en) | 1977-05-30 |
| JPS609833Y2 true JPS609833Y2 (en) | 1985-04-05 |
Family
ID=28639474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16054775U Expired JPS609833Y2 (en) | 1975-11-27 | 1975-11-27 | electronic timer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS609833Y2 (en) |
-
1975
- 1975-11-27 JP JP16054775U patent/JPS609833Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5272455U (en) | 1977-05-30 |
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