JPS6097646A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6097646A JPS6097646A JP58205659A JP20565983A JPS6097646A JP S6097646 A JPS6097646 A JP S6097646A JP 58205659 A JP58205659 A JP 58205659A JP 20565983 A JP20565983 A JP 20565983A JP S6097646 A JPS6097646 A JP S6097646A
- Authority
- JP
- Japan
- Prior art keywords
- epoxy resin
- semiconductor device
- coated
- polyimide resin
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、すぐれた耐湿特性を有するエポキシ樹脂封
止型半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an epoxy resin-encapsulated semiconductor device having excellent moisture resistance.
一般に、エポキシ樹脂封止型の半導体装置は、外部リー
ドとエポキシ樹脂との接着性が悪いため、高温高湿条件
下では著しく半導体特性を損なう。In general, epoxy resin-encapsulated semiconductor devices have poor adhesion between the external leads and the epoxy resin, which significantly impairs semiconductor characteristics under high temperature and high humidity conditions.
このため、外部リードに金、銀、ニッケルなどのことが
行われているが、満足な結果は得られていない。For this reason, attempts have been made to use gold, silver, nickel, etc. for external leads, but satisfactory results have not been obtained.
この発明は、上記の問題を解決して、高温高湿条件下に
おいてもすぐれた耐湿特性を有するエポキシ樹脂封止型
半導体装置を提供することを目的としてなされたもので
ある。The present invention has been made for the purpose of solving the above-mentioned problems and providing an epoxy resin-encapsulated semiconductor device having excellent moisture resistance even under high temperature and high humidity conditions.
すなわち、この発明は、少なくとも半導体素子と外部リ
ードとを構成要素とし、これら構成要素が結合されてエ
ポキシ樹脂で一体に被覆されてなるエポキシ樹脂封止型
半導体装置において、前記構成要素のうち少なくとも外
部リードの表面にこのリードのエポキシ樹脂被覆部から
外部引き出し部にまたがるポリイミド系樹脂被膜を形成
し、この被膜で上記両部を被覆したことを特徴とする半
導体装置に係るものである。That is, the present invention provides an epoxy resin-sealed semiconductor device that includes at least a semiconductor element and an external lead, and in which these components are combined and integrally coated with an epoxy resin. The present invention relates to a semiconductor device characterized in that a polyimide resin film is formed on the surface of the lead extending from the epoxy resin coated portion to the external extension portion of the lead, and both parts are covered with this film.
前記のポリイミド系樹脂被膜を形成するには、一般には
この被膜を形成すべき部分にポリイミド系樹脂の前駆体
の有機溶剤溶液を塗布し乾燥させたのち加熱してこの前
駆体をイミド化させる。To form the polyimide resin film, generally an organic solvent solution of a polyimide resin precursor is applied to the area where the film is to be formed, dried, and then heated to imidize the precursor.
ｒのを８月において田い＾冶７．ポ１１イミド秦桔Ｊｌ
ｌ旨の前駆体には、ジアミンとテトラカルボン酸二無水
物とを反応させて得られるポリアミド酸や、ジアミンと
テトラカルボン酸二無水物の誘導体（たとえば低級ジア
ルキルエステル）とを反応させて得られるポリアミド酸
誘導体のほか、ジアミンとともにジアミノアミドを併用
しこれらとテトラカルボン酸二無水物ないしその誘導体
とを反応させて得られるポリイミド−インインドロキナ
シリジオン樹脂の前駆体などが広く包含される。R's in August 7. Po11 Imide Qinqi Jl
The precursors mentioned above include polyamic acids obtained by reacting diamines with tetracarboxylic dianhydrides, and polyamic acids obtained by reacting diamines with derivatives of tetracarboxylic dianhydrides (for example, lower dialkyl esters). In addition to polyamic acid derivatives, precursors of polyimide-indoroquinasilidione resins obtained by using diaminoamide together with diamine and reacting these with tetracarboxylic dianhydride or its derivatives are widely included.
上記の前駆体の合成に用いられるジアミンとしては、た
とえば４・４′−ジアミノジフェニルエーテル、４・４
′−ジアミノジフェニルメタン、４・４′−ジアミノア
ミドとルスルホン、４・４′−ジアミノジフェニルサル
ファイド、ベンジジン、メタフェニレンジアミン、パラ
フェニレンジアミン、１・５−ナフタレンジアミン、２
・６−ナフタレンジアミン、エチレンジアミン、シクロ
ヘキサンジアミンなどが用いられる。これらは一種であ
っても二種以上を併用してもよい。Examples of diamines used in the synthesis of the above precursors include 4,4'-diaminodiphenyl ether, 4,4
'-Diaminodiphenylmethane, 4,4'-diaminamide and rusulfone, 4,4'-diaminodiphenyl sulfide, benzidine, metaphenylenediamine, paraphenylenediamine, 1,5-naphthalenediamine, 2
・6-Naphthalenediamine, ethylenediamine, cyclohexanediamine, etc. are used. These may be used alone or in combination of two or more.
また、上記ジアミンと併用できるジアミノアミドとして
は、たとえば４・４′−ジアミノジフェニルエーテル−
３−スルホンアミド、３・４′−ジアミノジフェニルエ
ーテル−４−スルホンアミド、３・４−ジアミノジフェ
ニルメタン−４−スルホンアミド、３・４−ジアミノジ
フェニルスルホン−４−スルホンアミド、４・４′−ジ
アミノジフェニルエーテル−３−カルボンアミド、３・
４′−ジアミノジフェニルエーテル−４−カルボンアミ
ド、４・４−ジアミノジフェニルメタン−３−カルボン
アミド、４．・４′−ジアミノジフェニルスルホン−３
−カルボンアミド、４・４′−ジアミノジフェニルサル
ファイド−３−カルボンアミド、３・４′−ジアミノジ
フェニルサルファイド−３７−スルホンアミドなどがあ
る。これらは一種であっても二種以上を併用してもよい
。。In addition, examples of diaminoamides that can be used in combination with the above diamines include 4,4'-diaminodiphenyl ether-
3-sulfonamide, 3,4'-diaminodiphenyl ether-4-sulfonamide, 3,4-diaminodiphenylmethane-4-sulfonamide, 3,4-diaminodiphenylsulfone-4-sulfonamide, 4,4'-diaminodiphenyl ether -3-carbonamide, 3.
4'-diaminodiphenyl ether-4-carbonamide, 4,4-diaminodiphenylmethane-3-carbonamide, 4.・4'-diaminodiphenylsulfone-3
-carbonamide, 4,4'-diaminodiphenyl sulfide-3-carbonamide, 3,4'-diaminodiphenyl sulfide-37-sulfonamide, and the like. These may be used alone or in combination of two or more. .
上記のジアミン類と反応させるテトラカルボン酸二無水
物としては、たとえばピロメリット酸二無水物、３・３
′・４・４′−ジフェニルテトラカルボン酸二無水物、
３・３′・４・４′−ベンゾフェノンテトラカルボン酸
二無水物、シクロペンクンテトラカルボン酸二無水物、
１・２・５・６−ナフタレンテトラカルボン酸二無水物
、２・３・６・７−ナフタレンテトラカルボン酸二無水
物、２・３・５・６−ピリジンテトラカルボン酸二無水
物、３・４・９・１０−ペリレンテトラカルボン酸二無
水物、４・４′−スルホニルシフタル酸二無水物、ブタ
ンテトラカルボン酸二無水物などが用いられる。これら
は一種であっても二種以上を併用してもよい。また、上
記二無水物の誘導体としては低級ジアルキルエステル化
物やハロゲン化物などが挙げられる。Examples of the tetracarboxylic dianhydride to be reacted with the above diamines include pyromellitic dianhydride, 3.3
',4,4'-diphenyltetracarboxylic dianhydride,
3, 3', 4, 4'-benzophenone tetracarboxylic dianhydride, cyclopenkune tetracarboxylic dianhydride,
1,2,5,6-naphthalenetetracarboxylic dianhydride, 2,3,6,7-naphthalenetetracarboxylic dianhydride, 2,3,5,6-pyridinetetracarboxylic dianhydride, 3. 4,9,10-perylenetetracarboxylic dianhydride, 4,4'-sulfonylsiphthalic dianhydride, butanetetracarboxylic dianhydride, and the like are used. These may be used alone or in combination of two or more. In addition, examples of derivatives of the dianhydride include lower dialkyl esters and halides.
ポリイミド系樹脂の前駆体を溶解させるための有機溶剤
は、上記前駆体を合成する際に用いた有機溶剤をそのま
ま使用でき、必要に応じて前駆体合成後にさらに希釈し
てもよい。溶剤量は組成物の固形分濃度が１０〜３０重
量％程度となるようにするのがよい。かかる有機溶剤の
具体例としては、Ｎ−メチル−２−ピロリドン、Ｎ−Ｎ
−ジメチルアセトアミド、Ｎ−Ｎ−ジメチルホルムアミ
ド、Ｎ−Ｎ−ジエチルホルムアミド、ジメチルスルホキ
サイド、ヘキサメチルホスホルアミド、テトラメチレン
スルホン、２−エトキシエチルアセタートなどが挙げら
れる。また、これら溶媒とともに組成物の粘度を調整す
るためにナフサなどの汎用溶媒を併用することもできる
。As the organic solvent for dissolving the precursor of the polyimide resin, the organic solvent used when synthesizing the precursor can be used as is, and it may be further diluted after synthesizing the precursor as necessary. The amount of solvent is preferably set so that the solid content concentration of the composition is about 10 to 30% by weight. Specific examples of such organic solvents include N-methyl-2-pyrrolidone, N-N
-dimethylacetamide, N-N-dimethylformamide, N-N-diethylformamide, dimethyl sulfoxide, hexamethylphosphoramide, tetramethylene sulfone, 2-ethoxyethyl acetate, and the like. Moreover, a general-purpose solvent such as naphtha can also be used together with these solvents in order to adjust the viscosity of the composition.
このようにして調製されるポリイミド系樹脂の前駆体の
溶液を、半導体装置のポリイミド系樹脂被膜を形成すべ
き部分に、通常は乾煙後の厚みが１〜３０μ程度となる
ように塗布し乾燥させたのち加熱硬化（イミド化）させ
ることによりポリイミド系樹脂被膜が形成される。The solution of the polyimide resin precursor prepared in this way is applied to the part of the semiconductor device where the polyimide resin film is to be formed, usually to a thickness of about 1 to 30 μm after drying, and then dried. After that, a polyimide resin coating is formed by heating and curing (imidization).
第１図および第２図は、この発明の半導体装置の一例（
トランジスタ）を示したものであり、外部リードである
リードフレームｌａ上に導電性銀ペースト組成物などの
グイボンディング材３により半導体素子２が強固に接着
されている。４，４゛は他のリードフレームｌｂ、Ｉｃ
に金属線５，５を介して電気的に接続された一対の電極
である。６はトランスファー成形などにより上記のリー
ドフレーム１ ａ ＋ １ ｂ ＋ １ ｃ ｓ半導体
素子２、グイボンディング材３、電極４，４および金属
線５，５を一体に被覆したエポキシ樹脂である。FIG. 1 and FIG. 2 show an example of the semiconductor device of the present invention (
A semiconductor element 2 is firmly bonded onto a lead frame la, which is an external lead, using a bonding material 3 such as a conductive silver paste composition. 4,4゛ are other lead frames lb, ic
A pair of electrodes are electrically connected to each other via metal wires 5, 5. Reference numeral 6 denotes an epoxy resin integrally covering the lead frame 1a+1b+1cs semiconductor element 2, the bonding material 3, the electrodes 4, 4, and the metal wires 5, 5 by transfer molding or the like.
７は、上記リードフレームｌａ、ｌｂ、ｌｃのエポキシ
樹脂６に被覆される部分の表面全面とこの被覆部表面か
らひき続く外部引き出し部表面の一部を被覆するポリイ
ミド系樹脂被膜である。Reference numeral 7 denotes a polyimide resin coating that covers the entire surface of the portion of the lead frames la, lb, and lc covered with the epoxy resin 6 and a portion of the surface of the external extension portion continuing from the surface of the covered portion.
前記のポリイミド系樹脂被膜は、少なくとも第１図およ
び第２図に示すように外部リード（リードフレームＩａ
、ｌｂ、ｌｃ）のエポキシ樹脂被覆部表面全面とこの被
覆部表面からひき続（外部引き出し部表面に形成される
ことが必要である。なお、この引き出し部表面における
ポリイミド系樹脂被膜は、エポキシ樹脂被覆部との境界
から延出した外方の通常は０．２ ｍｍ以上、好ましく
は０．３ ｒｎｍ以上０５πｍ以下の範囲りを被覆する
ように形成されることが好ましい。The polyimide resin coating described above is applied to at least the external leads (lead frame Ia) as shown in FIGS. 1 and 2.
It is necessary to form the polyimide resin coating on the entire surface of the epoxy resin coated part of (, lb, lc) and continuously from the surface of this coated part (on the surface of the external extension part.The polyimide resin coating on the surface of this extension part is made of epoxy resin. It is preferably formed so as to cover an area extending outward from the boundary with the covering portion, usually 0.2 mm or more, preferably 0.3 rnm or more and 05πm or less.
前記樹脂被膜が形成される外部リードの材質としては、
鉄系、鉄−ニッケル合金系、銅系、銅合金系などが挙げ
られるが、これらに限定されず、これら材質からなる外
部リードに金、銀、ニッケルなどのメッキが施されたも
のでもよい。The material of the external lead on which the resin coating is formed is as follows:
Examples include iron-based, iron-nickel alloy-based, copper-based, copper alloy-based, etc., but are not limited to these, and external leads made of these materials may be plated with gold, silver, nickel, or the like.
前記の樹脂被膜は、上記のように外部リードの表面に形
成されるとともに、その他半導体素子、この半導体素子
を接続するための電極、電線などの構成要素のエポキシ
樹脂被覆部表面の一部または全部に形成されていてもよ
い。The resin coating is formed on the surface of the external lead as described above, and also covers part or all of the surface of the epoxy resin coating of other components such as semiconductor elements, electrodes for connecting the semiconductor elements, and electric wires. may be formed.
なお、この発明において用いられる封止樹脂であるエポ
キシ樹脂としては特に限定されず、例えばノボラック型
、ビスフェノール型などのエポキシ樹脂が挙げられる。Note that the epoxy resin that is the sealing resin used in this invention is not particularly limited, and examples thereof include novolac type and bisphenol type epoxy resins.
また、これらを硬化させるための硬化剤としてはフェノ
ール樹脂、芳香族アミン、酸無水物などが挙げられる。In addition, examples of curing agents for curing these include phenol resins, aromatic amines, acid anhydrides, and the like.
上記のような構成からなるこの発明の半導体装置は、ポ
リイミド系樹脂被膜が外部リードと封止樹脂であるエポ
キシ樹脂との両方に対して接着性にすぐれたものである
ため之外部リードはこの樹脂被膜を介してエポキシ樹脂
と強固に接着されている。このため、この半導体装置は
、従来のエポキシ樹脂封止型半導体装置のようにエポキ
シ樹脂と外部リードとの接着性が悪いことに起因する半
導体特性の低下がなく、扁温扁湿下においてもすぐれた
耐湿特性を有するものである。In the semiconductor device of the present invention having the above structure, the polyimide resin coating has excellent adhesiveness to both the external leads and the epoxy resin which is the sealing resin. It is firmly bonded to the epoxy resin through a coating. Therefore, unlike conventional epoxy resin-sealed semiconductor devices, this semiconductor device does not suffer from deterioration in semiconductor characteristics due to poor adhesion between the epoxy resin and the external leads, and has excellent performance even under cold and humid conditions. It has excellent moisture resistance.
以下に、この発明の実施例を記載してより具体的に説明
する。なお、以下において％とあるのは重量％を意味す
る。EXAMPLES Below, examples of the present invention will be described in more detail. In addition, below, % means weight %.
実施例１
無水ピロメリット酸１モルとよく精製した４・４−ジア
ミノジフェニルエーテル１モルとをＮ−メチル−２−ピ
ロリドン中約８０°Ｃ以下（とくに室温付近ないしそれ
に近い温度）に保ちながら撹拌した。これによって反応
は速かに進行し、かつ反応系の粘度は次第に上昇して、
っぎの構造式で表わされる固有粘度〔η〕が０７のポリ
イミド前駆体が得られた。Example 1 1 mol of pyromellitic anhydride and 1 mol of well-purified 4,4-diaminodiphenyl ether were stirred in N-methyl-2-pyrrolidone while maintaining the temperature at about 80°C or less (particularly at or near room temperature). . As a result, the reaction progresses rapidly, and the viscosity of the reaction system gradually increases.
A polyimide precursor having an intrinsic viscosity [η] of 07 was obtained, as represented by the following structural formula.
この前駆体はこれを１２０℃で０５時間および２５０°
Ｃで１０時間加熱処理することにより完全に硬化（イミ
ド化）シ、っきの構造式で表わされるポリイミドを与え
る。This precursor was heated at 120 °C for 05 h and at 250 °C.
By heat-treating with C for 10 hours, it is completely cured (imidized) and a polyimide represented by the structural formula of plating is obtained.
一方、半導体素子をリードフレーム上にグイボンティン
クシ、さらに他のリードフレームに所定のワイヤボンデ
ィングを行った。このようにして結合された構成要素は
、下記のエポキシ樹脂によるトランスファーモールド成
形により一体に被覆されるものであるが、これに先がけ
て、上記のリードフレームの、エポキシ樹脂被覆部とな
る表面の全面および外部引き出し部表面のうち樹脂被覆
部との境界から外方へＱ、’３ｍｍ以内の表面に、上記
の前駆体の溶液（樹脂温度１６．５％）を乾燥後の厚み
が１５μとなるように塗布し、１２０’Ｃで０５時間お
よび２５０°Ｃで１０時間加熱処理して完全に硬化（イ
ミド化）させた。On the other hand, the semiconductor element was bonded onto a lead frame, and predetermined wire bonding was performed to another lead frame. The components joined in this way are integrally coated by transfer molding with epoxy resin as described below. Then, apply the above precursor solution (resin temperature 16.5%) to the surface of the external drawer part within Q, 3mm outward from the boundary with the resin coating part so that the thickness after drying is 15μ. It was completely cured (imidized) by heat treatment at 120°C for 05 hours and at 250°C for 10 hours.
なお、上記のリードフレームの側斜としては日立金属社
製ＹＥＦ−４２（４２アロイ；Ｎ ｉ ４１％、Ｆｅ５
９％）を用いた。The side slope of the above lead frame is YEF-42 (42 alloy; Ni 41%, Fe5 manufactured by Hitachi Metals).
9%) was used.
上記のようにしてリードフレーム表面にポリイミド樹脂
被膜を形成したのちノボラック型エポキシ樹脂（硬化剤
としてフェノール樹脂を使用）によるトランスファーモ
ールド成形を行って、第１図および第２図に示される如
きこの発明の半導体装置を作製した。After forming a polyimide resin film on the surface of the lead frame as described above, transfer molding with a novolac type epoxy resin (phenol resin is used as a hardening agent) is performed to produce the invention as shown in FIGS. 1 and 2. A semiconductor device was fabricated.
このようにして得た半導体装置につき、１２１°Ｃ１２
気圧での加圧浸水テスト（プレッシャークツカーテスト
）を行い、経時的な配゛線腐食を調べた結果は、後記の
表に示されるとおりであった。For the semiconductor device obtained in this way, the temperature was 121°C12
A pressurized water immersion test at atmospheric pressure (pressure pump test) was conducted to investigate wire corrosion over time, and the results were as shown in the table below.
表中の数値は、試験個数（ｎ）４０個中の配線腐食数を
示したものである。The numerical values in the table indicate the number of wiring corrosion in 40 test pieces (n).
実施例２
テトラカルボン酸二無水物として無水ピロメリット酸０
５モルとベンゾフェノンテトラカルボン酸二無水物０．
５モルとを使用し、かつジアミンとしてよく精製した４
・４′−ジアミノジフェニルエーテル０．６モルと４・
４′−ジアミノジフェニルエーテル−３−カルボンアミ
ド０．４モルとを使用した以外は、実施例１と同様にし
て後記の構造式（１）で表わされる固有粘度〔η〕が１
．８のポリイミド系樹脂の前駆体を得た。Example 2 Pyromellitic anhydride 0 as tetracarboxylic dianhydride
5 mol and benzophenonetetracarboxylic dianhydride 0.
5 mol and well purified as diamine 4
・4′-diaminodiphenyl ether 0.6 mol and 4・
The process was repeated in the same manner as in Example 1, except that 0.4 mol of 4'-diaminodiphenyl ether-3-carbonamide was used, so that the intrinsic viscosity [η] expressed by the structural formula (1) below was 1.
．． A precursor of polyimide resin No. 8 was obtained.
この前駆体は、これを実施例１に示すイミド化条件で完
全に硬化させると後記の構造式（２）で表わされるポリ
イミド−イソインドロキナシリジオン樹脂を与える。When this precursor is completely cured under the imidization conditions shown in Example 1, a polyimide-isoindorochinasilidione resin represented by the structural formula (2) below is obtained.
上記の前駆体溶液（樹脂濃度１２．５％）を用いて実施
例１と同様にしてこの発明の半導体装置を得た。ただし
、リードフレームの材料としては、土用機械金属社製Ｈ
５Ｍ（Ｃｕ９７．５％、Ｆｅ２．３５％。A semiconductor device of the present invention was obtained in the same manner as in Example 1 using the above precursor solution (resin concentration 12.5%). However, the material for the lead frame is H
5M (Cu97.5%, Fe2.35%.
Ｚｎ０．１２％、Ｐｏ、０３％）を用い、上記の前駆体
溶液を乾燥後の厚みが５０／”となるように塗布した。Using Zn0.12%, Po03%), the above precursor solution was applied so that the thickness after drying was 50/''.
この半導体装置につき、実施例１と同様にしてプレッシ
ャークツカーテストを行った結果は後記の表に示される
とおりであった。This semiconductor device was subjected to a pressure puller test in the same manner as in Example 1, and the results were as shown in the table below.
実施例３
テトラカルボン酸二無水物として無水ピロメリット酸ｏ
、 ４モルとベンゾフェノンテトラカルボン酸二無水物
０６モルとを使用し、かつジアミンとしてよく精製した
４・４′−ジアミノジフェニルエーテル０４モルとアミ
ノフェノキシフェニルスルホン０．６モルとを使用した
以外は、実施例１と同様にして後記の構造式（３）で表
わされる固有粘度〔η〕が２．７のポリイミド前駆体を
得た。この前駆体は、これを実施例１と同様のイミド化
条件で完全に硬化させると後記の構造式（４）で表わさ
れるポリイミドを与える。Example 3 Pyromellitic anhydride o as tetracarboxylic dianhydride
, and 06 moles of benzophenonetetracarboxylic dianhydride, and 04 moles of 4,4'-diaminodiphenyl ether, which had been well purified as a diamine, and 0.6 moles of aminophenoxyphenylsulfone were carried out. A polyimide precursor having an intrinsic viscosity [η] of 2.7 and represented by the structural formula (3) described later was obtained in the same manner as in Example 1. When this precursor is completely cured under the same imidization conditions as in Example 1, it yields a polyimide represented by the structural formula (4) below.
上記の前駆体溶液（樹脂濃度１８％）を用いて実施例１
と同様にしてこの発明の半導体装置を得た。ただし、リ
ードフレームの材料としては、高゛砂鉄工社製ＴＡＫ−
８（Ｆｅ９９．５％以上）を用い、このリードフレーム
には鈑メッキを施した。また、上記の前駆体溶液を乾燥
後の厚みが７０μとなるように塗布した。Example 1 using the above precursor solution (resin concentration 18%)
A semiconductor device of the present invention was obtained in the same manner as described above. However, the material for the lead frame is TAK-
8 (99.5% or more of Fe) was used, and this lead frame was plated. Further, the above precursor solution was applied so that the thickness after drying was 70 μm.
この半導体装置につき、実施例１と同様にしてプレッシ
ャークツカーテストを行った結果は後記の表に示される
とおりであった。This semiconductor device was subjected to a pressure puller test in the same manner as in Example 1, and the results were as shown in the table below.
比較例１〜３
リードフレームの表面にポリイミド系樹脂被膜を形成し
ない以外は、比較例１は実施例１と同様にして、比較例
２は実施例２と同様にして、また比較例３は実施例３と
同様にしてそれぞれ半導体装置を作製した。Comparative Examples 1 to 3 Comparative Example 1 was conducted in the same manner as Example 1, Comparative Example 2 was conducted in the same manner as Example 2, and Comparative Example 3 was conducted in the same manner as in Example 2, except that a polyimide resin film was not formed on the surface of the lead frame. Semiconductor devices were manufactured in the same manner as in Example 3.
これらの半導体装置につき実施例１〜３と同様にしてプ
レッシャークツカーテストを行った結果は後記の表に示
されるとおりであった。A pressure shoe test was performed on these semiconductor devices in the same manner as in Examples 1 to 3, and the results were as shown in the table below.
比較例４
リードフレーム表面にポリイミド樹脂被膜を形成する際
に、リードフレームのエポキシ樹脂被覆部となる表面の
うち外部引き出し部との境界から円方へ１．５ ｍ以内
の表面および引き出し部表面にハホリイミド樹脂被膜を
形成しなかった以外は実施例１と同様にして半導体装置
を得、−この半導体装置につき実施例１と同様にしてプ
レッシャークツカーテストを行った結果は後記の表に示
されるとおりであった。Comparative Example 4 When forming a polyimide resin coating on the surface of a lead frame, a polyimide resin film was applied to the surface of the lead frame that was to be coated with epoxy resin within 1.5 m in a circular direction from the boundary with the external extension part, and on the surface of the extension part. A semiconductor device was obtained in the same manner as in Example 1 except that the haphorimide resin film was not formed, and a pressure tester test was conducted on this semiconductor device in the same manner as in Example 1. The results are shown in the table below. Met.
以上の結果から明らかなように、この発明の半導体装置
は冒温高湿下においてもすぐれた耐湿特性を有する。As is clear from the above results, the semiconductor device of the present invention has excellent moisture resistance even under high temperature and high humidity conditions.
第１図および第２図は、この発明の半導体装置の一例を
示す断面図および平面図である。
ｌａ、Ｉｂ、ｌｃ・・・リードフレーム、２・・・半導
体素子、６・エポキシ樹脂、７・・ポリイミド系樹脂被
膜1 and 2 are a cross-sectional view and a plan view showing an example of a semiconductor device of the present invention. la, Ib, lc...Lead frame, 2...Semiconductor element, 6...Epoxy resin, 7...Polyimide resin coating
Claims (1)
とし、これら構成要素が結合されてエポキシ樹脂で一体
に被覆されてなるエポキシ樹脂封止型半導体装置におい
て、前記構成要素のうち少なくとも外部リードの表面に
このリードのエポキシ樹脂被覆部から外部引き出し部に
またがるポリイミド系樹脂被膜を形成し、この被膜で上
記両部を被覆したことを特徴とする半導体装置。(1) In an epoxy resin-sealed semiconductor device that includes at least a semiconductor element and an external lead, these components are bonded together and integrally coated with an epoxy resin, and the surface of at least the external lead among the components is 1. A semiconductor device characterized in that a polyimide resin film is formed extending from the epoxy resin coated portion of the lead to the external lead-out portion, and both parts are covered with this film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58205659A JPS6097646A (en) | 1983-10-31 | 1983-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58205659A JPS6097646A (en) | 1983-10-31 | 1983-10-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6097646A true JPS6097646A (en) | 1985-05-31 |
Family
ID=16510556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58205659A Pending JPS6097646A (en) | 1983-10-31 | 1983-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6097646A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0243758A (en) * | 1988-08-03 | 1990-02-14 | Fuji Electric Co Ltd | Resin sealed type semiconductor element |
| US5883439A (en) * | 1996-03-19 | 1999-03-16 | Nec Corporation | Semiconductor device molded in plastic package free from crack by virtue of organic stress relaxation layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS506279A (en) * | 1973-05-18 | 1975-01-22 | ||
| JPS50110774A (en) * | 1974-07-05 | 1975-09-01 |
-
1983
- 1983-10-31 JP JP58205659A patent/JPS6097646A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS506279A (en) * | 1973-05-18 | 1975-01-22 | ||
| JPS50110774A (en) * | 1974-07-05 | 1975-09-01 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0243758A (en) * | 1988-08-03 | 1990-02-14 | Fuji Electric Co Ltd | Resin sealed type semiconductor element |
| US5883439A (en) * | 1996-03-19 | 1999-03-16 | Nec Corporation | Semiconductor device molded in plastic package free from crack by virtue of organic stress relaxation layer |
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