JPS6097284A - Clutter suppressing apparatus - Google Patents

Clutter suppressing apparatus

Info

Publication number
JPS6097284A
JPS6097284A JP58205244A JP20524483A JPS6097284A JP S6097284 A JPS6097284 A JP S6097284A JP 58205244 A JP58205244 A JP 58205244A JP 20524483 A JP20524483 A JP 20524483A JP S6097284 A JPS6097284 A JP S6097284A
Authority
JP
Japan
Prior art keywords
output
log
video
delay
tap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58205244A
Other languages
Japanese (ja)
Inventor
Kiyoshi Shimojo
下條 潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58205244A priority Critical patent/JPS6097284A/en
Publication of JPS6097284A publication Critical patent/JPS6097284A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28Details of pulse systems
    • G01S7/285Receivers
    • G01S7/292Extracting wanted echo-signals
    • G01S7/2923Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods
    • G01S7/2927Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods by deriving and controlling a threshold value

Landscapes

  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To dispense with adjustment for aligning an amplitude level or timing, by simultaneously realizing the delay function possessed by a bypass circuit along with LOG/CFAR function by partially making use of a circuit for constituting LOG/CFAR. CONSTITUTION:A clutter suppressing circuit 5 consists of a logarithmic converter 321, a delay device 322 with a tap, a sum total operator 323, an 1/N operator 324, a subtractor 325, an anti-logarithmic converter 326 and a video change-over device 327. The video change-over device 327 has function for changing over the average value subtracting output of the subtractor 325 and the tap N/2 output of the delay devices 322 with the tap. When the video change- over device 327 is changed over to a B-side, LOG/CFAR output video is obtained at the output terminal of the anti-logarithmic converter 326. When the video change-over device 327 is changed over to an A-side. The output video of the logarithmic converter 321 is delayed by the delay device 322 with the tap before subjected to direct anti-logarithmic conversion.

Description

【発明の詳細な説明】 本発明は航空機、船舶などを監視するための監視管制用
レーダー装置に使用するクラッタ抑圧装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clutter suppression device used in a surveillance and control radar device for monitoring aircraft, ships, etc.

一般に監視管制用レーダー装置においては、航空機、船
舶などの目標からの反射信号とともに地上の固定物(地
表、建物、山などを示す)からの反射信号であるグラン
ドクラツタや、海面からの反射信号であるジ−クラッタ
及び雨雲などの反射信号であるウェザ−クラッタなど、
不要信号が受信される。このためこれらの不要信号を除
去し、目標からの反射信号だけを検出し表示するため種
々のクラッタ抑圧手段が講じられる。前述のジ−クラッ
タやウェザ−クラッタに対するクラッタ抑圧手段として
は一般的にLOG/CFAR,と呼ばれる抑圧手段が多
く使用される。
In general, in surveillance and control radar equipment, in addition to reflected signals from targets such as aircraft and ships, ground clutter, which is a reflected signal from fixed objects on the ground (indicating the ground surface, buildings, mountains, etc.), and reflected signals from the sea surface are used. weather clutter, which is a signal reflected from rain clouds, etc.
Unwanted signals are received. For this reason, various clutter suppression means are used to remove these unnecessary signals and detect and display only the signals reflected from the target. As a clutter suppressing means for the above-mentioned g-clutter and weather clutter, a suppressing means generally called LOG/CFAR is often used.

しかしながらこのクラッタ抑圧手段は対象とするクラッ
タが存在しない場合に使用すると、この手段の特性から
目標の信号強度が弱められ目標検出性能が低下すること
が知られている。このため通常はLOG/CFARを通
る系とLOG/CFARをバイバスする系を合わせもち
クラッタの発生状況に応じて切替えて、使用されること
が多い。
However, it is known that when this clutter suppressing means is used when there is no target clutter, the signal strength of the target is weakened due to the characteristics of this means, and the target detection performance is degraded. For this reason, a system that passes through the LOG/CFAR and a system that bypasses the LOG/CFAR are usually used, and are switched depending on the occurrence of clutter.

従来のLO()/CIi’ARを抑圧手段とするクラッ
タ抑圧装置の一例について第1図を参照して説明する。
An example of a clutter suppression device using conventional LO()/CIi'AR as a suppression means will be described with reference to FIG.

第1図は従来のクラッタ抑圧装置3とともに空中線1.
送受信装置2およびビデオ表示装置4を併記して示して
いる。
FIG. 1 shows a conventional clutter suppression device 3 and an antenna 1.
A transmitting/receiving device 2 and a video display device 4 are also shown.

レーダー受信信号は空中線l全通して送受信装置2に供
給され、ビデオ信号に変換される。このビデオ信号はク
ラッタ抑圧装置3に供給されリニアビデオ遅延器31お
よびLOG/CFAR32に入力される。LOG/CF
AR32について第2図および第3図を参照して説明す
る。第3図(a)に示す入力ビデオ信号はログ(対数)
変換器321により第3図(b)に示すログビデオに変
換された後タップ付遅延器322に供給される。タップ
付遅延器322は最小遅延時間出力のタップlから最大
遅延時間出力のタップNtで隣り合うタップ間の遅延時
間差の等しいN個の遅延信号を出力できる遅延回路であ
る。これらN個の出力は総和演算器323へ送られタッ
プ1からNtでの出力の総和がめられる。この総和はl
/N演算器324へ入力され総和の1/Nすなわち第3
図<c>に示すN個の遅延出力の加算平均値がめられる
。この加算平均値とタップN/2の遅延出力とが減算器
325へ送られタップN/2出力からクラッタ成分を含
む加算平均値が差し引かれ、第3図(d)に示すような
りラックの抑圧された平均値減算出力が得られる。
The radar reception signal is supplied to the transmitting/receiving device 2 through the antenna l, and is converted into a video signal. This video signal is supplied to the clutter suppression device 3 and input to the linear video delay device 31 and LOG/CFAR 32. LOG/CF
The AR32 will be explained with reference to FIGS. 2 and 3. The input video signal shown in Figure 3(a) is logarithmic.
The log video is converted by the converter 321 into the log video shown in FIG. 3(b) and then supplied to the tapped delay unit 322. The tapped delay device 322 is a delay circuit capable of outputting N delay signals having equal delay time differences between adjacent taps from a tap l having a minimum delay time output to a tap Nt having a maximum delay time output. These N outputs are sent to the summation calculator 323, and the summation of the outputs from tap 1 to Nt is calculated. This sum is l
1/N of the total sum, that is, the third
The average value of the N delayed outputs shown in Figure <c> is calculated. This additive average value and the delayed output of tap N/2 are sent to the subtracter 325, and the additive average value including the clutter component is subtracted from the tap N/2 output, resulting in rack suppression as shown in FIG. 3(d). The average value subtracted output is obtained.

この出力はまだログ振巾特性を有するビデオ信号であり
次段のアンチログ(逆対数)変換器326により第3図
(e’)に示すリニア特性のビデオ信号に変換されT、
OG/CFA凡32の出力となる。
This output is still a video signal having a logarithmic amplitude characteristic, and is converted into a video signal having a linear characteristic shown in FIG. 3(e') by an antilog converter 326 in the next stage.
This is the output of OG/CFA 32.

ここで再び第1図に戻って従来のクラッタ抑圧装置3に
ついて説明を続けるとり二゛γビデオ遅延器31はLO
G/CFAR32の出力が上述の如くタップ付遅延器3
22により処理時間遅れを生ずるため、切替を行った時
2つのビデオ信号の時間的ずれが無いように時間補正用
の遅延機能を有するバイパス回路である。従来のクラッ
タ抑圧装置3はリニアビデオ遅延器31およびLOG/
CFAR32の2つの出力をクラッタの発生状況に応じ
てビデオ切替器33により切替えてビデオ表示装置4へ
出力する。
Now, returning to FIG. 1 again to continue the explanation of the conventional clutter suppression device 3, the 2.gamma. video delay device 31 is LO
The output of the G/CFAR32 is connected to the tapped delay device 3 as described above.
22 causes a processing time delay, so this bypass circuit has a delay function for time correction so that there is no time lag between the two video signals when switching is performed. The conventional clutter suppression device 3 includes a linear video delay device 31 and a LOG/
The two outputs of the CFAR 32 are switched by a video switch 33 according to the occurrence of clutter and output to the video display device 4.

上述の従来のクラッタ抑圧装置はノくイノ(ス回路であ
るリニアビデオ遅延器31の分だけ価格か高くなりかつ
LOG/CFAR32の出力と切替えるため両出力のピ
ア141号の振幅レベルやタイミングを合わせるなどの
調整を要した。
The above-mentioned conventional clutter suppression device is expensive due to the linear video delay device 31, which is a noise circuit, and in order to switch with the output of the LOG/CFAR 32, the amplitude level and timing of the peer 141 of both outputs must be adjusted. This required some adjustments.

本発明は、LOG/CFARを構成する回路の一部を流
用することにより上記欠点を除去し本来のLOG/CF
ARfi能のともに)(イノ(ス回路のもつ遅延機能も
同時に有することのできるクラッタ抑圧装置を提供する
ものである。
The present invention eliminates the above drawbacks by reusing a part of the circuit constituting the LOG/CFAR.
The present invention provides a clutter suppression device that can simultaneously have the delay function of an innoc circuit as well as the ARfi function.

本発明のクラッタ抑圧装置はレーダー受信信号を振巾検
波し、かつログ変換して得るログビデオ信号を出力する
手段と、前記ログビデオ信号を時間遅延した信号を出力
するとともにその途中の複数個の遅延出力も出し得るタ
ップ付遅延手段と前記複数個の遅延出力の加算平均値を
算出する手段と前記遅延出力から前記加算平均出力を差
し引いて得る平均値減算結果を出力する手段と、前記平
均値減算出力と前記遅延出力とを切替える手段と前記切
替手段の出力をアンチログ変換して得るビデオ信号を出
力する手段とを含んで構成される。
The clutter suppression device of the present invention includes a means for amplitude-detecting a radar reception signal and outputting a log video signal obtained by performing log conversion, and a means for outputting a signal obtained by time-delaying the log video signal, and also for outputting a signal obtained by time-delaying the log video signal. a tapped delay means capable of outputting a delayed output; a means for calculating an average value of the plurality of delayed outputs; a means for outputting an average value subtraction result obtained by subtracting the average output from the delayed output; and the average value. The apparatus includes means for switching between the subtracted output and the delayed output, and means for outputting a video signal obtained by performing antilog conversion on the output of the switching means.

次に本発明の実施例について第4図を参照して説明する
Next, an embodiment of the present invention will be described with reference to FIG.

本発明のクラッタ抑圧装置5は前述の従来のクラッタ抑
圧装置3のLOG/CFAR,32を構成するログ変換
器321とタップ付遅延器322と総和演算器323と
1/N演算器324と減算器325とアンチログ変換器
326に加えビデオ切替器327とからなる。ビデオ切
替器327以外の構成回路は前述のとおりの機能を有す
る。
The clutter suppression device 5 of the present invention includes a log converter 321, a tapped delay device 322, a summation arithmetic unit 323, a 1/N arithmetic unit 324, and a subtractor that constitute the LOG/CFAR 32 of the conventional clutter suppression device 3 described above. 325, an anti-log converter 326, and a video switch 327. The constituent circuits other than video switch 327 have the same functions as described above.

ビデオ切替器327は減算器325の平均値減算出力と
タップ付遅延器322のタップN/2出力とを切替える
機能を有する。これら2つの出力はともにログ特性を有
するビデオ信号であり、アンチログ変換器326により
リニア特性のビデオ信号に変換され出力される。すなわ
ちビデオ切替器327がB側に切替えられた時は前述の
LOG/C1”AR出力ビデオがアンチログ変換器32
6の出力端で得られる。反対にA側に切替えられた時は
ログ変換器321の出力ログビデオがタップ付遅延器3
22により遅延された後平均値減算されないで直接アン
チログ変換されるため従来のクラッタ抑圧装置3のリニ
アビデオ遅延器31の出力と同じく、LOG/CFAR
’iバイパスされ、かつ遅延されたビデオ信号が得られ
る。
The video switch 327 has a function of switching between the average value subtraction output of the subtracter 325 and the tap N/2 output of the tapped delay unit 322. These two outputs are both video signals having logarithmic characteristics, and are converted by the anti-log converter 326 into a video signal having linear characteristics and output. That is, when the video switch 327 is switched to the B side, the above-mentioned LOG/C1''AR output video is transferred to the anti-log converter 32.
It is obtained at the output end of 6. On the other hand, when switched to the A side, the output log video of the log converter 321 is transferred to the tapped delay device 3.
After being delayed by 22, the average value is not subtracted and anti-log conversion is performed directly.
A bypassed and delayed video signal is obtained.

以上説明したように本発明はLOG/CFARを構成す
る回路を一部流用することにより、本来のLOG/CF
AR機能とともにバイパス回路のもつ遅延機能も同時に
有することのできるのでバイパス回路骨だけ 価でかつ
2つの振幅レベルやタイミングを合わせる調整の不要な
りラッタ抑圧装置を容易に構成できる特徴を有する。
As explained above, the present invention utilizes some of the circuits that make up the LOG/CFAR, so that the original LOG/CFAR
Since it can have both the AR function and the delay function of the bypass circuit, it has the feature that the rutter suppression device can be easily configured without requiring the bypass circuit only and without the need for adjustment to match two amplitude levels or timings.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のクラッタ抑圧装置を含む監視管制用レー
ダー装置を示すブロック図、第2図は従来のクラッタ抑
圧装置を構成するLOG/CFARの構成を示すプロン
、り図、第3図はLOG/CFA几を構成する各回路の
入出力信号を示す信号波形図。 第4図は本発明の一実施例を示すブロック図である。 1・・・・・・空中線、2・・・・・・送受信装置、3
,5・・・・・・、クラッタ抑圧装置、4・・・・・・
ビデオ表示装置、31・・・・・・リニアビデオ遅延器
、32・・・・・・LOG/CF/R。 33、.327・・・・・・ビデオ切替器、321・・
・・・・ログ変換器、322・・・・・・タップ付遅延
器、323・・・・・・総和演算器、324・・・・・
・l/N演算器、325・・・・・・減算器、326・
・・・・・アンチログ変換器。 (C) しΩ裏k)q筆【fじ、力 (jビノエ「仁v(IL;A’:刺(,3二カ(Cノア
>プロア°゛愛1灸りが〃
Fig. 1 is a block diagram showing a monitoring and control radar device including a conventional clutter suppression device, Fig. 2 is a diagram showing the configuration of LOG/CFAR that constitutes the conventional clutter suppression device, and Fig. 3 is a block diagram showing the LOG/CFAR configuration. FIG. 2 is a signal waveform diagram showing input and output signals of each circuit configuring the /CFA box. FIG. 4 is a block diagram showing one embodiment of the present invention. 1... Antenna, 2... Transmitting/receiving device, 3
, 5..., clutter suppression device, 4...
Video display device, 31...Linear video delay device, 32...LOG/CF/R. 33. 327...Video switch, 321...
... Log converter, 322 ... Delay device with tap, 323 ... Summation calculator, 324 ...
・l/N calculator, 325...Subtractor, 326・
...Antilog converter. (C) しΩ Ura k) q brush [fji, power (j Binoe ``Jin v (IL; A': sashi) (, 3 two ka (C Noah > proa °゛ love 1 moxibustion)

Claims (1)

【特許請求の範囲】[Claims] レーダー受信信号を振巾検波し、かつログ(対数)変換
してログビデオ信号として出力する手段と、前記ログビ
デオ信号を時間遅延した信号を出力するとともにその途
中の複数個の遅延出力も出し得るタップ付遅延手段と、
前記複数個の遅延出力の加算平均値を算出する手段と、
前記遅延出力から前記加算平均出力を差し引いて得る平
均値減算結果を出力する手段と、前記平均値減算出力と
前記遅延出力とを切替える手段と、前記切替手段の出力
をアンチログ(逆対数)変換して得るビデオ信号を出力
する手段とを含んで構成されたことを特徴とするクラッ
タ抑圧装置。
A means for amplitude-detecting a radar reception signal, performing logarithmic conversion and outputting it as a log video signal, and outputting a signal obtained by time-delaying the log video signal, and also outputting a plurality of delayed outputs in the middle. a tapped delay means;
means for calculating an average value of the plurality of delayed outputs;
means for outputting an average value subtraction result obtained by subtracting the average output from the delayed output; means for switching between the average value subtraction output and the delayed output; and anti-log transformation of the output of the switching means. and means for outputting a video signal obtained by the clutter suppressing apparatus.
JP58205244A 1983-11-01 1983-11-01 Clutter suppressing apparatus Pending JPS6097284A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58205244A JPS6097284A (en) 1983-11-01 1983-11-01 Clutter suppressing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58205244A JPS6097284A (en) 1983-11-01 1983-11-01 Clutter suppressing apparatus

Publications (1)

Publication Number Publication Date
JPS6097284A true JPS6097284A (en) 1985-05-31

Family

ID=16503779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58205244A Pending JPS6097284A (en) 1983-11-01 1983-11-01 Clutter suppressing apparatus

Country Status (1)

Country Link
JP (1) JPS6097284A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142281A (en) * 1986-12-04 1988-06-14 Nec Corp Radar signal processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142281A (en) * 1986-12-04 1988-06-14 Nec Corp Radar signal processor
JPH0547076B2 (en) * 1986-12-04 1993-07-15 Nippon Electric Co

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