JPS585385B2 - Receive beamformer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving beamformer that is necessary when obtaining high-resolution images using a phased array antenna, and particularly to a receiving beamformer that can perform dynamic focusing that changes the focal length, such as sonar, radar, etc.
This is used in ultrasound imaging devices, etc.

When obtaining high-resolution images by echo ranging using a phased array antenna, in order to increase the resolution in the angular direction, a multi-element array is used and the distance (i.e., time from the transmission pulse emission time) changes. Correspondingly, it is necessary to use so-called dynamic focusing, which makes the focal length variable.

Furthermore, in order to increase the resolution in the distance direction, it is necessary to be able to transmit and receive short pulses or broadband pulses.

A generally used receiving beamformer that satisfies these requirements uses a variable delay line as shown in FIG.

In this figure, 10, . . . , 14 are sensor elements, 2
1. ..., 24 is a preamplifier, 3□, ..., 34 is a variable delay line, 4 is an adder, 5 is an output terminal, 6 is a delay controller, 7 is a trigger signal input terminal, 9 is an azimuth signal This is an input terminal.

The input signal converted into an electrical signal in each sensor element 1□, . . . , 14 is sent to a preamplifier 21 . . . , 24, the signal is amplified to an appropriate signal level, and the variable delay line 31
. . , 34, are added by an adder 4, and outputted from an output terminal 5.

In this case, since the direction signal of the receiving beam is applied from the direction input terminal 8 and the trigger signal representing the emission time of the transmission pulse is applied from the trigger input terminal 7, the delay controller 6 is applied to the given direction and distance. Each variable delay line 31 . ..., 34 delay amounts are controlled.

General beamformers often ignore changes in compensation delay amount due to distance and apply a fixed delay only to a certain direction, but in order to obtain high-resolution images, it is necessary to also compensate for the effects of distance. Focusing will be required.

That is, it is necessary to change the amount of compensation delay along with the time from the trigger signal input time (which is converted to the distance).

Note that such beam forming is called dynamic focusing.

In order to achieve dynamic focusing using this type of method using a variable delay line, an analog switch that can switch the amount of delay at high speed is required, but this type of analog switch that handles high-frequency signals is difficult to implement.

Additionally, the wideband analog delay lines with the large number of taps required to obtain high resolution video are very expensive.

In addition, after converting each sensor output signal into digital code,
A beamformer can also be implemented by applying signals to digital variable delay lines (implemented with digital memory or the like) and summing their outputs, but this becomes difficult when using high frequency signals.

Another example of a conventionally used receive beamformer is one using an orthogonal demodulator as shown in FIG.

That is, the output signals of each sensor 1□, . . . , 14 are amplified to a predetermined level by preamplifiers 2 □, . ....

94 and converted into baseband signals for real and imaginary parts, and then phase shifter 100, . . .
A phase delay equivalent to the amount of delay required for beam forming is given in , 104, and the real part and imaginary part of the output are added in adders 4□ and 4□, respectively, and the output is added to the squarer 11.
After being squared by □ and 112, they are added together by an adder 43 and output from the output terminal 5.

Orthogonal demodulator 9□ in this case. ..., 94 has a configuration as shown in FIG. 3, and the output terminal 13 of the carrier generator 13
Multipliers 151 and 152 use a sine wave signal in phase with the transmission signal sent from 1 and a sine wave signal orthogonal to the transmission signal sent from the other output terminal 13□ of the carrier generator 13 as reference signals, respectively. and low pass filter 1
6□.

162 synchronously detects the sensor output signal applied to the input terminal 14, and outputs the real part and imaginary part of the demodulated signal from output terminals 17□ and 17□, respectively.

Moreover, each phase shifter 101. ..., 104 inputs the phase delay amount ψ equivalent to the delay amount from the delay controller 6 and executes ex
p(-iψ) is generated, and the orthogonal demodulator 9□,...
, 94, and achieves an effect equivalent to applying a phase shift of 1 ψ to the carrier domain signal before demodulation.

However, the accurate amount of delay that can be compensated for by this type of circuit is limited to one wavelength or less, and if the amount to be compensated exceeds this, there is a risk that an error of an integral multiple of the wavelength will occur.

Therefore, this type of circuit cannot be applied when the size of the sensor array is sufficiently large compared to the wavelength and the received signal changes rapidly.

The present invention is intended to eliminate the above-mentioned drawbacks of the prior art, and its purpose is to provide a receiving beamformer that can be easily digitized and can handle wideband, high-frequency signals.

The features of the present invention that achieve this object include a demodulator that decomposes the output signals of N sensor elements into an in-phase component and a quadrature component of a transmission carrier wave having a wavelength λ and a propagation speed C; An A/D converter that converts the components into digital codes, and a delay amount dn (n
= 1, 2°..., N), and a delay means for digitally delaying the delayed in-phase component by the real part and the delayed orthogonal component as the imaginary part. exp(-i
a digital arithmetic circuit that performs complex multiplication with a complex number ψn), means for cumulatively adding the real part and imaginary part of the multiplication results, respectively, squaring the absolute values of the cumulative addition results, and adding the squared results to each other. and where the necessary delay amount to be set for each sensor at least corresponding to the desired orientation is Dn (n=1.2...,N), the delay amount dn and the phase amount ψ.

and is Dn=dn+ψ. - The delay amount dn is set to maintain the relationship λ/2πC, and furthermore, the delay amount dn is quantized in units of quantization with a period of 270 or more of the transmission carrier wave.

The present invention will be explained in detail below with reference to the drawings.

4 and 5 are explanatory diagrams of one embodiment of the present invention, and FIG. 5 is a block diagram showing the configuration of one embodiment of the present invention. In order to make the principle of operation easier to understand, it is a functional block diagram that focuses on the operation.

In FIG. 4, the output signals of each sensor element 1□, . . . , 24 to a predetermined level. . ..., 38
The demodulated signal is delayed into a real part and an imaginary part set by
Further, the phase delay is compensated by the phase shifters 10□, . . . , 104.

The output of the phase shifters 10□, ..., 104 is sent to the adder 40
, 4□ to the real part and imaginary part set, the absolute value of the cumulative addition output is squared by the squarer 111. It is output from terminal 5.

In this embodiment, the propagation delay necessary for beam forming is compensated for by the variable delay lines 3□, . . .

38 and phase shifter 101.38. . . , 104, and the necessary compensation amount is determined by the delay controller 6,
and a phase controller 62.

In other words, the beam direction and the delay amount to be set for each sensor element are Dn (where n=1, 2..., 4),
Variable delay lines 31 and 32, 33 and 34. ..., 37 and 3
The delay amount of 8 is dn (however, n=1.2..., 4), and the phase amount ψn set for each sensor element (however, n=1, 2..., 4) The amount of delay obtained thereby is ψ.

When λ/2πC (λ is the wavelength of the transmitted carrier wave and C is the propagation speed of the transmitted carrier wave), Dn2ds+ψ.

Due to the relationship λ/2πC, the required delay amount Dn is determined by the variable delay line 31. ..., 38 and phase shifter 10□..., 104
Let them share the burden with each other.

In other words, since the variable delay lines 3□, . . . , 38 only need to compensate for the group delay of the input signal, the increments of the variable delay amount can be approximately a fraction of the rise time of the received pulse. For more detailed delay compensation, phase shifter 101. . . , 104.

In other words, the necessary delay amount Dn is determined by the variable delay line 31,...
238 and the phase shifters 10□, . Detailed delay amount ψ in quantization unit.

・Since λ/2πC is set by the phase shifters 101, . . . , 104, the quantization unit (i.e. delay step) of the variable delay lines 31, . This type of variable delay line can be easily realized because the transmission signal band can be changed from the carrier frequency domain to the video (baseband) domain.

Also, when performing dynamic focusing, the phase shifter 101. . . , 104, high-speed switching of the variable delay line is not necessary.

Furthermore, in this example, beamforming calculations are performed after conversion to a video signal, so digitization is easy.
Moreover, it can solve the drawback of the prior art (FIG. 2), which is that it cannot handle broadband signals.

FIG. 5 is a block diagram showing a configuration that performs the functions shown in FIG.
, 2N to a predetermined level, and is then amplified to a predetermined level by quadrature demodulator 90 . . . , 9N, and demodulated into a video signal by an analog-to-digital converter (A/D converter) 21□.

21□, . ..., 22N perform delay and phase compensation calculations, and the complex output thereof is cumulatively added to the real part and imaginary part set by the adding squarer 23, and after the absolute values are squared, they are added together and sent to the output terminal. Output from 5.

In this case, in order to keep the received signal level, which decreases over time from the time of pulse transmission, within the dynamic range of the orthogonal demodulator and A/D converter, the gain controller 20 controls each preamplifier 21 . . . . Apply a signal to control the gain of 2N.

However, this signal is generated simultaneously with the input of the trigger signal to the trigger signal input terminal 7.

Note that by using a simple A/D converter such as a combination of a delta modulator and a reversible counter, the cost of the apparatus can be reduced.

Each calculation unit 221. . . , 22N has a configuration as shown in FIG.

That is, for example, the outputs of A/D converters 211 and 212 are respectively applied to signal input terminals 311 and 312, written to random access memories (RAM) 321 and 32□, and read again after a necessary delay. The signal is output and input to an arithmetic circuit consisting of a multiplier 33, an adder/subtractor 34, and a register 35.

This arithmetic circuit is a COS ψ written in advance in a read-only memory (ROM) 36.

and sinψ. Using the data of exp(-iψ.

) and the input signal, and outputs the result from the output terminal 37.

The delay amount is written in the read-only memory 38 as a negative number, and this output and the output of the zero address counter 25 (FIG. 5), which increments each time a pair of input data is input, are added by the adder 39. This becomes the address of the random access memory 32□, 322.

However, it is assumed that the output of the read-only memory 38 is zero when writing data to the random access memories 320, 32□.

Further, the delay amount and phase amount to be compensated in this arithmetic unit are determined by the output terminals 240 and 242 of the controller 24 in FIG.
The addresses of the read-only memories 38 and 36 are changed by being switched by an address signal sent from the read-only memories 38 and 36.

Therefore, according to this example, dynamic focusing can be easily realized.

FIG. 7 shows the configuration of the addition squarer 23 shown in FIG.

Arithmetic unit 7 221. ..., 22N output is input terminal 371. ..., 37N, the real part and imaginary part of the output are sent to shift registers 41□, 41, respectively.
2.

The outputs of the shift registers 410 and 412 are sent to the adder 42□,
Two accumulators consisting of registers 43□ and 432 perform cumulative addition, and the results are sequentially selected by a selector 44 and applied to a squarer 45 to be squared.

The output of the squarer 45 is applied to an accumulator consisting of an adder 46 and a register 47, and the result is outputted from the output terminal 5 as a beamformer output.

As described above, according to the present invention, a receiving beamformer that handles high-frequency, wide-band signals can be easily realized using a general IC, and dynamic focusing is also easy, so that high-resolution ultrasound imaging equipment, etc. It can be realized easily and inexpensively.

Furthermore, when digitizing, delay and phase compensation amounts are written in read-only memory, so by increasing the capacity of this read-only memory or using rewritable read-only memory or random access memory, The screen format (number of scanning lines, range, scanning angle, etc.) can be easily changed, making it possible to realize a multifunctional, multipurpose video device.

As explained above, the reception beamformer according to the present invention has the advantage that it is possible to perform beamforming calculations after demodulating into a video signal, and that it can be easily digitized, resulting in less characteristic deterioration and that it can be realized at low cost. ing.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams each showing a conventional receiving beamformer, FIG. 3 is a block diagram showing a part of FIG. 2 in detail, and FIGS. 4 and 5 are one embodiment of the present invention. Fig. 5 is a block diagram showing its configuration, Fig. 4 is a functional block diagram shown to explain the operating principle of Fig. 5, and Figs. 6 and 7 are the same as Fig. 5. FIG. 2 is a block diagram showing a part of the . 11-14...sensor element, 2,-24...
...Preamplifier, 3, ~38...Variable delay line, 4□ ~43, 39°42, . 42°, 46...
・Adder, 5...Output terminal, 6,...
Delay controller, 6□... Phase controller, 7...
...Trigger input terminal, 91-94...Orthogonal demodulator, 101-104...Phase shifter, 111-
11□, 45...Squarer, 13...Carrier generator, 20...Gain controller, 21□~
21N...Analog-digital converter, 221~
22N... Arithmetic unit, 23... Addition squarer, 24... Controller, 25...
Zero address counter, 311, 31□, 371-37
4...Input terminal, 321, 32□...
Random access memory, 33... Multiplier, 3
4...Adder/subtractor, 35°430.43□, 47
...Register, 36, 38...Read only memory, 37...Output terminal, 411゜4
12...Shift register, 44...Selector.

Claims (1)

[Claims] 1. A demodulator that decomposes the output signals of N sensor elements into an in-phase component and a quadrature component of a transmission carrier wave having a wavelength of λ and a propagation speed of C, and a demodulator that converts the in-phase component and the quadrature component into digital codes. and an A/D converter that converts the digitally encoded in-phase and quadrature components into digital signals by a predetermined delay amount dn (n=1, 2..., N) for each sensor element. a delay means for delaying the delay, and a complex number in which the delayed in-phase component is the real part and the delayed orthogonal component is the imaginary part, and the complex number and the phase amount predetermined for each sensor element are set to ψ . (n=1.2°...,N) exp(-iψn)
a digital arithmetic circuit that performs complex multiplication with a complex number;
means for cumulatively adding the real and imaginary parts of the multiplication results, and means for squaring the absolute values of the cumulative addition results and adding the squared results to each other, at least for each sensor corresponding to a desired orientation. The required delay amount to be set to D
The delay amount dn is n(n-1y2p...,N)
and the phase amount ψ. and is Dn-dn ten ψ. - A reception beamformer that is set to maintain the relationship λ/2πC, and further characterized in that the delay amount dn is quantized in a quantization unit having a transmission carrier period of 270 or more. 2. The receive beamformer according to claim 1, wherein the delay means is a random access memory. 3. The receiving beamformer according to claim 2, comprising a digital memory storing information on the amount of delay in the delay means and information on complex multiplication coefficients in the digital arithmetic circuit, and means for switching the address of the information.