JPS6097279A - Phase detecting method - Google Patents

Phase detecting method

Info

Publication number
JPS6097279A
JPS6097279A JP20659083A JP20659083A JPS6097279A JP S6097279 A JPS6097279 A JP S6097279A JP 20659083 A JP20659083 A JP 20659083A JP 20659083 A JP20659083 A JP 20659083A JP S6097279 A JPS6097279 A JP S6097279A
Authority
JP
Japan
Prior art keywords
phase
pulse
buses
time
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20659083A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Iwashima
岩島 裕芳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TAKAMI DENKI KAGAKU KOGYO KK
Original Assignee
TAKAMI DENKI KAGAKU KOGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TAKAMI DENKI KAGAKU KOGYO KK filed Critical TAKAMI DENKI KAGAKU KOGYO KK
Priority to JP20659083A priority Critical patent/JPS6097279A/en
Publication of JPS6097279A publication Critical patent/JPS6097279A/en
Pending legal-status Critical Current

Links

Landscapes

  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE:To make it possible to achieve phase detecting work in an extremely safe and simple manner, by setting arbitrary one of buses as a reference bus while taking AC components from two remaining buses in a non-contact state and judging the timewise before and after relation thereof. CONSTITUTION:Freely openable and closable chip shaped electrode terminals T1, T2, T3 are attached to the insulating covers of three power source buses and AC components taken out from the power source buses at terminals T1, T2 in a non-contact state are amplified by an operation amplifier OP and a low frequency component is cut. A trapezoidal wave from the operation amplifier OP is differentiated by a differentiator circuit CR3 and inputted to reset set flip- flop. The pulse out of this RS-FF is inputted to an integrator circuit CR4 where only the rising part of the pulse is integrated and, because integration output becomes higher than a threshold level at the time of a positive phase, a light emitting diode LED emits light and generates no light at the time of an inverse phase.

Description

【発明の詳細な説明】 この発明は、三相交流の流れている3本の電源器線中任
意の1本を基準母線とし、残余の2つの母線から夫々交
流成分を非接触で取出してその交流波形が進行する時間
的先後関係を判定して正相・逆相を検出する検相方法に
関するものである。
Detailed Description of the Invention This invention uses any one of the three power supply wires through which three-phase alternating current flows as a reference bus, and extracts AC components from the remaining two busses without contact. The present invention relates to a phase detection method that determines the temporal relationship in which an AC waveform progresses and detects positive phase and negative phase.

3本の電線を使用して交流電力を送る三相交流では、第
1図に示すように各線に流れている電流の間には120
°ずつの位相差があり、また各線間の電圧相互間にもそ
の大きさは等しいが12o6ずつの位相差がある。この
三相交流の流れる三つの母線は便宜上R相、S相、T相
に区別されているが、例えば三相誘導電動機の如き負荷
を接続するに際しては電磁接触器のU相、■相、W相と
の各相を一致させる必要がある。そしてその接続を間違
えると負荷の回転方向が逆になったり、また誤作動によ
り電源系統がブレークダウンする原因となる。
In a three-phase AC system that uses three wires to transmit AC power, there is a distance of 120 degrees between the currents flowing through each wire, as shown in Figure 1.
There is a phase difference of 12 degrees, and there is a phase difference of 12o6 between the voltages between the lines, although the magnitudes are the same. For convenience, the three busbars through which the three-phase alternating current flows are divided into R phase, S phase, and T phase, but when connecting a load such as a three-phase induction motor, the U phase, It is necessary to match each phase with the phase. If the connection is incorrect, the direction of rotation of the load may be reversed, or a malfunction may cause a breakdown of the power supply system.

そこで三相交流における正相・逆相を検出表示するため
の計測手段として一般に検相器が知られている。しかし
ながら従来の検相器は、その検出プローブの端子に設け
たクリップを、三相交流が到来している活線の充電部に
直接挾持させて接続するものであって、高電圧が検相器
に印加されるという意味において極めて危険性が高いも
のであった。また前述したように活線の充電部にプロー
ブをクリップ接続するには、電磁開閉器や端子台、その
他制御盤等のケースを開放しなければならず、更に狭い
場所では検相作業自体が繁雑で困難を窮める問題がある
等、その改善が要請されている。
Therefore, a phase detector is generally known as a measuring means for detecting and displaying the positive phase and negative phase in three-phase alternating current. However, with conventional phase detectors, the clip attached to the terminal of the detection probe is directly clamped and connected to the live wire's live part where three-phase alternating current is coming. It was extremely dangerous in the sense that it was applied to Furthermore, as mentioned above, in order to clip the probe to the live wire's live part, it is necessary to open the case of the electromagnetic switch, terminal block, and other control panels, and furthermore, the phase detection work itself is complicated in a confined space. Improvements are being requested as there are problems that are making it difficult for the government to operate.

本発明は、三相交流を負荷に接続するに際し、正相・逆
相を検出区別して正しい接続を行う必要があることに鑑
み、前記欠点を良好に解決するべく提案されたものであ
って、三相交流における検相作業を極めて安全に、しか
も簡単な操作で達成し得るようにしたものである。
The present invention has been proposed in order to satisfactorily solve the above-mentioned drawbacks, in view of the fact that when connecting a three-phase alternating current to a load, it is necessary to detect and distinguish between positive and negative phases to make a correct connection. This allows phase detection work in three-phase alternating current to be accomplished extremely safely and with simple operation.

すなわち発明者は、前記検相作業を安全なものとするた
めには、従来の如く活線の充電部にプローブを直接接続
する方式を廃止し、非接触で検相を行う必要があること
を結論付け、その前提において試作検品・1を重ねた結
果、各母線の金属芯線と絶縁被覆との間には電界の強度
に応じた交流成分を静電容量として取出すことができ、
その関係はコンデンサと同様にみなし得ることに想到し
た。
In other words, the inventor found that in order to make the phase detection work safe, it is necessary to abolish the conventional method of directly connecting the probe to the live wire's live part and perform phase detection without contact. As a result of the conclusion and repeated prototype inspections based on this premise, it is possible to extract an AC component as a capacitance between the metal core wire and the insulation coating of each bus bar, depending on the strength of the electric field.
We came up with the idea that this relationship can be considered similar to that of a capacitor.

また三相交流における検相は、3本の電源母線のうち任
意の1本の母線を基準として、他の2本の母線につき正
相・逆相を決定すればよく、従って第2図に示すように
仮に3つの交流波形のうちT相を基準として時間軸にと
れば、他の2相(R相、T相)は時間差をもって波形進
行する2つの引伸ばされた交流波形の関係になり、正相
・逆相はこの時間的先後関係を判定すればよいことを併
せて突き止めた。
In addition, for phase detection in three-phase AC, it is sufficient to use any one of the three power supply buses as a reference and determine the positive phase and negative phase for the other two buses, as shown in Figure 2. If we take the T phase of the three AC waveforms as a reference on the time axis, the other two phases (R phase, T phase) will have the relationship of two stretched AC waveforms whose waveforms progress with a time difference, We also found that the positive and negative phases can be determined by determining this temporal precedence relationship.

従って本発明に係る検相方法は、三相交流が流れている
3つの電源母線の内任意の母線を基準とし、残余の2つ
の母線から夫々交流成分を非接触で取出すと共に低周波
数成分を除去し、この各交流成分を微分することにより
時間差を有する2つの立下りパルス波形を得、この2つ
の立下りパルスをフリップフロップにセットおよびリセ
ット条件として入力し、該フリップフロップをセットし
た後直ちにリセットすることにより短時間だけハイ(h
igh)となるパルスまたはセットした後火のリセット
まで若干の時間的余裕を有して長時間ノ)イ(high
)状21Mを維持するパルスの何れかを出力し、得られ
たパルスを積分することにより正相・逆相の何れかを表
示する表示手段を駆動するすることを特徴とする。
Therefore, in the phase detection method according to the present invention, any one of the three power supply buses through which three-phase alternating current flows is taken as a reference, and AC components are extracted from the remaining two buses without contact, and low frequency components are removed. Then, by differentiating each AC component, two falling pulse waveforms with a time difference are obtained, and these two falling pulses are input to a flip-flop as setting and reset conditions, and the flip-flop is reset immediately after being set. By doing this, it becomes high for a short time (h
After setting the pulse that becomes high) or setting it, there is a slight margin of time until the flame is reset.
The present invention is characterized in that it outputs any one of the pulses that maintains the ) shape 21M and integrates the obtained pulse to drive a display means that displays either the positive phase or the negative phase.

次に本発明に係る検相方法につき、好適な実施例を挙げ
て、以下詳細に説明する。第3図は本発明方法を実施す
るのに使用される一実施例としての回路例を示すもので
あって、当該回路における(A)〜(D)の個所におけ
る信号の様子を第4図にタイムチャートとして示す。各
端子T、 、 T2. T、は開閉自在なりリップ状の
電極端子として構成されて、三相交流の流れている3本
の電源母線の絶縁被覆上に着脱自在に取付けられるよう
になっている。
Next, the phase detection method according to the present invention will be described in detail using preferred embodiments. FIG. 3 shows an example of a circuit used to implement the method of the present invention, and FIG. 4 shows the state of signals at points (A) to (D) in the circuit. Shown as a time chart. Each terminal T, , T2. T is configured as a lip-shaped electrode terminal that can be opened and closed, and can be detachably attached to the insulation coating of three power supply buses through which three-phase alternating current flows.

なお前記3つの電極端子の内、’R端子は3本の電源母
線から任意に選択した基準母線に非接触で接続される。
Of the three electrode terminals, the 'R terminal is connected to a reference bus arbitrarily selected from the three power supply buses in a non-contact manner.

この基準母線は、第2図に示す波形図と一致させるため
に、仮にT相であるとしておく。
In order to match the waveform diagram shown in FIG. 2, this reference bus line is assumed to be in T phase.

他の2つの端子T、および−は、夫々残りの電源母線に
同じく非接触で接続されるが、この時点ではこの母線が
R相なのかS相なのかは勿論判明していない。
The other two terminals T and - are respectively connected to the remaining power supply bus in a non-contact manner, but it is of course unclear at this point whether this bus is in the R phase or the S phase.

前記2つの端子−およびT2は、全く同じ構成からなる
回路AおよびBに夫々入力接続されている。
The two terminals - and T2 are connected as inputs to circuits A and B, respectively, which have exactly the same configuration.

この回路A(B)は、例えばCMOSデジタルTCと、
微分回路とから基本的に構成され、前記端子”r、 (
72)から取出した交流成分を増幅および波形の整形処
理するものである。すなわち端子毛において電源母線か
ら非接触で取出された交流成分は、オペアンプOPによ
り増幅されるが、このとき当該オペアンプOPに介装し
た抵抗P、により適正な増幅率に設定される(増幅率が
鋭敏すぎると外来ノイズを拾い易くなり、増幅率が低す
ぎると取出した交流成分を有効に信号処理し得ない)。
This circuit A (B) includes, for example, a CMOS digital TC,
It basically consists of a differential circuit, and the terminals "r, (
72) is amplified and waveform shaped. That is, the AC component extracted from the power supply bus at the terminal hair without contact is amplified by the operational amplifier OP, but at this time, the appropriate amplification factor is set by the resistor P inserted in the operational amplifier OP (the amplification factor is If it is too sensitive, external noise will be easily picked up, and if the amplification factor is too low, the extracted AC component cannot be effectively signal-processed).

また同じく前記オペアンプOPに介挿した抵抗語により
、例えば交流成分中60Hz以下の低周波数成分はカッ
トされる。このため回路Aの(A ) Aには、第4図
(A)に示す如く過剰増幅分がスライスされた台形波T
、が表われ、また回路Bの(A)点にも同じく台形波T
7が表われる。但し側台形波−1−は、その基となる交
流が相互に時間的先後関係をもって波形進行しているの
で時間差Tdを有している。
Furthermore, by using the resistor inserted in the operational amplifier OP, for example, low frequency components of 60 Hz or less among the AC components are cut. Therefore, in (A)A of circuit A, there is a trapezoidal wave T in which the excessive amplification is sliced, as shown in Fig. 4 (A).
, appears, and a trapezoidal wave T also appears at point (A) of circuit B.
7 appears. However, the side trapezoidal wave -1- has a time difference Td because the alternating currents that form the basis of the waveform progress with respect to each other in time.

前述した第4図(A)に示す台形波T、および−は、夫
々の回路AおよびB中のコンデンサCおよび抵抗P3か
らなる微分回路において微分され、第4図(B)に示す
如き立下りパルス波形に整形されるにの時間差を有して
単発的に立下るパルスは、後段に設けたリセットセット
・フリップフロップ(R3−FF)にリセット信号およ
びセット信号として入力される。すなわち第4図の(B
)に示す一方の立下りパルスT、は、他方の立下りパル
ス−に比べて時間的に先行しているから、前記フリップ
フロップ(R3−FF)に立下りパルスT、が先に入る
と該ブリップフロップをセット(S)するが、時間差T
dをおいた後直ちに後続の立下りパルス−が到来して該
フリップフロップをリセット(R)する。従って第3図
に示す回路中の(C)点には、第4図Q、に示す如く、
ハイ(high)になっている時間の短い非対称のパル
ス波形が得られる。また前記フリップフロップ(R3−
FF)に立下りパルス−が先に入ると、該フリップフロ
ップをセット(s)し若干の時間的余裕を経た後、該フ
リップフロップをリセット(R)するので、第4図のQ
2に示す如くハイ(high)になっている時間が比較
的長い非対称のパルス波形が得られる。
The trapezoidal waves T and - shown in FIG. 4(A) described above are differentiated in differentiating circuits consisting of capacitors C and resistors P3 in circuits A and B, respectively, and fall as shown in FIG. 4(B). A pulse that falls singly with a time lag before being shaped into a pulse waveform is input as a reset signal and a set signal to a reset set flip-flop (R3-FF) provided at a subsequent stage. In other words, (B
Since one falling pulse T, shown in ) is temporally earlier than the other falling pulse -, if the falling pulse T, enters the flip-flop (R3-FF) first, the falling pulse T, shown in FIG. The flip-flop is set (S), but the time difference T
Immediately after d, a subsequent falling pulse arrives to reset (R) the flip-flop. Therefore, at point (C) in the circuit shown in Fig. 3, as shown in Fig. 4 Q,
An asymmetric pulse waveform with a short high time is obtained. Moreover, the flip-flop (R3-
When the falling pulse (FF) enters first, the flip-flop is set (s) and after some time, the flip-flop is reset (R).
As shown in FIG. 2, an asymmetric pulse waveform having a relatively long high time is obtained.

このように第4図に示すQ、またはQ2の何れかのパル
ス波形を選択的に得た後、このパルス波形を抵抗P4お
よびCで摺成される積分回路に入力し、ダイオードD、
により該パルスの立」ニリ部分のみ積分して立下り部分
は積分しないよう処理することにより、(D)点には第
4図に示す如き波形が得られる。この波形信号により適
宜の表示手段を駆動して正相・逆相を表示する。例えば
本実施例では、前記波形は後段のオペアンプOPにより
増幅されるが、第4図のQ?に示すような波形の場合は
スレッシュホールドレベルより上なので、発光ダイオー
ドL E Dは発光して正相であることを検査者に見知
させる。しかしながら第4図のQ、に示すような波形の
場合は、スレッシュホールドレベルより下になるため発
光ダイオードLEDは発光せず、逆相であることを示す
ことになる。なお表示手段としては各種のものが考えら
れるものであって、電子ブザー等の音発生手段を使用し
て警告音により検査者に見知させたり、当該警告音を連
続音と断続音とに区別したり、発光表示と音響表示との
組合せを併用したりすることが提案される。
After selectively obtaining the pulse waveform of either Q or Q2 shown in FIG. 4 in this way, this pulse waveform is input to an integrating circuit formed by resistors P4 and C,
By integrating only the rising edge and not integrating the falling edge of the pulse, a waveform as shown in FIG. 4 is obtained at point (D). This waveform signal drives an appropriate display means to display the positive phase and negative phase. For example, in this embodiment, the waveform is amplified by the operational amplifier OP in the subsequent stage, but Q? In the case of a waveform as shown in , since it is above the threshold level, the light emitting diode L ED emits light to let the inspector know that it is in the correct phase. However, in the case of a waveform as shown in Q in FIG. 4, the light emitting diode LED does not emit light because it is below the threshold level, indicating that the phase is reversed. Various types of display means are possible, such as using a sound generating means such as an electronic buzzer to make the inspector aware of the warning sound, or distinguishing the warning sound into continuous sound and intermittent sound. It has been proposed to use a combination of a luminescent display and an acoustic display.

以上詳細に説明したように、本願発明に係る検相方法に
よれば、3本の電源母線中任意の1本を基準母線とし、
他の2本の電源母線から交流成分を非接触で取出して時
間差を有する2つのパルス波形を得、この2つのパルス
波形の時間的先後関係により、ハイ(high)になっ
ている時間が長いパルス波形または短いパルス波形を得
て、これにより発光手段、音響手段等の表示手段を駆動
して正相・逆相の状態を見知させるものであって、三相
交流が流れている活線に対し非接触で検相し得るので極
めて安全である。また各電源母線の絶縁被覆上にプロー
ブ端子をクリップで取付けるだけの簡単な操作でよいた
め、端子盤や開閉器のケースを開ける手間が不要で使用
する場所を選ばない等、多くの有益な利点を有する。
As explained in detail above, according to the phase detection method according to the present invention, any one of the three power supply buses is used as a reference bus,
The AC component is taken out from the other two power buses without contact to obtain two pulse waveforms with a time difference, and due to the temporal precedence relationship between these two pulse waveforms, the pulse remains high for a long time. It obtains a waveform or short pulse waveform and uses it to drive a display means such as a light emitting means or an acoustic means to tell the state of normal phase and reverse phase. On the other hand, it is extremely safe because phase detection can be performed without contact. In addition, the simple operation of attaching the probe terminals to the insulation coating of each power bus bar with clips is sufficient, so there is no need to open the terminal board or switch case, and it can be used anywhere. has.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は三相交流の波形図、第2図は三相交流のうち1
つの電源母線を基準としてこれを時間軸にとった場合に
おける他の2つの電源母線に流れる交流波形の説明図、
第3図は本発明に係る検相方法を実施するのに使用され
る回路例の結線図、第4図は第3図に示す回路の(A)
〜(D)の各点における信号の状態を示すタイミングチ
ャート図である。
Figure 1 is a waveform diagram of three-phase AC, and Figure 2 is one of the three-phase AC.
An explanatory diagram of AC waveforms flowing through two other power supply buses when one power supply bus is taken as a reference and this is taken as a time axis,
FIG. 3 is a wiring diagram of an example of a circuit used to implement the phase detection method according to the present invention, and FIG. 4 is a diagram (A) of the circuit shown in FIG.
It is a timing chart figure which shows the state of the signal at each point of - (D).

Claims (1)

【特許請求の範囲】[Claims] 三相交流が流れている3つの電源母線の内任意の母線を
基準とし、残余の2つの母線から夫々交流成分を非接触
で取出すと共に低周波数成分を除去し、この各交流成分
を微分することにより時間差を有する2つの立下りパル
ス波形を得、この2つの立下りパルスをフリッププロッ
プにセットおよびリセット条件として入力し、該フリッ
プフロップをセラ1−シだ後直ちにリセットすることに
より短時間だけハイ(high)となるパルスまたはセ
ラ1へした後火のリセットまで若干の時間的余裕を有し
て長時間ハイ(high)状態を維持するパルスの何れ
かを出力し、得られたパルスを積分することにより正相
・逆相の何れかを表示する表示手段を駆動することを特
徴とする検相方法。
Using any one of the three power supply buses through which three-phase alternating current flows as a reference, extracting AC components from each of the remaining two buses without contact, removing low frequency components, and differentiating each AC component. obtain two falling pulse waveforms with a time difference, input these two falling pulses to a flip-flop as a set and reset condition, and reset the flip-flop immediately after switching to a high level for a short period of time. Output either a pulse that becomes high (high) or a pulse that maintains a high state for a long time with some time margin until the fire is reset after being sent to cellar 1, and integrate the obtained pulse. A phase detection method characterized by driving a display means that displays either a positive phase or a negative phase.
JP20659083A 1983-11-01 1983-11-01 Phase detecting method Pending JPS6097279A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20659083A JPS6097279A (en) 1983-11-01 1983-11-01 Phase detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20659083A JPS6097279A (en) 1983-11-01 1983-11-01 Phase detecting method

Publications (1)

Publication Number Publication Date
JPS6097279A true JPS6097279A (en) 1985-05-31

Family

ID=16525919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20659083A Pending JPS6097279A (en) 1983-11-01 1983-11-01 Phase detecting method

Country Status (1)

Country Link
JP (1) JPS6097279A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0642507A (en) * 1992-07-20 1994-02-15 Akio Matsui Pressure intensifying fluid pressure cylinder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0642507A (en) * 1992-07-20 1994-02-15 Akio Matsui Pressure intensifying fluid pressure cylinder

Similar Documents

Publication Publication Date Title
US6731102B2 (en) Electronic test instrument with extended functions
JPS6097279A (en) Phase detecting method
JP2940658B2 (en) Track circuit short circuit
RU2121150C1 (en) Continuous following system for controlling alternating current supply system electric conductivity
JPH0772739B2 (en) Analog tester
JP4108426B2 (en) Low frequency AC current detector
RU2097892C1 (en) Ac relay
JPS59220077A (en) Inverter with abnormality detecting circuit
JP2540553Y2 (en) LCD filter disconnection detector
SU1019349A1 (en) Direct current frequency-type pickup
JPS6469962A (en) Detecting apparatus of contact resistance
SU880224A1 (en) Device for measuring electric pulse signals
KR880014724A (en) How to convert alternating current into direct current without using magnetic force
KR20010077121A (en) method and apparatus for protecting of power circuit
SU723714A1 (en) Arrangement for short circuiting current protection of electric circuits
KR0139897Y1 (en) Dc link voltage detection circuit
SU966628A1 (en) Integrated ciruit testing device
SU1307379A1 (en) Phase comparator
JPH05292742A (en) Switching power supply
JPS59103285U (en) Electric circuit insulation monitoring device
JPH04351496A (en) Driver for induction motor
TW200514328A (en) Power source monitoring device and power inverter with the power source monitoring device
JPS6459512A (en) Temperature controller
JPS57168171A (en) Phase sequence checking apparatus
JPS61253471A (en) Detection circuit for direction of rotation