JPS609390A - Ripple reducing circuit of signal with ripple - Google Patents

Abstract

PURPOSE:To accelerate the responding speed at a load varying time by providing a plurality of filters of different responding speeds and ripple reducing rates to an input signal, and sequentially outputting stepwisely the faster one of the responding speeds to slower one. CONSTITUTION:The output voltage Vt of a tachometer generator 4 is converted by a ripple reducing circuit 6 to a voltage Vt', and fed back to an addition point 1. The reducing circuit 6 has filter amplifiers 11-13 of different responding speeds and ripple reducing rates to an input signal, ripple reduction signals A-C are processed by subtractors 21, 22, adders 24, 26, and nonlinear circuits 23, 25 for eliminating the ripple in the normal state of the ripple reduction signal, and sequentially outputted stepwisely from the faster responding speed to slower speed. In this manner, the responding speed at the load varying time is accelerated, and the ripple in the normal state can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application The present invention relates to a ripple reduction circuit for converting a signal with a reduced pull rate.

BACKGROUND OF THE INVENTION A ripple reduction means for converting a signal having a ripple rate into a signal with a reduced kripple rate is known, and is applied, for example, to a speed servo system as shown in FIG.

In FIG. 1, the difference voltage Δ■ obtained by adding the speed command voltage Vc and the feedback voltage vt' (described later) to the addition point 1 is amplified by the amplifier 2, and then the servo motor 3
is applied to. A speed generator 4 for detecting the rotational speed of the servo motor is directly connected to the servo motor 3.
lFrom this speed generator 4, a voltage Vt proportional to the rotational speed is generated.
is output, and this voltage is passed through the Okiha circuit 5 to the voltage Vt'
It is converted into and fed back to the addition point IVC. In this case, the servo motor 3 rotates at a speed corresponding to the speed command voltage Vc. In this case, the voltage Vt output from the speed generator 4 is affected by brushes, etc. Since the ripple voltage is included in the equation, if the voltage Vt is fed back to the summing point 1 as it is, the ripple rate will increase when the gain of the amplifier 2 is high.
As the servo motor 3 rotates, the pull voltage may cause the modulation to be distorted or undulations to occur. Particularly, when the ripple rate is large in a steady state of rotation, rotation ripples occur and the performance of the speed servo system deteriorates.

For this reason, conventionally, in order to reduce such ripples m, fJ:, the output waveform LIEVt from the velocity light ttE 4 is connected to the lithography (
1(: p+) and fed back by converting it into a voltage Vt'.
By determining the values of elements such as j, a certain ripple reduction effect can be obtained.

However, in the above-mentioned conventional circuit, if the ripple reduction effect is increased, the time constant determined by the above-mentioned element increases, so there is a drawback that the response speed becomes slow during load fluctuations, etc. .

For example, when controlling machine tools, the second
As shown in the figure, at time t1, when the tool of the go machining machine contacts the workpiece and suddenly becomes loaded, the rotational speed of the servo motor 30, that is, the voltage Vt output from the speed generator 4 increases. When the load changes like this, iJ decreases as ΔV increases.

Very fast response speed is required, but (if not 1i +
In l rN, the ripple reduction effect of the P-wave circuit 5 is increased at time t, and at time t, a relatively long time Δt has elapsed.

The output voltage Vt cannot be returned to the original unless it reaches Vt, which has the disadvantage that the response speed becomes extremely slow.

For this reason, there has been a strong demand for the development of ripple reduction means that can sufficiently reduce the ripple in a steady state while maintaining a fast response speed.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problem 811, and its object is to provide a ripple system that has a fast response speed to transient states during load fluctuations and can sufficiently reduce ripples in a steady state. A ripple reduction circuit of the present invention is constructed as follows in order to achieve the above object.

A plurality of Oki wave generators each receiving a signal containing ripple as input and outputting a different ripple reduction signal by changing the response speed and ripple reduction rate of the output to the input (M) in stages, It consists of a combination of 2g and a nonlinear circuit in monopolization j'!i'J jj+24λ
Arithmetic processing is performed on the signal outputted from the oscillating device of step '4, and the output signal of each of the oscillators is outputted in stages from the fastest response speed to the slowest response speed, and the steady state of the human input signal is In the Hama 7ij-dokoro J! 1Ipl J
, I got ripple reduction before the ripple in the signal :)! ] Non-wire 1 [, 6 circuits to eliminate the signal processing circuit +
1. At the beginning of the response to changes in human labor, Q'
, before N(''+ Outputs a signal with a small noise reduction rate among the output signals of the plurality of P-wave devices, and the input signal is like 1-
Next a′! The present invention is characterized in that it outputs a signal with a large ripple reduction rate when the input signal is in a steady state, and outputs a signal in which ripples have disappeared in the steady state of the input signal.

EXAMPLE The preferred iR product 1 (11) of the present invention will be described in detail based on the following aspects.

Figure aR3 shows an embodiment of the ripple reduction circuit according to the present invention, in which parts corresponding to those in Figure 1 are denoted by the same reference numerals. As is clear from the figure, the output (1i11) of the speed generator 1L generator 4 is provided with the ripple reduction circuit 6 of the present invention, and the voltage Vt output from the speed generator plate 4' is changed to the voltage ■t' by this ripple reduction circuit 6. is converted into and fed back to the boundary point 1.

FIG. 4 shows a specific example of the block configuration of the ripple reduction circuit 6. Ripple reduction circuit 6 of this embodiment
An input terminal IO receives the voltage Vt outputted from the speed generator 4 via a level expander (not shown), and a plurality of five-wave amplifiers 11 to 13 each inputs the signals received at the input terminal. These P-amplifiers 11 to 13 bridge a parallel connection circuit of a resistor and a capacitor between the input and output terminals of an operational amplifier, respectively. 7 with a time constant determined by the above resistors and capacitors, respectively.
? It is set so that a constant Ir response speed and ripple reduction rate can be obtained. In this embodiment, the Y wave amplifier 11 has the highest response speed, the ripple reduction rate of J6 is also set to be small, and the PilQ amplifier 11i, tp;
2 has a faster response than the Okinami amplifier 11.
The ripple reduction rate is set large, and the response speed of the p pump J1υ-13tj and the f# wave amplifier 12 is also 17' (
is J1′! In Lament, the ripple reduction rate is set high. %Y1 is speed power generation] From 4, the voltage signal Vt is input to the input terminal 1. If OK, each p-wave amplifier 11-1
From 3 onwards, rough reduction signals A, B, and C with different response speeds and ripple low-state rates are output.

Further, the ripple reduction circuit 6 includes the r-wave J19 width amplifier 1.
Ripple reduction signal A output from 1 to 13.

A signal processing circuit 20 is provided that performs arithmetic processing on B and C and contributes to steady state ripple reduction.

This signal processing circuit 20 includes subtracters 21 and 22, adders 24 and 26, and a nonlinear circuit 23. ．． 25 is the circuit β group,
This is a circuit that operates to eliminate the ripple in the steady state of the ripple reduction signal that is outputted.Each nonlinear circuit 23 For example, 030 is the output of the ripple reduction circuit 6, and the signal output from the output CM and 1 is at the l/') level (not shown). After the level is compressed by the compressor, it is fed back to the addition point 1 of h, 31ru.Next, H',
I will explain about ij's work.

Now, time t. When the voltage signal Vt is input to the input terminal as shown in Figure n15, the p-wave width amplifier 11~
From 13 onwards, J5 as shown in Figures 6 to 8 respectively.
Ripple reduction signals A, B, and C having the response speed and ripple reduction rate are output.

The above ripple reduction signals A and B are input to the subtracter 21, and the subtracter 21 outputs a ripple reduction signal r-(A-B)J having an absolute value waveform as shown in FIG. . This ripple reduction signal is input to the nonlinear circuit 23, and from the nonlinear circuit 23, as shown in FIG. 10, the ripple voltage in the steady state is eliminated.
A ripple reduction signal of 1"r is output.

In fact, the ripple reduction signals B and C are reduced by (11 units 2
2, and from the subtracter 22 it is shown as m 1113<l, and is output from the nonlinear circuit 23 [-(8-B)
The ripple reduction signal 'j and the ripple low-scale 4 signal r-(B-C)J output from the reducer z2 are sent to the adder 2.
4, and the adder 24 outputs a lip reduction signal of 1(A-B)'+(B-C)j having an absolute value waveform as shown in FIG. The ripple reduction signal B is input to the non-linear circuit 25, and from the non-linear circuit 26, the ripple voltage in the steady state of the ripple reduction signal is eliminated, and the absolute value waveform 1 (
A lip reduction signal (A-B)'+(I3-C))'J is output.

Furthermore, the ripple reduction signal output from the nonlinear circuit 25 and the ripple reduction signal C output from the p-wave amplifier 13 are input to a coupler 26, and from the adder 26, the first
4]K As shown, 7J: r-((((
A Litz reduction signal of A-B)'+(J3-c>l'+c+J is output).

In this way, the ripple reduction circuit 6 of this embodiment reduces the ripple 46 output from the amplifiers 11 to 13).
A ripple 1 reduction signal consisting of a combination of numbers A, B, and C is output, and among the outputs of the F-wave amplifiers 11 to 13, the response speed is changed from fastest to slowest) for each output of 1σ. A, B, and C are output step by step through 16F.

As a result, for example, when controlling a machine tool, the following operations are performed.

As shown in FIG. 15, at time L1, when the tool of ``C machining 4'' comes into contact with the workpiece pc and suddenly becomes negative, the rotation of the servo motor 3 decreases by -1. Speed j end, that is, 1 pressure Vt output from speed generator 4
suddenly decreases by ΔVt. Thereafter, at the initial stage of response to this voltage change, ripple low pull reduction signals B and C are sequentially output. Therefore, even when a load fluctuation occurs as described above, the voltage Vt is recovered at a fast response speed, that is, in an extremely short time Δt', and the ripple rate is sufficiently reduced in the steady state of the voltage Vt. Ru.

Modification In the embodiment described above, three r-wave amplifiers were used, as shown in FIG. 16, for example. Two Okinami amplifiers 11, 12 may be used, as shown in FIG. Vessels 24, 26, 2
9, and using nonlinear circuits 23.25.28, 1
．． <, P ill Jff IfFf By increasing the number of detectors, the response speed and ripple reduction rate can be further improved.

Furthermore, in the embodiments described above, a case was shown where the tJl and ripple reduction circuit was applied to a feedback circuit, but the ripple reduction circuit of the present invention can also be applied to an open loop circuit.

As described in detail, according to the present invention, a plurality of filters having different response speeds and ripple reduction rates to input signals in stages are provided.
The ripple reduction signals output from each wave transmitter are processed, and the signals are output in stages from the fastest response speed to the slowest response speed, so load fluctuations, etc. According to the present invention, in the steady state of the input signal, the ripple of the ripple reduction signal obtained by the arithmetic processing is eliminated by the nonlinear circuit. ,
Ripples such as noise in a steady state can be sufficiently reduced. Therefore, the present invention can be used in a speed control system of a servo motor, etc. to perform extremely good speed control.

[Brief explanation of drawings]

Fig. 31 is a block 4ff diagram showing the speed control system of a servo motor using a conventional P-wave circuit, Fig. 2 is a -j characteristic curve diagram showing the output voltage characteristics of the p-wave circuit in Fig. The figure is a block diagram of a speed control system of a servo motor to which the ripple reduction circuit according to the present invention is applied. 1411g1 is a voltage waveform diagram of each part in the circuit of FIG. 4, FIG. 21115 is a row 1 raw curve diagram that does not show the output voltage characteristics of the circuit of FIG. 4, and FIGS. 16 and 17 are different diagrams of the present invention. FIG. 2 is a block configuration diagram showing an example. 6... Ripple reduction circuit, 11-14... P wave J'
l? Width gauge, 20...Signal processing circuit, 21, 22.27
...Reducer II, 24, 26.29...Adder, 23
．． 25゜28...Nonlinear circuit 〇 Agent Patent attorney Hidetoshi Matsuki

Claims (1)

[Scope of Claims] A plurality of F-wave devices each receiving a signal containing +11 1J tuples and outputting a different ripple reduction signal by varying the output response speed and ripple reduction rate in response to the input signal in stages; The signals output from the plurality of filters are processed by a combination of a random number of arithmetic units and non-linear circuits, and the output signals of the P-wave filters are classified from those with fast response speeds to those with slow response speeds. and a signal processing circuit that sequentially outputs ripples in a step-by-step manner and, in a steady state of the input signal, eliminates ripples in the ripple reduction signal obtained by the arithmetic processing by the nonlinear circuit. Signal ripple reduction circuit. (2; The P-wave device is provided with six P-wave devices, first, second, and third, in the fast response speed 11R1, and the signal processing circuit is connected to each of the first and second P-wave devices. a first subtractor receiving each output; a second subtractor receiving each output of the second and third filter; and a first nonlinear subtractor receiving the output of the first subtractor. a first adder receiving each output of the i3 nonlinear circuit and the second p-reducer, a second nonlinear circuit receiving the Φ force of the adder, and the second nonlinear circuit. and a second q adder receiving each output of the fifth P-wave device.
ripple reduction circuit for signals containing ripples.