JPS6092631A - Dielectric isolation type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To stabilize the operation of a circuit, and to increase density and the degree of integration by connecting one part of a wiring, through which a large amplitude signal is conducted, to a polycrystalline semiconductor substrate through a diode having high withstanding-voltage stopping power. CONSTITUTION:A plurality of first conduction type single crystal semiconductors 13 electrically insulated and isolated by dielectric isolating films 12 (SiO2 films) are formed on the main surface side of a polycrystalline semiconductor substrate 11. First conduction type high-concentration buried layers 14 are formed to the bottom sections and side surface sections of the single crystal semiconductors 13. The main surface is coated with the surface insulating film 15, and second conduction type diffusion layers 16a, 16b and first conduction type diffusion layers 17 are formed through a selective diffusion method using the surface insulating film 15 as a mask. Metallic wirings 18a and 18b are each connected to anodes and cathodes for diodes in an ohmic manner. The metallic wirings 18a are connected to wirings having an opportunity, where potential is maximized, in a pellet on the operation of a circuit. The metallic wirings 18b are connected further to the polycrystalline semiconductor substrate 11 in an ohmic manner through the diffusion layers 16b.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a dielectrically separated semiconductor integrated circuit, and in particular provides a structure that realizes a high integration density and stable high breakdown voltage semiconductor integrated circuit.

Dielectric isolation, which is one of the element isolation structures of semiconductor integrated circuits (hereinafter referred to as IC), has a +11 element isolation that is bidirectional compared to the most widely used PN junction isolation. , (Il+ dielectric strength voltage is high, (DC parasitic current leakage to the board does not occur)% (IV5
It is clearly superior in terms of high breakdown voltage, such as having a large degree of freedom in selecting the resistivity of the island, and therefore, one of its major application fields is the high breakdown voltage IC field.

As is well known, in the field of high-voltage ICs, circuits are often required to process large-amplitude currents or signals. For example, high-voltage ICs for AC/DC control, which are used in many home appliances, are an example of the former, and integrated circuit type access switches for subscriber circuits of telephone exchanges that process bell signals are an example of the latter. In such applications, dielectric isolation structures are used and the isolation between devices is bidirectional, and the substrate is traditionally either left floating or fixed at ground potential. Ta. The present invention was made based on experimental knowledge discovered by the inventors while conducting research on the practical application of dielectrically separated high voltage ICs. below,
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Problems occurring in conventional structures, principles and embodiments of the present invention for solving the problems will be explained in detail with reference to the drawings.

Figure 1 shows the semiconductor switches (P
This is a list showing experimental results in which the 13T bias direction during a high temperature voltage application test (hereinafter referred to as BT test) of a PNPN switch (NPN switch) corresponds to the direction in which deterioration of the PNPN switch occurs. In FIG. 1, the forward direction is the direction from the anode to the cathode in the PNPN switch, and the reverse direction is the opposite. Furthermore, the occurrence of deterioration referred to here means that the withstand voltage as measured at a current of 10 μA has decreased, and from another investigation (measuring the current-voltage characteristics), the deterioration here is not a decrease in breakover voltage, but rather a decrease in leakage current. It has been found that there has been an increase in What should be noted in the experimental results shown in FIG. 1 is that the deterioration occurs on the forward direction side, regardless of the direction of the BT bias.

Another experimental finding regarding the deterioration in the BT test is that the temperature characteristics of the forward breakdown voltage of the PNPN switch are significantly deteriorated by the BT test, as shown in FIG. The close relationship between the temperature characteristics of withstand voltage and the N+ buried layer is described, for example, in "Reliability of High Voltage Subscriber Circuit LSI" (Masamichi Mori et al., Institute of Electronics and Communication Engineers Technical Research Report R83-19), pages 44 to 45. The manner of deterioration of the temperature characteristics in the above experiment conducted by the inventors is also extremely similar to the phenomenon described in the above literature. N This is thought to be related to the buried layer.

FIG. 3 shows the states of the forward biased and reverse biased switches during the BT test. IC
The structure has a large number of element regions separated by 5-ins films 2 in a polycrystalline semiconductor l, and each element region is formed with a silicon risk as a PNPN switch 50° and 60°. First, in the forward bias switch 50, during the BT test, the highest potential is applied to the 7 node A, and the lowest potential or the ground potential is applied to the cathode K.

A depletion layer 3 is generated at the junction between the A- and N- islands as shown in the figure, and almost all of the voltage is applied there. In that state, the potential of N-island is t
1 anode potential (within the pellet, separated for 5 ins) The mobile ions in the membrane 2 are moved in the direction of the arrow in the figure (from the N island side to the polycrystalline semiconductor substrate 0111 in the BT test. However, when the ions are ■, the O ions are in the opposite direction) (direction) to lift (to move with a bias).

Also, in the reverse bias switch 60, the potential of the N-island is the same as the cathode potential (the highest potential in the pellet), and the polycrystalline semiconductor substrate is floating (
In the conventional structure, which is fixed at ground potential (floating state) or fixed at ground potential, the mobile ions in the separation 5i01 membrane 2 are
In the test, the ion drifts in the direction of the arrow in the figure (from the N-island side to the substrate side when the 0■ ion is present).

As is clear from the above description, the separation 8i0. The direction in which the mobile ions in the film 2 drift is the same regardless of the direction of the bias applied to the PNPN switch during the BT test, and in terms of positive charges, they drift from the N-island side to the polycrystalline semiconductor substrate side. It is the direction. Due to the drift, free electrons that have been attracted to the crystal surface of the fiN island (surface portion of the N+ buried layer) are driven into the interior of the crystal. FIG. 4 shows this aspect.

That is, it shows how the effective concentration profile of the N+ buried layer is affected by the drift of possible ions in the isolated Sin film.

The surface charge amount of the separated 8i 02-8i interface, which varies in the BT test, is 1010 according to the inventors'
~tollq-cIrL-2, which has a sufficient effect on the N+ buried layer surface concentration of 10110 l6''.
The reason for this is that the N+ buried layer contains antimony (sb
), arsenic (As), and other impurities with small diffusion constants are used, but even so, thermal diffusion occurs during the heat treatment applied to the formation of isolated Si, film, and formation of polycrystalline semiconductor formation-blocking PN junctions. The phenomenon of suppressing the amount by which the layer reduces the N- island thickness and reducing the breakover voltage due to electric field concentration occurring at the intersection between the surface portion of the N+ buried layer and the lead wire from the high voltage blocking PN junction. In order to alleviate this, there is a limit of 6D on the amount of impurities to be doped (added), and therefore the surface concentration is kept to a relatively low level as described above.

There are two methods for technical countermeasures against deterioration caused by BT testing. One is to increase the surface concentration of the N 2 buried layer to a level where fluctuations in surface charge do not affect it. For this purpose, the N bulk (single crystal) must be made thicker than the above-mentioned N
It is necessary to technically overcome the local breakdown that occurs at the intersection between the buried layer surface and the lead wiring.

Now, one method is to determine the cause of the deterioration. This is a technical countermeasure against the problem caused by the drift of mobile ions in the film in the direction of depleting (depleting) the surface of the N bulk (N− island + N+ buried layer). Of course, reducing or inactivating the amount of mobile ions in the separated Sin film during the process is an effective technical measure, but the potential during operation of the polycrystalline semiconductor substrate (including during BT testing) is the highest potential. The above-mentioned BT deterioration can also be overcome by increasing the bias voltage to the separation sinus film and not applying a bias in the direction of depleting the N bulk surface to any N bulk in the pellet.

The present invention focuses on the disadvantages of the novice and provides a dielectrically isolated semiconductor integrated circuit without BT deterioration.

Hereinafter, the principle and structure of the present invention will be explained based on examples.

FIG. 5 is a sectional view showing an embodiment of the present invention.

That is, on the main surface side of the polycrystalline semiconductor substrate 11, a dielectric isolation film i2 (in the example, an 8i0. film of 2 to 3 μm) is provided.
The first of the plurality of cylinders is electrically insulated and separated.
Conductivity type (N type in the case of the example) single crystal semiconductor 13 (in the case of the example, resistivity 1O~30Ω-I, thickness 30~6
0 μm).

A first conductivity type high concentration buried layer 14 is provided on the bottom and side surfaces of this single crystal semiconductor 13.

In the embodiment, an N-type impurity having a small diffusion constant, such as antimony (sb) or arsenic (As), was used to form the first conductivity type high concentration buried layer 14. Doping concentration is 7X10"~5X1016cIrL
It is about -3. The main surface is covered with a surface insulating film 15, and a second conductivity type diffusion layer 168° 16b and a first conductivity type diffusion layer 17 are formed by a selective diffusion method using the surface insulating film 15 as a mask. There is. In the embodiment, the diffusion layers 16a and 16b were formed by diffusing and polarizing boron as an impurity to a depth of 2 to 10 μm. , In addition, in forming the diffusion layer 17, phosphorus is used as an impurity to form the diffusion layer 17 at a depth of 0.
．． It was formed by spreading to 5 to 3 μm. Predetermined electrical connections are made using metal wirings 18a and 18b to complete the process.

In the case of this embodiment, processed aluminum thin films with a thickness of 1 to 3 μm are used for the metal wirings 18a and 18b. Further, metal wirings 18a and 18b'1. TM
Kka, work em, 511Cu-f! l. 1. . , 7-2
A 5 μm 5i02 film is used. Metal lines 18a and 18b are ohmically connected to the anode and cathode of the diode, respectively, as shown in FIG. Further, the metal wiring 18a is connected to a wiring that has a chance of reaching the highest potential within the pellet (or may be called inside the circuit) during circuit operation.

Furthermore, the metal wiring 18b is ohmically connected to the polycrystalline semiconductor substrate 11 via the diffusion layer 16b.To further explain the diode shown in FIG. Like the element, it must be designed with high voltage resistance.

However, since the current to flow is extremely small, the smallest size may be sufficient.

Next, to explain the effects of the present invention, the wiring that makes the wide signal conductive (that is, the wiring that has the opportunity to reach the highest potential)
Through a diode with high voltage blocking ability,
Since it is connected to the polycrystalline semiconductor substrate 11, the polycrystalline semiconductor substrate 11 is in circuit operation (including during BT testing),
When the bullet is at its highest potential, any first
Depletion does not occur on the surface of the conductive single crystal semiconductor 130 either. Therefore, the operation of one circuit can be stabilized, there is no need to forcibly increase the impurity concentration of the first conductivity type high-concentration buried layer, and high-density integration is made easier. The effect is obvious.

Finally, in view of the gist of the present invention, the first conductivity type single crystal semiconductor 13 need not be limited to N type as in the embodiments, but may also be implemented as P type. In that case, the current direction of the diode shown in Figure 5 must be reversed, and the metal wiring isa is connected to the wiring that has a chance of being at the lowest potential during circuit operation, and the polycrystalline semiconductor substrate is at the lowest potential during circuit operation. will be retained.

[Brief explanation of drawings]

FIG. 1 is a table showing experimental results in which the BT bias direction of the switches of each part on the same pellet corresponds to the direction of occurrence of deterioration. FIG. 2 shows experimental data showing the temperature dependence of breakdown voltage before and after the BT test. FIG. 3 is a cross-sectional view showing the state of a conventional semiconductor integrated circuit during forward and reverse bias during a BT test. FIG. 4 shows N profile separation 8i0. for N+ buried layer. FIG. 3 is an explanatory diagram showing how the film is affected by the drift of mobile ions in the film. FIG. 5 is a sectional view showing an embodiment of the present invention. 11... Polycrystalline semiconductor substrate, 12...
Dielectric isolation thin film, 13...first conductivity type single crystal semiconductor, 14...first conductivity type high concentration buried layer, 15
...Surface insulating film, 16a, 16b...
Second conductivity type diffusion layer, 17...First conductivity type diffusion layer, 18a, i8b...Metal wiring. Rate 1 Figure θ, fQ 1(k) /67) 200 Shyness [・C]

Claims (1)

[Claims] A polycrystalline semiconductor substrate has a plurality of first conductivity type single crystal semiconductor regions electrically insulated and separated by a dielectric thin film on the main surface side thereof, and each circuit component formed in each semiconductor region. 1. A dielectrically isolated semiconductor integrated circuit connected by metal wiring, characterized in that a wiring for conducting a large amplitude signal is connected to the polycrystalline semiconductor substrate via a diode.