JPS6092629A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6092629A JPS6092629A JP58200385A JP20038583A JPS6092629A JP S6092629 A JPS6092629 A JP S6092629A JP 58200385 A JP58200385 A JP 58200385A JP 20038583 A JP20038583 A JP 20038583A JP S6092629 A JPS6092629 A JP S6092629A
- Authority
- JP
- Japan
- Prior art keywords
- case
- semiconductor substrate
- island
- semiconductor
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
本発明は半導体基板のサブ電位とケースのリード端子と
の接続に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a connection between a sub-potential of a semiconductor substrate and a lead terminal of a case.
従来半導体基板のサブ電位ｔケースから取シ出すには半
導体基板底面とケースのアイ２ンドを合金接着し、アイ
ランドをケースのリードと接続して取シ出しているのが
普通である。Conventionally, in order to take out the sub-potential t case of a semiconductor substrate, the bottom surface of the semiconductor substrate and the island of the case are bonded with an alloy, and the island is connected to the lead of the case to take out the island.
しかし最近の半導体装置ではその機能特性とか組立工程
の合理化等から半導体基板をケースのアイランドに接着
固定するのではなく、半導体基板をインナーリードを介
してケースに固定する事も行われている。この場合半導
体基板のサブ電位を取るには基板表面からコンタクトを
介して電位を取っている。However, in recent semiconductor devices, due to their functional characteristics and rationalization of the assembly process, the semiconductor substrate is not fixed to the island of the case by adhesive, but the semiconductor substrate is also fixed to the case via inner leads. In this case, to obtain the sub-potential of the semiconductor substrate, the potential is obtained from the surface of the substrate via a contact.
第１図はインナーリードを介してケースに固定されたカ
ラー剛固体操像装置である。第１図において、ｌは表面
に固体撮像素子を製作した半導体基板、２は絶縁酸化膜
、３は拡散層、４は拡散層に接続されている電極、５は
半導体基板１に接続された電極で本電極から半導体基板
にサブ電位が供給される。６は透明ガラス基板、７はカ
ラーフィルター、８はインナーリードでいずれも透明ガ
ラス基板６上に作成されている。９はバンプで、半導体
基板１を透明ガラス基板６上に作られたインナーリード
８を介してケース１ｏに接続固定している。１１は透明
キャップである。本例では半導体基板１のサブ電位を基
板表面のコンタクトを介して接続している。このような
構造ではコンタクト周辺とコンタクトから離れた部分で
は基板電位に差が生じる欠点がある。それはコンタクト
から遠い部分は基板の抵抗を介して電位が供給される為
である。又サブ電流を流して使用する場合には特にこの
欠点が大きくなシ固体撮像装置の特性にシェーディング
とかプルーミング抑制特性の劣化とか、スワールが発生
しやすい等の画質の低下をきたす。FIG. 1 shows a collar rigid imaging device fixed to a case via an inner lead. In FIG. 1, l is a semiconductor substrate on which a solid-state image sensor is fabricated, 2 is an insulating oxide film, 3 is a diffusion layer, 4 is an electrode connected to the diffusion layer, and 5 is an electrode connected to the semiconductor substrate 1. A sub-potential is supplied from the main electrode to the semiconductor substrate. 6 is a transparent glass substrate, 7 is a color filter, and 8 is an inner lead, all of which are formed on the transparent glass substrate 6. Reference numeral 9 denotes bumps that connect and fix the semiconductor substrate 1 to the case 1o via inner leads 8 made on the transparent glass substrate 6. 11 is a transparent cap. In this example, the sub-potentials of the semiconductor substrate 1 are connected through contacts on the surface of the substrate. Such a structure has the disadvantage that there is a difference in substrate potential between the periphery of the contact and a portion away from the contact. This is because the potential is supplied to the portion far from the contact via the resistance of the substrate. In addition, this drawback is especially serious when a sub-current is applied to the solid-state imaging device, resulting in deterioration of image quality such as shading, deterioration of pluming suppression characteristics, and tendency to generate swirl.
本発明は上記欠点、すなわち半導体基板に不均一なサブ
電位がかかって生ずる不具合を無くした半導体装置を提
供するものでるる。すなわち本発明は半導体基板底面と
ケースのアイランド間を導電性バネで接続し、サブ電位
をしっかシ取るものである。The present invention provides a semiconductor device which eliminates the above-mentioned drawbacks, namely the problems caused by non-uniform sub-potentials being applied to the semiconductor substrate. That is, the present invention connects the bottom surface of the semiconductor substrate and the island of the case with a conductive spring to securely remove the sub-potential.
次に本発明の実施例を第２図によシ説明する。Next, an embodiment of the present invention will be explained with reference to FIG.
第２図の番号は第１図と共通でるる。２１は半導体底面
につけられた金蒸着層で半導体裏面を低抵抗で同一電位
にするものである。２２は導電性アイランドでケースの
リード端子に接続されている。２３はケースのアイラン
ド２２と半導体底面を接続する導電性バネである。導電
性バネ２３を用いることによシアイランド２１と半導体
基板１は金蒸着層２１によシ低抵抗で一様電位に保たれ
る。従って従来のような表面コンタクト法によりて生じ
た半導体基板電位の場所による不均一性が生じない。よ
って次のような長所をもたらす。The numbers in Figure 2 are the same as in Figure 1. Reference numeral 21 is a gold vapor deposited layer applied to the bottom surface of the semiconductor, which makes the back surface of the semiconductor low in resistance and at the same potential. 22 is a conductive island connected to a lead terminal of the case. 23 is a conductive spring that connects the island 22 of the case and the bottom surface of the semiconductor. By using the conductive spring 23, the island 21 and the semiconductor substrate 1 are maintained at a uniform potential with low resistance by the gold vapor deposited layer 21. Therefore, non-uniformity in semiconductor substrate potential due to location, which occurs with the conventional surface contact method, does not occur. Therefore, it brings about the following advantages.
１：シェーディングが無い。1: No shading.
２：プルーミング抑制特性が均一でめる。2: The pluming suppression characteristics are uniform.
３ニスワールが発生しない０ ４：使用電源マージンが拡大する。3 Niswar does not occur 0 4: The power margin used will expand.
次に第３図による他の実施例を示す。第３図の番号は第
１図、第２図と共通である。２４はケースのアイランド
２２と半導体底面を接続するコイル状の導電性バネでお
る。本導電性バネ２４を用いた効果は第２図の実施例で
述べたことと同じでめるＯ
導電性バネ２３．２４はあらかじめケースアイランド２
２に固定されていてもよいし、あるいは半導体基板ｌが
接続された透明基板６をバンプを介してケースに固定す
る時に挿入してもよい。本実施例は固体撮像素子をケー
スに組込んだ例を示したがｄ常の半導体装置の作成に使
用できること言うまでもない。Next, another embodiment according to FIG. 3 will be shown. The numbers in FIG. 3 are the same as in FIGS. 1 and 2. 24 is a coiled conductive spring that connects the island 22 of the case and the bottom surface of the semiconductor. The effect of using this conductive spring 24 is the same as that described in the embodiment shown in FIG.
2, or may be inserted when the transparent substrate 6 to which the semiconductor substrate 1 is connected is fixed to the case via bumps. Although this embodiment shows an example in which a solid-state image pickup device is incorporated into a case, it goes without saying that the present invention can also be used to create a conventional semiconductor device.
第１図は従来の半導体装置の一例の断面図、第２図およ
び第３図は本発明による半導体装置の実施例の断面図で
める。
第１図、第２図、第３図の番号は共通で、１・・・・・
・半導体基板、２・・・・・・絶縁酸化膜、３・・・・
・・拡散層、４．５・・・・・・電極、６・・・・・・
透明基板、７・・・・・・フィルター、８・・・・・・
インナーリード、９・・・・・・バンプ、−１０・・・
・・・ケース、１１・・・・・・透明キャップ、２１・
・・・・・金蒸着層、２２・・・・・・アイランド、２
３．２４・・・・・・導電性バネ。FIG. 1 is a sectional view of an example of a conventional semiconductor device, and FIGS. 2 and 3 are sectional views of an embodiment of a semiconductor device according to the present invention. The numbers in Figures 1, 2, and 3 are common, 1...
・Semiconductor substrate, 2...Insulating oxide film, 3...
...Diffusion layer, 4.5... Electrode, 6...
Transparent substrate, 7...Filter, 8...
Inner lead, 9...Bump, -10...
...Case, 11...Transparent cap, 21.
...Gold vapor deposited layer, 22...Island, 2
3.24... Conductive spring.
Claims (1)
接続した事を特徴とする半導体装置〇A semiconductor device characterized by connecting the bottom surface of the semiconductor substrate and the island of the case with a conductive bag.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200385A JPS6092629A (en) | 1983-10-26 | 1983-10-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200385A JPS6092629A (en) | 1983-10-26 | 1983-10-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6092629A true JPS6092629A (en) | 1985-05-24 |
Family
ID=16423436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58200385A Pending JPS6092629A (en) | 1983-10-26 | 1983-10-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6092629A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9914370B2 (en) | 2013-06-10 | 2018-03-13 | Toyota Boshoku Kabushiki Kaisha | Vehicle seat |
-
1983
- 1983-10-26 JP JP58200385A patent/JPS6092629A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9914370B2 (en) | 2013-06-10 | 2018-03-13 | Toyota Boshoku Kabushiki Kaisha | Vehicle seat |
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