JPS6091781A - Recorder of video signal - Google Patents

Abstract

PURPOSE:To stabilize a carrier frequency of a sound signal subject to frequency modulation by linking a carrier frequency of a pilot signal, a chrominance signal and the sound signal to frequency fH of a horizontal synchronizing signal. CONSTITUTION:The horizontal synchronizing signal of frequency fH obtained from a horizontal synchronising signal separator circuit 15 is fed to a VCO 18 so as to form a signal of, e.g. 1024 fH. Then the signal 1024 fH is frequency- divided by a circuit 41 and a pilot signal P is formed. Moreover, a signal of 64 fH obtained by frequency-dividing the output 1024 fH of the VCO 18 is added (29) with the sound input signal via a phase comparator 28 and fed to a VCO 30. The phase comparator 28, the adder 29 and the VCO 30 form a phase locked loop. The frequency of the pilot signal P, the chrominance signal C and the sound signal AFM is close to each other, but since the frequency is linked entirely to the fH and set accurately, the interference is minimized.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an apparatus for recording a video signal on a recording medium), and in particular to recording a pilot signal for tracking control and a frequency-modulated audio signal onto a video signal by frequency multiplexing. The present invention relates to a device suitable for

[Background of the invention] Conventional equipment that frequency-multiplexes frequency-modulated audio signals onto video signals and records them requires a dedicated reference oscillator and frequency dividing circuit in order to stabilize the carrier frequency of the audio signal. , which led to an increase in circuit costs.

[Purpose of the invention]

The object of the present invention is to provide a video recording device capable of stabilizing the carrier frequency of a frequency-modulated audio signal without using a reference oscillator or a frequency dividing circuit without using the above-described conventional technology. It's about doing.

[Summary of the invention]

In the present invention, the clock generator Ln for time @1 compression, which transmits at a frequency multiple of the horizontal synchronization frequency, divides the output signal of the carrier generator for low frequency conversion of the color signal, and the frequency of this frequency dividing circuit is A phase-locked loop is formed to match the output signal frequency and the audio signal carrier frequency.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 11.

Figures 1 to 9 show an embodiment of a cross-azimuth two-head helical scan video tape recorder in which the present invention is used to record color signals and luminance signals in a video signal by time division multiplexing. be.

FIG. 1 is a block diagram showing an embodiment of the main part of the recording circuit of the present invention, FIG. 2 is a block diagram showing an embodiment of the video signal generation circuit 1, and FIG. 3 is a block diagram showing an embodiment of the recording circuit of the present invention. Figure 4 is a diagram showing an example of the spectrum of a recorded signal recorded by the circuit shown in Figure 1. Figure 5 is an example of the input/output characteristics of an NR (No-Lingar) circuit. , FIG. 6, and FIG. 7 are diagrams showing examples of waveform diagrams of each part in FIG. 1.

In FIG. 1, numeral 1 denotes a video signal generation circuit, which generates the Y, U, and V signals shown in FIGS. 6 and 7. 2,3.4
8 is an AD converter that converts an analog signal into a digital signal, a time compression circuit consisting of 5, 6.7 u RAM and a shift register h, and 8 is a digital circuit of approximately 1H (1 horizontal period) consisting of a RAM and a shift register, etc. delay circuit,
9 is a digital signal generation circuit corresponding to the reference level of the achromatic signal (approximately 501RE), 10 is a DA converter that returns the digital signal to an analog signal 1), and its output is get the signal.

11 is a pre-emphasis circuit, 12 is a clip circuit, 1
3 is a frequency modulation circuit, 14 is an HPF, and a fifth signal having a VFH spectrum shown in 1 is obtained at its output. VFM has a synchronous peak frequency of t? MHz.

White peak frequency 5. aMEz, the lower limit of the lower sideband is approximately 1M
It is limited to Hz. In order to maintain the above frequency, the conventional circuit includes an AGC circuit that controls the signal amplitude to a constant value on the input side of the emphasis circuit 110, and a Franz circuit that fixes the DC potential of the synchronous tip to a constant value.

I needed a circuit. In Figure 1, by making an open DC coupling between the DA controller 10 and the emphasis circuit,
It is possible to completely eliminate the GC circuit and clamp circuit.

Reference numeral 15 denotes a horizontal synchronization separation circuit, and outputs a horizontal synchronization signal having a frequency of fx. 16 is a phase comparator, 17
is a frequency divider of i, 1B is a VCo that oscillates at 1024f1
, 19, 20, 21, and 22 are one-frequency dividers and form a phase-locked loop.

23 is a 1 frequency divider for stabilizing the audio carrier frequency and outputs a frequency of -fH. 24 is a phase comparator, 2
5 is an adder, 26 is a VCO, and 24, 25, and 26 also form a phase-locked loop.

27 is a BPF for suppressing unnecessary signals. 28 is a phase comparator, 29 is an adder, 30 is a VCO%2B, 29°3
0 to form a 7-a-slot loop. 31 is a BPF for suppressing unnecessary signals.

Reference numerals 32 and 33 are two-channel audio signal input terminals, into which signals for %A1 and %A1 are input. 35 is an AGC circuit to which the (AI-'t) signal is input, and the signal is sent to the adder circuit 25 via a pre-emphasis circuit 36 and an NR circuit 37. An example of the characteristics of the NR circuit is shown in FIG. 38 is AG
This is a C circuit, and the ('+ 1,0004) signal is inputted, passes through the pre-emphasis circuit 39 and the NR circuit, and then reaches the adder circuit 29. Therefore, the output of VCO26 has a center frequency '
Frequency modulated waves with a center frequency of 6Afx are obtained at the output of the VCO 50, respectively.

The reason for choosing carrier k'ifx for the difference signal and t6Afrt for the sum signal of stereo audio signals is that the higher the carrier frequency, the less crosstalk interference from adjacent trunks due to azimuth loss. The signal carrier was 64fn. Therefore, in the case of main sound and sub-sound in two languages, rather than stereo sound, it is necessary to select a higher carrier on the main-sound side.

When selecting the audio carrier frequency, it is necessary to take into account flyback pulse interference, which is a problem when playing a video tape recorder placed on top of a television receiver.Make it less susceptible to flyback pulse interference. It is sufficient to have an off-seratra with respect to the frequency (7y) of the flyback pulse.It is desirable that both carriers have an offset, and it is desirable that at least the carrier with the lower stutter also has an offset.

When the luminance signal is time-compressed every other horizontal period as shown in FIG. 1, the tW given by the audio carrier to the video signal does not depend on the carrier frequency. For this reason, it is desirable that the audio carrier frequency be an integral multiple of fg because the generation circuit is simple. Therefore, the upper carrier frequency is an integer multiple of frt, and the lower carrier frequency has an off-seratra ft'
It is better to do so.

41 consists of a frequency divider circuit with four different frequency division ratios 024 Get 4 carriers of Za Knee Stone fH.

42 is a mixing circuit, 43 is a recording amplifier, 44 is a 2-channel rotary transformer, and A5 is a 10° azimuth hero.
46 is a video tape.

In FIG. 2, numeral 47 is an input terminal for a conhogit video signal, 4th is an AGC circuit that controls the output signal so that the output signal does not exceed a certain value, 49 is a 1B delay circuit, 50 is a subtraction circuit, 51 is an adder circuit, 49.50 constitutes a C-shaped comb filter, and 49 and 51 constitute a Y-shaped comb filter. 52 is an LPF, 53 is an adder circuit, and 54 is a Y signal output terminal which removes the color subcarrier f' and outputs the entire luminance signal. 55 is a BPF, 56 is an AGC circuit that makes the amplitude of the burst signal constant, and 57 is two color difference signals B-Y and R-YX from the carrier color signal. i-Decoder for demodulating, 5
8.59 is an output terminal for color difference signals U and V.

The characteristics of the combination of Figures 1 and 2 are filAGC.
Circuit dB, 56 is provided on the input side of AD converter 2, 3.4, +21 < L-type filter 719.50
51 is provided on the input side of the AI) converter.

(The advantage of 11 is that it only requires two AGC circuits)
The dynamic range utilization of the converters 21 31 4 and the DA converter 10 can be optimized, and the frequency shift of the frequency modulation circuit 13 can be controlled.

Advantages of (2) 11. The generation of false signals due to line sequentialization of the high-frequency components of the luminance signal and the color difference signal can be suppressed by one 1B delay circuit 49.

Since the color sub-carrying amount input to the ifr-AD converter 4 is sufficiently suppressed, the generation of return signals is also suppressed.

In FIG. 4, 60 is the first diagonal track recorded on the videotape 46;
Four signals, FM and P, are recorded. As mentioned above, the pilot signal P is fI r fM Hfs, f for each track.
&, fI, . . . are signals having four different frequencies, and these are recorded cyclically. 1 on one diagonal track
Usually, the video signal for the field is recorded.

61 is a second diagonal track on which information other than the video signal is recorded as necessary.

In Figure 5 f;? lx, 62 indicates the input/output characteristics of the NR circuit.

In FIG. 6, Y, U, and V indicate three output signal waveforms of the video signal generation circuit 1. A is a diagram showing the operating state of the digital delay circuit 8, and both the write clock and the read clock are '02Afy. Write every 1B,
By repeating readout, the signal every 1H, Yn −
2, Y n, Yn+2.

...is delayed by 1B.

B is a diagram showing the operating state of the 7-hour compression circuit 7, in which the write clock is 5121. , the read clock is 1024
I was selected for 1H. 177b signal Yn-5, Yn
-1, Ya+1. ``'' is compressed in time to 7.

cVi is a diagram showing the operating state of the time compression circuit 5, where the write clock is 256fH and the read clock is 10'.
I was selected by 1AfH. IHb signal s un-1
, Un+1. Time is compressed to Un+s, -k 7.

D is a diagram showing the operating state of the 7-hour compression circuit 6, where the write clock is 256fH1 and the read clock is 1o24.
Selected by fti. 1R oyster signal, 'n-1,
'n+1. 'n+5. ``' k , time is compressed.

S indicates the waveform of the output signal of the DA converter 10.

63 is a time-compressed horizontal synchronization signal, 64 is a time-compressed horizontal synchronization signal, 65 is a chroma zero level corresponding to a color difference signal of zero, 66 is a video signal that is not time-compressed, and 67 is a time-compressed horizontal synchronization signal. Compressed (B-Y) signal, 68
iL is the near time compressed (RY) signal, and 69 is the i near time compressed 'fc luminance signal.

Depending on the difference in the horizontal synchronization signal during playback, it is possible to determine whether the signal is time-compressed.

In FIG. 7, Y, U, and V indicate three output signal waveforms of the video signal generation circuit 1.

A' is a diagram showing the operating state of the 7-hour compression circuit 7. 7
Figure %(:/
, 0/ are diagrams showing the operating states of the i time compression circuit 5.6, respectively.

S' indicates the waveform of the output signal of DA converter 0.

Horizontal synchronization signal 6 time-compressed compared to S in FIG.
3 is not available, but the chroma zero level is 70, and the switching margin is 71.
The difference is that 72 is newly inserted.

FIG. 8 is a block diagram showing another embodiment of the main parts of the recording circuit of the present invention, and FIG. 9 is a diagram showing an example of a waveform diagram of each part of FIG. 8.

The differences between FIG. 8 and FIG. 1 will be explained below. 1st
In the figure, two AD converters are used for U and V, but in Figure 8, only one AD converter is required by providing a switch 73t''.
In order to make the horizontal synchronizing signal waveform applied to the output waveform (S" in FIG. 9) uniform for every line, the horizontal synchronizing addition circuit 74'5c
It is inserted into f# 几. Therefore, the differences between FIG. 9 and FIG. 2 are the horizontal synchronization pulse width at S", the pulse width of the back porch 75, the pulse width of the chroma zero level, and the operating state of the one-time compression circuit 7 B". 7 hour compression circuit 5.6
The operating states Ctt and gt are the only ones.

In the recording method shown in FIG. 8, it is possible to determine whether the signal is a time-compressed signal or not by detecting the pulse width of the back porch during reproduction.

Figures 10 and 11 show a cross-azimuth two-head helical scan type video tape recorder in which the chrominance signal in the video signal is converted to low frequency and the luminance signal is converted into a frequency modulated wave and recorded by full frequency multiplexing. This is an example in which the present invention is used.

FIG. 10 is a block diagram showing an embodiment of the recording circuit of the present invention, and FIG. 11 is a diagram showing an example of the spectrum of a signal recorded by the circuit of FIG. 10.

In Figure 10, 11-14.30-48.55-5
6 is the same as in FIGS. 1 and 2. 76 is a clamp circuit that fixes the synchronizing tip of the LPF 77 for luminance signal extraction to a constant potential. 82 is a phase comparator, 83 is a fraction frequency divider, 8
4 is a 378 fH VCO and constitutes a PLL circuit.

85 is a percent frequency divider, 86 is a color subcarrier frequency crystal oscillator, 87 is a frequency converter, 79 is a BPF for extracting the sum frequency signal, 80 is a 78 frequency converter, %81 is low frequency converted to -a fy This is an LPF for color signal sampling. Reference numeral 41 denotes a pilot signal generation circuit, which outputs a signal of ft=ht, h=100 fH+field fs=takufir=−fH. 7836
40 is a -frequency divider and outputs the carrier of s fi. Therefore, the center frequency of vcoso is a fx.

As shown in Fig. 11, the pilot signal e) and the color signal (
C) and the audio signal CApht) have frequencies close to each other, so mutual interference tends to be a problem, but in this case (7) all frequencies are linked to fy and set accurately, so interference can be minimized. I can do it.

〔Effect of the invention〕

According to the present invention, the carrier frequency of the audio signal and the frequency of the pilot signal can be stabilized without providing a dedicated reference oscillator or frequency dividing circuit.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the recording circuit of the present invention, Fig. 2 is a block diagram showing an embodiment of the video signal generation circuit used in the invention, and Fig. 3 is a block diagram showing an embodiment of the recording circuit of the present invention. FIG. 4 is a diagram showing an example of the spectrum of a signal recorded by the recording circuit shown in FIG. 1, FIG. 4 is a diagram showing an example of a table turn recorded by the recording circuit shown in FIG. FIG. 6 and FIG. 7 are diagrams showing waveforms of each part of FIG. 1, and FIG. 8 is a diagram showing another embodiment of the recording circuit of the present invention. Block diagram, FIG. 9 is a diagram showing waveforms of each part of FIG. 8, FIG. 10 is a block diagram showing another embodiment of the recording circuit of the present invention, and FIG. FIG. 2 is a diagram showing an example of a spectrum of a signal. 1... Video signal generation circuit 2, 3. A...Al) Converter 5, 6.7... Time compressor 18.84... NfH VCO 19, 20, 21, 22, 23... Brancher 41...
・Pilot signal generation circuit

Claims (1)

[Claims] t In a device that records a video signal as a frequency modulated wave and an audio signal as a frequency modulated wave together with a tracking pilot signal on a recording medium by frequency multiplexing, the frequency is N times (N integer) the horizontal synchronization signal of the video signal. a signal generation circuit; a circuit that frequency-divides the output signal of the signal generation circuit to generate the pilot signal; Recording of a video signal, characterized by comprising a carrier generation circuit that generates a frequency higher than that of a pilot signal, and a circuit that makes the output signal of the carrier generation circuit substantially match the center frequency of the frequency modulated wave of the audio signal. Device.