JPS6091767A - Video signal generator - Google Patents

Abstract

PURPOSE:To eliminate the need for a frame memory of large capacity and a high speed code converter by constituting an MH code of a code to be decoded in real time. CONSTITUTION:One page's share of MH coded data such as document or picture stored in a file storage device 1 is reproduced and stored in a read buffer 2 comprising an RAM. After a register 3 is reset in order to read one word of MH codes from a series of MH code strings in which the boundary is not clear, logical 1 is set to the left end bit only and MH code word data for one page's share stored in the buffer 2 are read one by one bit until a code word end signal is generated in a code word end detection circuit 12. One word of the read MH code is fed to an ROM4 as an address signal. Since a decoded data is stored in the ROM4, when the address signal is a complete MH code, the length of the white or black picture line to be decoded is obtained in a binary number.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention receives a supply of binary image information obtained by compressing a document, image, etc. using a -dimensional run-length code word similar to a facsimile, and processes the compressed binary image information. The present invention relates to a video signal generation device that decodes image information, converts it into a binary image signal suitable for constant speed scanning, and supplies the signal to a constant speed scanning display device such as a CRT or printer.

PRIOR ART AND PROBLEMS As shown in FIG.
) The I code is read out and stored in the buffer 2, and the low-speed decoding circuit 15 restores it to a screen signal while continuing to store it in the frame memory 6. After the storage for 2 minutes is completed, the bus switching circuit 7 A frame memory 6 is connected to a parallel-to-serial conversion register 8, and a video signal is obtained by sequentially reading screen signals from the frame memory 6 in synchronization with the scanning speed of the CRT. Therefore, from optical disk 1 to 1
It takes 2 to 5 seconds after reproducing one page of screen information until a desired document or the like is reproduced on a CRT screen or the like. For this reason, it is impossible to read diagonally or read a large number of pages in a short period of time, and it is extremely inconvenient to search for documents.

On the other hand, considering the way paper files are used on a daily basis, the location of the desired document is generally vaguely memorized or completely unknown, so it is difficult to access the file. "Diagonal reading" and "
Disaggregation <9'' is essential, and it is extremely inconvenient that these are not possible, especially in OA file devices.

Also, CR screen of 1728 dots x 2304 lines
For example, when displaying on T, approximately 4M per screen
Not only does it require a bit frame memory, but it also requires a high-speed parallel-to-serial converter register 8 to match the CRT scanning speed and memory operating speed, resulting in an expensive and large device. Ta.

Furthermore, in another conventional example (not shown), two sets of 1728-bit line memories are prepared in place of the frame memory 6, and one of them is used for decoding while the other is used as a fresh memory for display. There is a way. However, this method requires an extremely high-speed operation during the refresh operation, so it requires a parallel-to-serial conversion circuit for speed conversion in addition to a normal memory element, which still has the disadvantage of making the device expensive. there were.

These problems arise because the conventional decoding method of MH code is derived from facsimile transmission.
/ line, but when generating video signals to be displayed on a rusk scan type CRT, the scanning speed of the electron beam is extremely high (20 to 7
This is due to the fact that real-time decoding is difficult because it is 0 μS/line).

Purpose of the Invention The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a small, inexpensive, and high-speed video signal generating device by eliminating expensive frame memories and the like. be.

Structure of the Invention The present invention achieves the above object by storing the run length and codeword group classification attributes of each codeword in each storage area having as an address a codeword with "1#" added to the beginning of each codeword to be decoded. and storage means for storing decoded data consisting of a white signal/black signal distinction, and storing data that does not correspond to any of the decoded data in each of the remaining storage areas;
At the time when the supply of the compressed binary image information is started and when the decoding of each code word is finished, 1" is added to the beginning of the newly supplied code string and N bits are added from the new beginning. an address means for serial/parallel converting and addressing the storage device using the parallel-converted code string, detecting that decoded data is output from the storage means, and decoding the valley code word to the address means means for notifying the point in time when the decoded data outputted from the storage means is buffered while preventing underflow; and means for initializing the decoded data outputted from the first-in first-out storage means; A counting means for decrementing the count by a pulse train having a speed corresponding to the code group classification attribute included in the decoded data, and a white signal// The image forming apparatus is configured to include an output means for outputting a binary image signal suitable for uniform speed scanning according to the distinction of black signals.

Further details of the present invention will be explained below using Examples.

In the description of this embodiment, an EIA-BFICC type MH code (MH white code exclusively for A4 size) will be used as an example of the -dimensional run-length code.

Furthermore, a code string means a part of a code word or a state in which the code word is incomplete due to concatenation.

Embodiment of the Invention FIG. 2 shows an embodiment of the present invention, in which 1 is a file storage device, 2 is an MM code reading buffer memory for one page, 3 is a 14-stage serial input parallel output shift register, 4 is a ROM (read-only memory) having addresses from address 0 to address 8311, 5 is a code read control circuit, 12 is a code word end detection circuit, 13 is a FIFO memory control circuit, 25 is a FIFO memory, and 26 is an output data word. Registers 27 and 28 are the first . a second counter,
29 is a frequency divider, 30 is an all-it-ill decoder, 3
1 is a clock switching gate, 32 is a CRT deflection circuit,
9 is a video signal holding circuit, IO is a video amplifier, 11 is CR
It is T.

Decoded data is configured and recorded in advance in the ROM 4 according to the procedure shown below. First, 1" is added to the beginning of all 91 black MH codewords, and the codeword after the addition is called a modified MH word. For example, "black run 11" is modified because it is "0000101 '''. 1000 MH words
0101''.Next, run length data corresponding to the regular MH code word is configured as shown in Figure 3 in the memory area on the ROM that has the same address as each of the 91 modified MH words generated in this way. In other words, the straight line length O to B to be decoded is represented by bits O to B. Bit 6 is used to distinguish termination codes/make-up codes (generally code word group classification attributes), and white is used to represent the straight line length O to B. / In addition to allocating bit 7 to black, bit 8 is allocated to indicate that it is decoded data, and the decoded data is configured and stored.Similarly, 91 white MH code words After adding 1'', the decoded data corresponding to the corresponding address is stored.

However, only addresses 132 and 260 already contain corresponding decoded data for black codes, so the decoded data for white codes (white run n and white run 45) are discarded. The EOL (end of line) code "00000000001" is also converted into two types, white and black. Also, if the binary representation of the address does not correspond to any of the modified MH words, a specific code such as "all 0" is converted. Therefore, out of the memory area from addresses 0 to 8311, the decoded data is stored in discrete 182
The remaining 8129 addresses are all "'0"s.

To operate this, first, the file storage device 1 is operated using a known method, and the M)I of documents, images, etc., which are quantized and recorded in 1728 dots) x 2304 lines, is stored using a known method not shown. One stage of encoded data is reproduced and stored in a read buffer 2 constituted by a RAM. In this example, one A4 size page is
Since sampling is done with 728 dots x 2304 lines, the amount of raw data during quantization is approximately 4 Mbtt (megabits), but as is well known, by using the MH white code, the amount of raw data is approximately 4 Mbtt (megabits) compared to a direct sample of the original. 1/io
The size of buffer 2 is approximately 400.
kbit (*O bit) is fine. Note that the above numerical values are merely examples, and even if other values are adopted, the effects of the present invention will not be impaired in any way.

Next, a series of M with unknown boundaries stored in buffer 2
One MH code word is cut out from the H code string as follows, and the corresponding linear length binary representation data is obtained.

Mass, register 3 has 1# only in the leftmost bit after reset.
Set it. Next, one page of MH code word data stored in the buffer 2 is transferred to a code word end detection circuit 1 which will be described later.
The data is read out one bit at a time until a code word end signal is generated at 2, and the bits are added from the left side of the shift register 3 while moving rightward on the shift register 3. As the signal progresses, it appears momentarily at the parallel output terminals of this shift register. Mu code 1
``1'' / ``0'' data string that is part or all of the word is R
It is supplied one by one to the address terminal group of OM4. At this time, R
Since the decoded data mentioned earlier is recorded as the contents of OM4, if the original data supplied to the address terminal group is a complete MH code, the ROM data terminal group will contain the white or black image to be decoded. The length of the line is 2 from bit 0 to bit 5.
It is obtained in decimal representation, and indicates whether the original data is a termination code or a make-up code, and bit 7 indicates whether the original data is a termination code or a make-up code, and bit 7 indicates whether it is white or black.It indicates that the supplied original data is a Mu code. A "1" is obtained on bit 8 at the same time.

This bit 8-11'' drives the code word end detection circuit 12 to generate the end signal.If the original data is a complete M
If it is not an H code word but is part of a word, bit 8 will contain “
0” appears. Note that the distinction between white/black and termination/make-up in the next decoding can be determined based on the latest decoding result, but this is not used in this embodiment and is therefore not shown.

Therefore, immediately after bit 8 of the ROM output becomes "1", the decoded data is transferred to the FIFO memory 25, and the serial/parallel conversion register 3 is reset.
00000000000'' and starts decoding the next MH code word in response to a trigger signal from the FIFO memory control circuit 13.

By the way, if part of the long MH code word is stored in register 3, the data word corresponding to the short MW code word is stored in the ROM.
There is also a concern that the data may be output incorrectly.

For example, the code word for black run 5 is @0011" and that for sb black run 2 is 611", so the code word for ROM address line is "@0011".
0000000000011'' is applied only.
It is not possible to distinguish whether length 5 or length 2 should be output. However, since the modified MH word that is used only during decoding has 1# added to the beginning, shifting the data to the right for each 1-bit reading will ensure that the address coordinates of the ROM go up one digit at a time. It corresponds to that. In the previous example, they can be distinguished by setting them to 1X10011'' and 'X111''. Address at that time (lattice point coordinates)
Also, by removing the added @1'', there is a one-to-one correspondence with each branch point of the MH code branching diagram (not shown). Therefore, in the present invention, when a long code is interpreted, a short There is no mistake in the code (the uniqueness of the MH code is preserved. Furthermore, if there is no '1#' at the beginning,
Even if the MH code advances one bit at a time, 'ooooxxx
Because codes such as `` do not advance beyond the digit, there are some codes that cannot be decoded.

In this way, boundaries between words can be found from a MH code word string with unknown boundaries, and corresponding binary data can be obtained. Note that the code word end detection signal is used not only for resetting the shift register but also as a trigger signal for incrementing data in the FIFO memory and starting output from the read buffer memory.

By the way, MI (codes can be roughly divided into make-up codes and termination codes, so bit 6 is used as the code group classification attribute, and the binary representation data of the stroke length obtained as above is expressed as follows. is converted into the image length, that is, the length of time that the image signal is white or black.

To illustrate from the time conversion of the termination code, bit 1
The decoded line length information stored in ~6 is the line length 0.
to 63, i.e. rXXOOOOOOOOJ to rXX
It is expressed as OllllllJ. Note that X displays black or white. Since such a binary representation is received in the output register 26 via the FIFO memory, this binary data is first preset in the first counter 27. Immediately after this, the subtraction of the pixel repetition frequency clock supplied via the line 31 is started, and when the first borrow appears on the line 33, it is known that the line has ended. Therefore, at the same time as the first counter γ starts counting, the information indicating white or black stored in bit 7 of the register 26 is stored in the holding circuit 9, and this is applied as a video signal voltage to a CRT etc. A desired line can be displayed by stopping the application of voltage at the same time as the occurrence of . The next continuous drawing line is displayed by the first counter n.
During the counting operation, the next stroke length data is preset in the second counter, and the second counter starts counting at the same time as the first counter fills out to display the next one stroke. do. Thereafter, the second counter 27 activates the first counter 27 via the line A, and this chain of alternating operations continues until the video signal of 1728 dots per line is completed.

In the makeup code, the stroke length is 64.128.192
°...~1728 is an integer multiple of 64, so set the drawing length to 1.
2.3°...~27. In other words, rXXOOOOOOIJ is expressed as rXXOllollJ, and bit 6 indicating that it is a makeup code and bit 8 indicating that it is an MH code are set to 1, and in the end, rlXloooo
The data words are configured and stored as "lX1011011J" from olJ. Therefore, in order to convert the make-up code to time, the gate switch 31 is first set to count the clock that has passed through the 1/64 frequency divider 4. The make-up/termination display pit 6 is used for control.As a result, the time required for the first and second counters n and 28 to generate a poll can be increased to 64 times the desired value, and decoding can be performed in the same way as the termination code. That means it's done.

Further, in the MH code, there are code words whose object length is longer than the υ code length. Therefore, in the ordinary real-time decoding method, by the time decoding is completed, the CRT beam or the like has already scanned several pixels, and it is predicted that there will be no time for the decoding. Further, the time required for decoding also varies depending on the length of the MH codeword, which is 2 to 13.

FIF was installed to absorb this decoding speed fluctuation.
By decoding and storing tens to hundreds of words in advance in the O memory 25, decoding delays can be eliminated. In the worst case where white and black dots appear alternately over one line, this amount of advance is necessary for 1728 data words, but in general, it is determined based on the statistical properties of the document.
, about 170 watts is sufficient.

When the FIFO memory capacity is insufficient, or when the white run 45 occurs as described above, a CRT or the like will display an incorrect screen on the screen, but the area is small and there is no problem in practical use.

This FIFO memory must perform so-called "first-in, first-out control" in which data words are sequentially input from the left and data words are sequentially output from the right. As a general method for realizing this, program control using a microprocessor is the easiest, but the speed is slow and cannot keep up with the beam scanning speed of CRT and the like. Therefore, one of the known means for realizing this function with a hard logic circuit is the configuration shown in FIG. 21 is a delay circuit, 21 is an OR circuit, 22 is an RS flip-flop, another is an 8-bit parallel input parallel output register, 3 is a borrow output line of the first counter, and 34 is a borrow output line of the second counter.

Because of this connection, when rlJ newly appears on bit 8 of the data output line 14 of the ROM, the differential circuit generates a very thin positive pulse on the line 15, which causes the illusion to occur for a very short time. After a delay of
The first RS flip-flop 22 is set. After setting the first RS flip-flop 22, its output Q also drives the second register 21 and the second RS flip-flop 22. From here on, the chain of operations continues like a chess game, and the data word is sent to the th (th) in the past.
New decoded data is delivered to the 11th register immediately before the register 24 (not shown), that is, the 11th register. This operation is repeated until the register group is full, and when the register group is full, the line 16 reports that it is full to the read control circuit 5, and the chain of operations for storing read decoded data is temporarily stopped.

A read operation from the right is performed as follows.

When the first or second counter generates a borrow, a pulse is generated on the line 39, and the next data word is output to the eighth register 26 at the final stage, and the RS flip-flop of the N-1th register is output. is reset. As a result of this reset, the data word of the N-2 register is loaded into the N-1 register. The same chain of operations continues thereafter.

To explain the above "first in, first out" operation in the context of decoding a normal document, the "first out" operation is stopped while a long white or black run is displayed, so the "right alignment" operation is in progress. and fills the register group with decoded data almost to full. Next, when the short black and white display begins to repeat, the decoded data of the register group is read out one after another in a "first out" manner and is shifted to the right, so that the contents of the register group approach empty. but,
Eventually, another long white or black run will appear, allowing the registers to be filled with decoded data during this display period.

In this way, the run length data to be displayed next is always prepared in the output decoding data register 26, so the first counter and the second counter alternately operate to continuously display the line signals one after another without interruption. occurs, and the decoder 30
H code BOL (End of Linejoooo
ooooooolJ) The display of the first line is ended upon finding the decoded data corresponding to the code, for example ti'rXllllllllJ, and all counters are reset. Thereafter, upon arrival of the horizontal deflection start pulse supplied from the deflection drive circuit 32 such as a CRT, the output buffer 2
The chain of operations of counters 6 to 27 and 28 is started, and the operation of the next second line begins.

The second and subsequent lines are displayed in the same manner, and the display of one screen ends when the display of the 2304th line ends.

As is well known, in a rask scan type CRT display device, the screen needs to be scanned 20 to 30 times per second.
triggers the display of the same page or the next page, and the operation from read buffer 2 to counters 27 and 28 continues without interruption.

To display a new document, etc., input M to read buffer 2.
After saving one page of new W-encoded information, the above operation is started.

In the above embodiment, since there is only one ROM, a word in which the white MH code word and the black MH code word are exactly the same cannot be used for decoding. White run 23 mentioned earlier
and black run 10, white run 45, and black run 13. C
Although there is no practical problem with soft copies such as RT, there are cases where printing devices and the like may not allow this. This can be easily solved as follows.

That is, this is a method in which ROMs for white code decoding and black code decoding are separated, and the ROMs are switched based on the black and white idea of the next MH code, which has been determined from the latest decoding results. At this time, the white code decoded data is stored in the ROM to be added. What happens is that the modified M1 word of the black code is 6 to 831.
While the distribution is at address 1, that of the white code is 23 to 73.
This is because the data is distributed only at one address, which has the advantage of requiring only a small capacity ROM.

Another solution is to store, for example, only the black decoded data in the MH code word address where white and black are the same, and based on the above-mentioned black and white idea, if it matches the prediction, the decoded data is directly transferred to the register group. Output to. Only when the prediction does not match (white runs 23 and 45), normal white code decoded data is output from a separately prepared register. in this way,
There is no need to add ROM, and only two registers need to be added.

The latter method has the advantage that the increase in cost can be ignored when the register group is constructed using a large-scale integrated circuit.

Additionally, a circuit (an all 'o'' decoder in the above embodiment) is added to the output side of the ROM 4 to detect that the output does not correspond to any of the 8-pit decoded data, and this detection result is negative. If the decoding of the valley code word is considered to be completed when the target is reached, the pit 8 can be omitted.

In addition, an example was shown in which a code word is read from the file storage device 1, it is temporarily stored in the buffer memory 2 for one page, and the code word for one page is repeatedly supplied to the serial and parallel output shift register. If the device is a printer instead of a CRT, the buffer memory 2 is omitted and the code words for one page are read out only once from the file storage device 1 and directly supplied to the serial and parallel output shift registers 3. You can also do that. Further, when the code word is supplied from a transmission path, the code word may be supplied to the serial input parallel output shift register 3 via a small capacity buffer memory.

Although the EIA-BFICC type MH code is illustrated as an example of a one-dimensional run-length code, other code words such as a WYLE code or an extended MH code word can also be applied.

Further, although a configuration using two counters 34 has been illustrated, if the display device is a low-speed device such as a printer, a configuration using only one counter may be used.

As described in detail, the video signal generating device of the present invention can decode the MH code in real time, so the CRT-j1% display device to which the present invention is applied is capable of decoding a large-capacity video signal as in the conventional example. No frame memory or high-speed speed conversion circuit is required,
The number of pages of documents, etc. that can be displayed per second is not only possible with small and low-cost CRT display devices, but also
It is possible to increase the vertical deflection frequency up to T. That is, about 20 to 30 documents can be displayed per second. This speed is
The daily page turning motion of humans is about 2 to 6 times/second, the speed of opening a dictionary is 10 to 20 pages/second, and the speed of movies and television is 20 frames/second or more. Considering this, it can be said that this is a practical speed that is sufficient for detecting information with the naked eye, not for the purpose of reading text, but for the purpose of searching.

Additionally, as the amount of information accumulated generally increases, it is often difficult to find a desired page of a desired document using only keywords or the like. In such a case, if the
I have experienced on a daily basis that ``ru'' and ``diagonal reading'' are extremely effective. In other words, since humans have a high ability to identify visual information such as page layouts and photos, the CRT display device to which the present invention is applied is extremely effective when searching for documents that have been viewed once. Demonstrate.

Furthermore, the present invention exhibits its advantages extremely effectively even when it is desired to make a so-called note copy of a portion of a large amount of documents and images stored in a file storage device. That is, since the time required to decode one page is approximately 30 ms, the advantage is that by combining this with known electrophotographic technology, it is possible to print approximately 30 pages per second.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional document/image video signal generation device, FIG. 2 is a schematic block diagram of an embodiment of the device of the present invention, FIG. 3 is a format diagram of an example of decoded data, and FIG. FIG. 1 is a configuration diagram of a portion of an embodiment of the present invention. 17=7 keyaki control circuit, 6... frame memory, 7...
・No(switching circuit), 8... Parallel-serial conversion register, 9... Video signal holding circuit, 10... Video amplifier,
11...CRT.

Claims (1)

[Claims] After receiving compressed binary image information using a one-dimensional run-length code word and decoding the compressed binary image information, In a video signal generation device that converts the encoded image signal into a constant speed scanning display device, the encoded image signal is stored in 6 storage areas each having a code word with “1” added to the beginning of each code word to be decoded as an address. Stores decoded data consisting of word length, code word group classification attribute, and white signal/black signal distinction, and stores data that does not correspond to any of the decoded data in each of the remaining storage areas. a storage means, at the time when the supply of the compressed binary image information is started and when the decoding of each code word is finished, adding 11'' to the beginning of the newly supplied code string to create a new beginning; Addressing means serial/parallel converting N bits from , and addressing the storage device with the parallel-converted code string; detecting that decoded data is output from the storage means, and causing the addressing means to decode each code word. means for notifying the point in time when the decoded data output from the first-in first-out storage means is buffered while preventing under-70- from each decoded data output from the storage means; after initializing the decoded data output from the first-in first-out storage means; A counting means for decrementing the count by a pulse train having a speed according to the classification of the code word group classification attribute included in the decoded data, and a counting means for decrementing the count by a pulse train having a speed corresponding to the classification of the code word group classification attribute included in the decoded data, and counting the decoded data from the initial setting of the cough counting means until the decrement result becomes 0. 1. A video signal generation device comprising an output means for outputting a binary image signal suitable for constant speed scanning according to a distinction between a white signal and a black signal included in the video signal.