JPS609166A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS609166A
JPS609166A JP11583183A JP11583183A JPS609166A JP S609166 A JPS609166 A JP S609166A JP 11583183 A JP11583183 A JP 11583183A JP 11583183 A JP11583183 A JP 11583183A JP S609166 A JPS609166 A JP S609166A
Authority
JP
Japan
Prior art keywords
oxide film
electrode
gate oxide
thickness
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11583183A
Other languages
Japanese (ja)
Inventor
Hideo Sunami
英夫 角南
Seiichi Iwata
誠一 岩田
Naoki Yamamoto
直樹 山本
Nobuyoshi Kobayashi
伸好 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11583183A priority Critical patent/JPS609166A/en
Publication of JPS609166A publication Critical patent/JPS609166A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To recover defective insulation by thickening a gate oxide film after forming a gate electrode, and to improve yield by thermally treating the whole in an H2 carrier gas containing H2O of 10ppm-10% within a temperature range of 500-1,200 deg.C. CONSTITUTION:A partially thick field oxide film 2 is formed on an Si substrate 1 through a well known LOCOS method. A gate oxide film 3 in 5-100nm thickness is shaped through a thermal oxidation method, and a W electrode 4 is applied selectively. Especially when there is a defect in the gate oxide film 3 and an insulation withstanding voltage defective section 5 is generated at that time, the defective section can be discriminated when currents between the W electrode 4 and the Si substrate are measured. When the presence of the insulation withstanding voltage defective section 5 is made sure after applying the W electrode 4, thermally treating the whole Si wafer, from which an integrated circuit is manufactured, in H2 containing 5% H2O under conditions such as 950 deg.C and 30min thickens the thickness of the gate oxide film 3 under a section such as the gate electrode 4 up to 20nm when the thickness of the oxide film 3 is 10nm. Accordingly, the insulation withstanding voltage defective section 5 also disappear, and excellent insulating properties are obtained.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置の製造方法に係り、特にゲート電極
絶縁耐圧の向上に有効な新規な半導体装造方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a novel semiconductor manufacturing method effective for improving gate electrode dielectric strength voltage.

〔発明の背景〕[Background of the invention]

一般にSi集積回路、特にMO8型集積回路においては
極く薄い5〜100 nm厚の5i02ゲート絶縁膜が
用いられる。この8 i 02膜は製造プロセスが完全
でないため、特に薄い場合KSi基板との間に絶縁耐圧
が低い部分が発生したり極端な場合には、電気的に短絡
することがあろう〔発明の目的〕 本発明の目的は、ゲート酸化膜に欠陥があって電気的絶
縁耐圧が低くなった集積回路を、後の処理によって回復
させる新規な方法を提供するととKある。
Generally, an extremely thin 5i02 gate insulating film with a thickness of 5 to 100 nm is used in Si integrated circuits, particularly in MO8 type integrated circuits. Because the manufacturing process for this 8i02 film is not perfect, if it is particularly thin, there may be areas with low dielectric strength between it and the KSi substrate, or in extreme cases, electrical short circuits may occur [Purpose of the Invention] ] An object of the present invention is to provide a novel method for restoring an integrated circuit whose electrical withstand voltage has become low due to a defect in the gate oxide film through subsequent processing.

〔発明の概要〕[Summary of the invention]

f3iとWあるいはMOは酸素を含む雰囲気で加熱する
とそれぞれ酸化される。特にWやMOはSiに比べて酸
化速度が犬である。一方H2中の高説加熱処理ではこれ
らの酸化物は還元される。
f3i, W or MO are each oxidized when heated in an oxygen-containing atmosphere. In particular, W and MO have slower oxidation rates than Si. On the other hand, these oxides are reduced by high heat treatment in H2.

従ってH2とH2Oを適当な割合に混合すると、Slと
WやMOが共存するとsiは酸化され、かつWやMOは
還元される温度とH2とH2Oの混合比の領域が存在す
る。本発明はこの現象と利用してW+MO下の8i02
膜厚を瑠太し、電気絶縁耐圧を向上するものである。
Therefore, when H2 and H2O are mixed in an appropriate ratio, there is a range of temperature and mixing ratio of H2 and H2O in which Si is oxidized and W and MO are reduced when Sl and W or MO coexist. The present invention takes advantage of this phenomenon to generate 8i02 under W+MO.
This increases the film thickness and improves electrical insulation breakdown voltage.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の実施例を第T−第2図に示す。第1図に示
すようにSi基板l上に部分的に厚いフィールド酸化膜
2をよく知られたLOCO8(局所酸化法)法で形成す
る。その後5〜1100n厚のゲート酸化膜3企熱酸化
法で形成する。その後、W電極4を選択的に被着する。
Embodiments of the present invention are shown in FIGS. T-2 below. As shown in FIG. 1, a partially thick field oxide film 2 is formed on a Si substrate 1 by the well-known LOCO8 (local oxidation method) method. Thereafter, a gate oxide film 3 having a thickness of 5 to 1100 nm is formed by a thermal oxidation method. Thereafter, W electrodes 4 are selectively deposited.

この場合特にゲート酸化膜3に欠陥があシ、絶縁耐圧不
良部5が発生したとする。これはW電極4とSi基板1
との間の電流を測定すれば判別しうる。
In this case, it is assumed that there is a defect in the gate oxide film 3, and a breakdown voltage defective portion 5 occurs. This is W electrode 4 and Si substrate 1
This can be determined by measuring the current between the two.

絶縁耐圧不良部5の存在がWグー1−1極4被着後に判
明したら、集積回路を作るSiウェハ全体をたとえば9
50Cで30分間5%のH2Oを含んだH2中で熱処理
すると、第2図に示すようにたとえばゲート電極4下の
ゲート酸化膜3が厚さ10膜mのときは20膜mに厚く
なった。これによって絶縁耐圧不良部5も消滅して良好
な絶縁性が得られた。
If the presence of the insulation breakdown voltage failure part 5 is found after the W goo 1-1 pole 4 is deposited, the entire Si wafer for making an integrated circuit is
When heat treated in H2 containing 5% H2O at 50C for 30 minutes, for example, when the gate oxide film 3 under the gate electrode 4 was 10 m thick, it became 20 m thick, as shown in Figure 2. . As a result, the defective dielectric strength portion 5 also disappeared, and good insulation was obtained.

従って本来不良とされて棄却されるべき集積回路が良品
に変ったので、良品歩留りの向上には著しい効果かめる
Therefore, integrated circuits that should originally have been considered defective and rejected have been turned into good products, which has a significant effect on improving the yield of non-defective products.

本発明の実施例ではWゲート電極がバターニングされた
後、H2+H♀0熱処理を行ったが、バターニング前す
なわち全面にWゲート′ft極が被着されている状態で
行うこともできる。
In the embodiment of the present invention, the H2+H♀0 heat treatment was performed after the W gate electrode was patterned, but it can also be performed before patterning, that is, with the W gate 'ft electrode coated on the entire surface.

また以上の本発明の実施例では8i基板上にn+やp+
の拡散層がない場合を述べたが、これらの高濃度層を形
成した後上記H2+ H20熱処理を行うこともできる
Furthermore, in the above embodiments of the present invention, n+ and p+
Although the case where there is no diffusion layer has been described, the above-mentioned H2+H20 heat treatment can also be performed after forming these high concentration layers.

また本発明の以上の実施例では全面をH2+H20熱処
理にさらしたが、ゲート絶縁膜が厚くなって有害な部分
は、実質的にH2Oを通さない十分に厚イCV D −
S i 02膜ヤS js N4膜で覆っておくことも
できる。
Further, in the above embodiments of the present invention, the entire surface was exposed to the H2+H20 heat treatment, but the thicker and harmful gate insulating film was exposed to a sufficiently thick ICV D − that substantially prevents H2O from passing through.
It can also be covered with an S i 02 film or an S js N4 film.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、電気的絶縁不良が発
見されたら、ゲート電極形成後にゲート酸化膜を厚くし
て絶縁不良を回復して良品にできるので歩留り向上に著
しい効果がある。
As described above, according to the present invention, if an electrical insulation defect is discovered, the gate oxide film is thickened after the gate electrode is formed to recover from the insulation defect and produce a non-defective product, which has a significant effect on improving the yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の一実施例を説明するための断
面図である。 1・・・st基板、2・・・フィールド酸化膜、3・・
・ケ−) ノ VJ+ (2) 江 第 2 (2)
FIGS. 1 and 2 are cross-sectional views for explaining one embodiment of the present invention. 1... st substrate, 2... field oxide film, 3...
・K-) No VJ+ (2) Edai 2 (2)

Claims (1)

【特許請求の範囲】[Claims] 1、Si基板上に5jO2膜を介して被着した難溶金属
あるいはそのシリサイドからなる電極を有する半導体装
置において、500〜1200tZ’の温度範囲で、H
2Oを10P−10チ含むH2キャリヤガス中で熱処理
することにより、上記電極とSi基板との間の5i02
膜の膜厚を増大させる半導体装置の製造方法。
1. In a semiconductor device having an electrode made of a refractory metal or its silicide deposited on a Si substrate via a 5jO2 film, H
By heat treatment in H2 carrier gas containing 10P-10 of 2O, 5i02 between the electrode and the Si substrate is
A method for manufacturing a semiconductor device that increases the thickness of a film.
JP11583183A 1983-06-29 1983-06-29 Manufacture of semiconductor device Pending JPS609166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11583183A JPS609166A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11583183A JPS609166A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS609166A true JPS609166A (en) 1985-01-18

Family

ID=14672195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11583183A Pending JPS609166A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS609166A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04217733A (en) * 1990-12-17 1992-08-07 Matsushita Refrig Co Ltd Air conditioner
US5907188A (en) * 1995-08-25 1999-05-25 Kabushiki Kaisha Toshiba Semiconductor device with conductive oxidation preventing film and method for manufacturing the same
EP0910119A3 (en) * 1997-10-14 2001-02-07 Texas Instruments Incorporated Method for oxidizing a structure during the fabrication of a semiconductor device
US6228752B1 (en) * 1997-07-11 2001-05-08 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN100428426C (en) * 2004-03-11 2008-10-22 茂德科技股份有限公司 Structure of metal-oxide-semiconductor transistor and process for forming same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04217733A (en) * 1990-12-17 1992-08-07 Matsushita Refrig Co Ltd Air conditioner
US5907188A (en) * 1995-08-25 1999-05-25 Kabushiki Kaisha Toshiba Semiconductor device with conductive oxidation preventing film and method for manufacturing the same
US6133150A (en) * 1995-08-25 2000-10-17 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6228752B1 (en) * 1997-07-11 2001-05-08 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6417551B2 (en) 1997-07-11 2002-07-09 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
EP0910119A3 (en) * 1997-10-14 2001-02-07 Texas Instruments Incorporated Method for oxidizing a structure during the fabrication of a semiconductor device
CN100428426C (en) * 2004-03-11 2008-10-22 茂德科技股份有限公司 Structure of metal-oxide-semiconductor transistor and process for forming same

Similar Documents

Publication Publication Date Title
KR910007097B1 (en) Manufacturing method of semiconductor device
JPS609166A (en) Manufacture of semiconductor device
JPH06103691B2 (en) Method of forming thin film
JPS5910271A (en) Semiconductor device
JPS6284562A (en) Semiconductor device and manufacture thereof
JPS59200453A (en) Manufacture of semiconductor device
JP2000150508A (en) Insulating film forming method for semiconductor element
JPH0316215A (en) Formation of silicon thermal oxide film
JPS5889869A (en) Manufacture of semiconductor device
JPH0370156A (en) Manufacture of semiconductor device
JPS5816569A (en) Vertical type mosfet
JPS61150236A (en) Semiconductor device
JPH0462974A (en) Mos field-effect transistor and manufacture thereof
JPS586125A (en) Manufacture of semiconductor device
JPS6132477A (en) Manufacture of semiconductor device
JPH01239931A (en) Manufacture of electronic device with carbon film formed thereon
JPS6037147A (en) Electrode wiring
KR930008643B1 (en) Test mehtod of semiconductor i.c.
JPS6037146A (en) Manufacture of semiconductor device
JPH06224413A (en) Mos type semiconductor integrated circuit and its manufacture
JPH03154332A (en) Manufacture of semiconductor device
JPH1167756A (en) Formation treatment of oxide film on surface of semiconductor substrate
JPS59178732A (en) Manufacture of semiconductor device
JPS59121855A (en) Semiconductor device
JPH09266304A (en) Method of forming gate insulating film