JPS6090428A - Semiconductor logical circuit - Google Patents

Abstract

PURPOSE:To stabilize the reference voltage of an ECL circuit by connecting a capacitor between the base of an emitter follower transistor (TR) for reference voltage generation and the low potential of a power source. CONSTITUTION:When an input signal VIN rises to H, a transient current is superposed upon a source current and a circuit voltage varies abruptly owing to inductance, etc., on a power line to generate opposite-phase noises between points VC and VE, but the noise at the side of the point VC lowers the base potential of the emitter follower TRQ3 for reference voltage generation and the noise at the side of the point VE raises the base potential through a capacitor C1. The value of the capacitor C1 is selected properly to reduce the influence of the noises appearing between the points VC and VE, then the base potential is kept almost constant.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to stabilizing the switching operation of semiconductor logic circuits.

Conventionally, an emitter-coupled logic circuit (hereinafter referred to as E
(abbreviated as CL), this voltage is Q
A predetermined input reference voltage μ that is input to constant current transistors such as I and Q4 generates an output level.

In Figure 1, VBO (in voltage from Vm) is VBO:
Vf + Va (11), where V( is the offset voltage between the base and emitter of the transistor and is approximately soomV).

Also, va is approximately 500mV determined by the reference voltage generation circuit.
Assume that it has a voltage of -.

For the sake of simplicity of explanation, if VcR1==R3, VRO will be (voltage from Vc). That is, VB□=800mV+500mV=1
From 300 mV, VRO=1300 mV, and it is possible to generate an input reference voltage of ECL.

By the way, in recent years, the performance of semiconductor devices has improved.
The speed of CL circuits has been increased, and in recent years, CL circuits have been realized from 0.5" to 0.3 n 8 per gate stage. However, when using such a high-speed BCLf, Two problems have arisen.

This is because in a transient state when the ECL switches, a sharp transient current is added to the power supply current, and this causes a sudden voltage fluctuation in the circuit due to the inductance present at the power supply terminal.

The influence of this noise voltage will be briefly explained using FIG. Hi from the input VINICLOw of the conventional circuit in the younger brother 1 diagram
If a pulse that transitions to gb is input, the base of Qs rises at the same time, and the emitter of Qs rises with approximately the same time constant.

At this time, Q6 charges the capacitance existing in the common emitter section of Qa and Qa, but this capacitance CO mainly consists of the collector:substrate capacitance of Q4 and the base:collector capacitance of Q4, so it is shown in Figure 1. It can be thought of as a capacitor CO connected between B and B.

From this, the transient current when Qs rises is vB from the c terminal.
It flows through the path of R6*Qs ICo as shown by the dotted line in Figure 1 to the terminal.

This current flows only for a short time, almost like the Icc current shown in FIG. 3B.

If the amount of change in this current is t-di/di, ■cK is L□
Therefore, a noise voltage of ΔVC=LI x (d i/d t ) is generated. At this time, VBVC has a slight time difference, but Δ! A transient current of the same amount as cc flows into the current.

Therefore, a voltage having an opposite phase to ΔVc is generated in vE due to R2. This situation is shown in FIG. 3E.

By the way, during this transition, VRO varies according to the movement of #t'Vc. This is because the loads of R3 and Qa are constant currents, so they are not affected by fluctuations in vE.

FIG. 5 shows the relationship between input voltage and VRO. As described above, when VIN is input, VRO oscillates transiently. Input voltage is usually High (VIN) -09V
, Low (Vll,) is -1,7■, and the input reference voltage VRO is (-1,3V) as shown in equation (2).
It is.

Therefore, in DC terms, the margin between VRO and VIH# ■IL is 0.4■, but in transient terms, VRO is approximately ±0.15
V vibration through TIC, Kotvmer Shinha 0.4v-0
, 15v=0.25v.

As described above, in the conventional circuit shown in FIG. 1, even when the performance of elements such as transistors has been improved, the circuit is vulnerable to noise voltages caused by transient currents generated during switching.

An object of the present invention is to provide a circuit that operates correctly even when such a noise voltage occurs.

According to the present invention, the noise voltage generated at ■c is directly connected to VRO.
This ensures a stable input voltage and reference voltage margin.

In other words, the semiconductor logic circuit is characterized by the fact that a capacitor is connected between the pace terminal and the lowest potential terminal of the emitter follower transistor that generates the input reference voltage of the emitter-coupled logic circuit. This solves the problem of reduced input level noise margin due to transient fluctuations in VRO.

FIG. 2 shows a specific embodiment of the present invention.

In FIG. 2, VIN is input and noise voltages of opposite phases are generated at Vo and VB, similar to the conventional example shown in FIG. At this time, the noise on the Vo side operates to lower the pace potential of Qa via the resistor R3, but at the same time, the noise on the vB side operates to increase the base potential of Qa via Ctt-. Therefore, by appropriately selecting the value of C1, the base potential of Qa can be set to a constant value that is not affected by the noise of ■o and VB.

Assuming that a noise voltage of ΔvB is now generated at the Vo terminal and the Pi terminal, the amount of variation in VB0 is as follows. Here, Zl is an impedance existing between the base terminal of Qa and Vo, and is approximately R3.

Further, Zl is an impedance existing between the base terminal of Qa and vB, and is represented by C1.

In equation (3), considering that ΔVo and Δ■E operate in opposite phase by #1, taking into account the noise frequency, Z1=z2
If so, Δ■VB0 can be made almost zero.

FIG. 5 shows how this VRD fluctuation is improved. C
In the case of the conventional example without 1, the VRO fluctuates as shown by the dotted line, but if 0111c is attached, the VRO fluctuates through the vB fluctuation 1cCx.
Since it is transmitted to RO, the fluctuation of sVRo becomes smaller as shown by the solid line.

As described above, according to the present invention, it has been found that the reference voltage can be stabilized by connecting a capacitor between the base of the reference circuit generating emitter follower transistor and the lowest potential.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional ECL circuit. FIG. 2 is a diagram showing an embodiment of the present invention. Figure 3 is a diagram showing the input waveforms of the conventional ECL circuit, 00 current, ■o, ■Ro, and the voltage at the vB terminal. Figure 4 is a diagram showing the relationship between VRO and input level in the conventional ECL circuit. , FIG. 5 is a detailed illustration of the present invention. lO...Reference voltage generation circuit L 4 Atsushi -sZ

Claims (1)

[Claims] A semiconductor logic circuit characterized in that a capacitor is connected between the base terminal and the lowest potential terminal of an emitter follower transistor for generating an input reference voltage HE of an emitter-coupled logic circuit.