JPS6089892A - Refresh controller of dynamic memory - Google Patents

Abstract

PURPOSE:To attain reduction of power consumption and effective utilization by detecting the presence or alsence of access operation to each block at memory access period just before refresh period to control the refresh operation. CONSTITUTION:A memory cell array 10 is sectioned into plural blocks A-D in response to the row address and when a head row address in each block is selected in memory access period, all word lines in the block are selected continuously. Whether or not the access operation exists to each block in the memory access period just before each refresh period is detected (51-54) by, e.g., a time constant circuit or the like. In the refresh period, the refresh is not conducted as to the block accessed at the memory access period just before the refresh period based on the detected output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic memory comprising a dynamically shaped memory cell array, and more particularly to a device for improving the refresh operation of the dynamic memory.

[Technical background of the invention and its problems]

Recently, various kinds of rewritable semiconductor memory cells have been put into practical use, but among these, one MO as shown in FIG.
S) A memory cell consisting of a transistor 1 and one MOS capacitor 2 is the most common. This memory cell has a MOS transistor 1 whose dart is connected to a word line 3, whose drain is connected to a digit line 4, and stores stored data in the form of charges in a MOS capacitor 2. In addition, when a memory device such as a dynamic memory is configured from this memory cell, a plurality of word lines and a plurality of digit lines W are arranged in a matrix as shown in FIG.
The memory cells M are connected between each intersection with d.

By the way, in the case of the dynamic memory with the above configuration, 1.
As mentioned above, when unique data is accumulated in the form of ηL load,
It is lost due to leakage current, etc. That is, M.O.
If data is written to the S capacitor 2 and left until it is read, the contents stored in the MOS capacitor 2 may be reversed. Furthermore, the charge accumulated in the MOS capacitor 2 increases or decreases due to soft errors. Soft errors are caused by alpha rays emitted from small amounts of radioactive substances contained in packages and semiconductor substrates entering the diffusion layer of memory cells and bit lines.
This is when the contents stored in the memory cells are reversed or the sense amplifier malfunctions.

Therefore, in the case of dynamic memory, conventional 2 [mas
A refresh period in which data cannot be accessed is provided for each step c), and during this period, all bits of the data stored in the MOS transistor 2 are rewritten, that is, refreshed.

During this refresh, it is usual to use a refresh control circuit to select each word line in sequence and to erase and erase memory cells for each word line.

However, this type of conventional device has the following problems. That is, since the refresh is also performed on the word line selected during the access period, refreshing all bits of all word lines during the refresh period means refreshing twice in succession on word lines that do not yet require refreshing. will be carried out. Performing unnecessary refreshes in this way increases the drain current, makes it impossible to access data, and makes it impossible to shorten the refresh period.
It was inconvenient.

[Purpose of the invention]

This invention was made in view of the above circumstances, and the memory cell array is divided into a plurality of blocks, and blocks that do not require refresh operations during the refresh period are not refreshed, thereby reducing the power consumption during refresh. It is an object of the present invention to provide a refresh control device for a dynamic memory, which reduces the amount of time required and also shortens the refresh period, thereby realizing efficient use of memory.

[Summary of the invention]

The present invention is applied to so-called burst mode refresh control in which seven refresh operations are performed in a concentrated manner at predetermined intervals. In this invention, the memory cell array is divided into a plurality of blocks corresponding to row addresses, and during the memory access period, when the first row address in each block is selected, all word lines in that block are selected consecutively. At the same time, it is detected whether or not there is an access operation for each block during the memory access period immediately before each refresh period, for example, using a time constant circuit. The above object is achieved by not refreshing blocks accessed during the memory access period immediately before the 7-receive period.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail according to embodiments shown in the accompanying drawings.

FIG. 3 shows the conceptual structure of an embodiment of the present invention.

In FIG. 3, 10 is a dynamic memory cell array, 11 is a row decoder, and 20 is a pulse generator (
(hereinafter abbreviated as PG), 30 is a row address counter, 40 is a determination section, and 51 to 54 are detection circuits. Note that in FIG. 3, components of a typical dynamic memory device such as a column decoder, a row address latch, a column address latch, a sense refresh amplifier, and a control clock generator are omitted.

In the memory cell array 10, as shown in FIG. 2, each memory cell is connected between each intersection of ordinal word lines and digit lines arranged in a matrix, and a row address is input to a row decoder 11. Then, only one of the plurality of word lines WL is selected, and a required access operation or refresh operation is performed according to the control signal input at that time. During the memory access period in which reading 71N is performed, a row address is input from the CPU side (not shown), and during the refresh period, the PG 20, row address counter 30, and
A row address is input from a refresh control circuit including a determining section 40 and the like.

Here, the memory cell array 10 is divided into four blocks, A block, B block, C block, and D block, corresponding to word lines WL. In the figure, wL
A is the word line corresponding to the first row address of A program, YRI, WLB is the word line corresponding to the first row address of B block, wLC is the word line corresponding to the first row address of C block, WLD is the word line of D block. This is a word line corresponding to the first row address. This memory cell array 1
When one of the four blocks is selected, the CPU access operation for 0 is always the word line corresponding to the first row address in that block, and then the memory access period for that block is (all word lines are selected consecutively). It is assumed that the selected word line has a logic level of 71 I level.

Next, the words MI WLA + WLn, WE, corresponding to the first row address of each block A, B, C, D,
cr WLp is connected to detection circuits 51, 52, 5°3, and 54, respectively. These detection circuits 51 to 54
For example, the word lines WLA and WLB are composed of a time constant circuit formed by connecting a resistor and a capacitor in series.

When WLc and who are selected during the memory access period and become high level, the capacitor is charged,
Thereafter, the selection state ends and the capacitor is discharged by going low level. This capacitor voltage is input to the determination section 40 as the detection outputs of the detection circuits 51 to 54. In the determination unit 40, these detection circuits 51 to 54
By converting each input capacitor voltage into a binary value using a predetermined threshold value, it is determined which block's leading address has been selected during the memory access period, and this determination result is stored until the next refresh period. In other words, in this case, the fact that the word line corresponding to the row address of the first row of the block in the memory access period is selected means that all the word lines of this block are selected in this memory access period, and the next row address is selected. Refresh this block during the refresh period
By doing so, it is possible to perform two consecutive refreshes for word lines that do not yet require refreshing.

Therefore, the determination unit 40 controls, based on the detection outputs of the detection circuits 51 to 54, so that the block accessed during the memory address period immediately before each refresh period is not refreshed during each refresh period.

Next, the configuration of the refresh row address generation control section will be described.

A pulse signal for updating the row address counter 30 is output from the PG 20 . The PG 20 is started by a refresh clock Re generated based on input of a refresh request signal from the CPU, and then outputs a reference pulse signal to the row address counter 30 in accordance with a counter update signal He input from the determination section 40.

The row address counter 30 is connected to the memory cell array 10.
This is a counter for generating a row address for refresh against the refresh clock Re.
It is reset by 1 and counts up by 1 when one pulse is input from PG20. This counter 30 has a ring counter configuration that has at least the number of bits that can output each row address corresponding to all the word lines of the memory 10, and returns to the original reset state when the maximum no row address is exceeded. Suppose there is.

The count output of the row address counter 30 is determined by the determination unit 40.
is input.

The determining unit 40 outputs the manually entered row address from the row address counter 30 to the row decoder 11 in order to sequentially perform a refresh operation for blocks that have not been accessed in the immediately preceding memory access period, and also outputs the row address manually entered from the row address counter 30 to the row decoder 11.
The counter update signal He is output to 20 to update the counters sequentially, but in order to omit the refresh operation for the block accessed in the immediately previous memory access period, the sending of the row address is suppressed and the counter update signal He is output. By outputting the same number of word lines belonging to one array block, pulses are generated in the PG 20, and the row address counter 30 is skipped to the first row address of the next block. Further, in each refresh period, the determination unit 40 outputs a clock signal Bc indicating the end of each refresh period to the CPU when the output of the row address counter 30 returns to the original initial reset state again.

Next, an example of the operation of the body of the embodiment shown in FIG. 3 will be explained according to the flowchart shown in FIG. 4.

One memory access period for reading or writing to memory 10 ends, and memory 10 enters a refresh period. In addition, in this operation example,
Assume that an access operation for block B of the memory cell array 10 is performed in the memory access period immediately before the refresh period. Therefore, the detection circuits 51 to 5
4, the detection circuit 52 detects the word ' corresponding to the first row address of block B in the previous memory access period.
IM WLB's y' haze selection state is detected and ''JJ 2
Part 40ji is aware of this.

As the first operation in the refresh period, a refresh request signal indicating the start of a refresh operation is input from a CPU (not shown) outside the chip to a refresh control section (not shown) inside the chip, and as a result, the PG20
Then, the refresh clock Re is input to the row address counter 30 (step 1oo). As a result, the row address counter 30 is reset (step 110) and the PG 20 is started (step 12o).
. At this time, one (7) /4' pulse signal is output to PG2 (H; be done. Here, the determination unit 40 searches whether the output of the row address counter 3o exceeds the maximum row address for the memory 10 and returns to the original reset state (step 140).
). At the start of refresh U#J (at this time, the row address counter 30 is incremented by 1, so in this case the control shifts to STAY 7' 150. At STAY 7' 150, the determination unit 40 detects the detection circuit 51 Based on the detection outputs of 54 to 54, it is determined whether a refresh operation is necessary for the block corresponding to the row address specified by the count output of the row address counter 30.As mentioned above, block A was accessed during the immediately preceding access period. Therefore, the detection circuit 51 does not output a detection signal indicating that the beam freshener is not required.
After the determination unit 40 stops the PC 20 (step 160
), the count output of the row address counter 30 is output to the row decoder 11 as the row address ADa. The row decoder 11 decodes and outputs the row address to select the word line, ie, WL, corresponding to the first row address of the A7' lock. Of course, at this stage, a control signal for performing a refresh operation has already been input to the memory cell array 10, and if a word line is selected, the memory 10 is in a state where refreshing for that word line is executed. ing. Therefore, first the memory cells connected to the word IJWLA of block A are refreshed (step 170).
. When the refresh for this word line WLA is completed, the control returns to Stellar ("Return to 120"), and then the row addresses are updated one by one by repeating the loop of Stellar f13L141L150, 160, 170, Af
Refreshing is performed sequentially for all word lines for the o work.

Refreshing for block A is completed, and the first row address of block B is input from the cell address counter 30 to the determination unit 4o. The determination unit 40 performs step 15
0, it is determined whether or not a refresh operation is necessary for block B. However, as mentioned above, block B has been accessed during the memory access period immediately before the 7th refresh period, so the detection circuit 52 detects the need for the memory access. The high level of the word line WLB is detected during the period -, and this detection output is input to the determination section 40. The determining unit 4o stores this information, determines that refreshing for the B block is unnecessary, suppresses the output of the row address to the row decoder 11, and sends the counter update signal He to the PG2o to the word line belonging to the B block. There will be as many appearances as there are. As a result, the row address counter 3o skips to the first row address of the C block (Stella f180
). In this way, the refresh operation for B2rI is suppressed.

Next, since the C block and D block have been accessed in the previous memory access period, the following step 1 is performed.
The loop of 40.15-0.160, 170, 120.degree. Soshite, D
When the freshness of the block is completed, the output of the row address counter 3o exceeds the maximum row address and returns to the original reset state, as described above. The determining unit 4o detects this in step 140 and outputs a clock Ee to the CPU indicating the end of the current Nori Friendship period. C.P.
U detects this, and memory cell array 1o selects the next memory r.
) Transition to the access period (step 190).

By the way, in a normal dynamic memory, the interval time of each refresh period is about 2 m5ec at maximum. In the embodiment described above, refresh is not performed on blocks accessed during the memory access period immediately before each refresh period. Therefore, this unrefreshed block needs to be refreshed in the next refresh period unless it is accessed in the next memory access period. From this, the interval time of each refresh period used in the above embodiment is determined from the above 2. It is necessary to set the time to a somewhat shorter time than msee.

Furthermore, in the above embodiment, the time from step 120 to step 170 in FIG. The refresh period can be further shortened by controlling the word lines of a block to take the same refresh time as usual, and skipping the word lines of a block accessed in the immediately preceding access period in a much shorter time. Such 10 control can be easily realized, for example, by adjusting the width of the pulse output from the PG 20. In other words, PG20 means a timer circuit for setting the time required to refresh one word line, and in the case of a block that performs refreshing, it has a clock width corresponding to the refresh time for one word line. A? If a block is not refreshed, a /4' pulse signal with a short pulse width may be outputted to skip the counter 30 at a higher speed.

In the above embodiment, a detection circuit for detecting whether each block is accessed is connected to each word line corresponding to the first row address of each block, but in each memory access period, the CPU As long as the word line corresponding to the first row address in the block is selected first, and then access is performed such that all word lines are selected consecutively during this memory access period, any row address in each block can be selected. The presence or absence of an access operation for each program may be detected using at least one word line corresponding to the program.

Further, in the above embodiment, time constant circuits were used as the detection circuits 51 to 54, which are charged with a predetermined time constant when a predetermined word line in each block is in a selected state, and are discharged when the selected state ends. Needless to say, a detection circuit for detecting the selected state of a word line using other methods may also be used.

The dynamic memory refreshed by the method of the present invention described above may be used, for example, as a memory for data transfer,
When adopted in a memory for static screen display in VTRs and the like, the power required for refresh operations can be reduced, and the refresh period can also be significantly shortened.

〔Effect of the invention〕

As described above, according to the present invention, the memory cell array is divided into a plurality of blocks, and refresh is performed only on the goolocks that have not been accessed during the memory access period immediately before each refresh period. In addition to significantly reducing power consumption during the refresh period, the refresh time can be shortened because refresh operations are not performed for memory that is determined not to require refresh during the refresh period. can be used efficiently. This invention works particularly effectively when memory is frequently accessed.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of one memory cell, FIG. 2 is a schematic diagram showing the configuration of a dynamic memory cell array, and FIG. 3 is a diagram showing the configuration of an embodiment of the present invention! Four 2 figures, 4th figure is 3rd figure
3 is a flowchart illustrating an example of the operation of the embodiment shown in the figure. 1...MO8) transistor, 2.i.capacitor, 3
. . . word line, 4 . . . digit line, 10 . . . memory cell array, 20 . . . pulse generator, 30.
... Row address counter, 40 ... Judgment section, 51,
52°53.54...Detection circuit.

Claims (4)

[Claims] (1) A dynamic memory having a matrix-like memory cell array is refreshed intensively during one refresh period at predetermined intervals, and each block is divided into blocks corresponding to &, rows, and rows during the memory access period. In a dynamic memory 1 refresh control device in which when the first row address in a block is selected, all word lines in that block are selected consecutively, each word line in the memory access period immediately before the refresh period is A detection circuit detects the presence or absence of an access operation to a block, and based on the output of the detection circuit, a memory access period immediately before the refresh period is provided.For the accessed block, one refresh is not performed in one period. What is claimed is: 1. A dynamic memory refresh control device, characterized in that it comprises a refreshing means. (2) The detection circuit is connected to a word line corresponding to the first row address in each block to detect the presence or absence of an access operation to each block.
1) The dynamic memory refresh control device described in item 1). (3) The dynamic memory according to claim (1), wherein the detection circuit is connected to at least one word line corresponding to an arbitrary row address in each block to detect the presence or absence of an access operation for each block. refresh controller. (4) The detection circuit is charged with a predetermined time constant when the word line of each block to which the detection circuit is connected enters a selected state, and is left alone when the selected state ends.