JPS608763A - Self-diagnostic circuit - Google Patents

Abstract

PURPOSE:To check the function of a counter to test a counter part independently and perform the test with a number of stages smaller than that of a conventional circuit, by comparing a parity signal and a forecasted party signal with each other in the counter provided with a parity extracting circuit and a separately extracted parity forecasting circuit to diagnose the trouble of the counter part. CONSTITUTION:In case that self-diagnosis is executed in a counter unit without segment division, a system clock (the first bit) 6, the second bit 7, the third bit 8, and an output bit (the fourth bit) 9 pass a parity detecting circuit, and a parity bit is outputted to an output line 13. The parity detecting circuit consists of an XOR, and ''0'' or ''1'' is outputted from the output line 13 in accordance with an even or odd-number of ''1''s of individual bits. A counter part B is provided. The signal outputted from an output line 16 from a parity forecasting circuit 14, to which bit output lines 6,7,8, and 9 are inputted, through a delay circuit 15 is compared with the parity 13, and ''0'' is outputted from a terminal OUT if coincidence between them (normality) is detected in an XOR 17; but ''1'' is outputted from the terminal OUT if disaccord (abnormality) is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a counter self-diagnosis circuit, and particularly to a self-diagnosis circuit provided with a parity prediction circuit.

[Prior art and its problems] In the case of a circuit that includes an internal counter, the test pattern is generally long, but as the scale of circuits has increased in recent years, testing the entire circuit has become unrealistic. . In this case, it is considered to test the counter section separately, but conventionally, the main function test for counters is
This caused a drop in test efficiency.

[Object of the Invention] The present invention has been made in view of the above-mentioned points, and in particular, an object of the present invention is to provide a quality check device in which a counter is divided into blocks.

[Summary of the Invention] Hereinafter, the outline of the present invention will be explained with reference to the drawings. Fig. 1 is a block diagram showing one segment of the counter diagnostic device of the present invention. The parity detected from the counter 1 by the parity extraction circuit 2 passes through the XOR circuit 5 and is output and displayed on the dUT to be compared with the signal that has passed through the parity prediction circuit 3 and the delay circuit 4.

In the present invention, several of these segments are used and the counter is tested in segment units. A is a synchronization signal. [Effects of the Invention] This method allows the function of the counter to be inspected, making it possible to test the counter section alone. Also, it is possible to find a faulty counter section, which is different from the conventional predictive harness circuit. Testing is possible with a much smaller number of stages.

Embodiment of the Invention An embodiment of the invention will be described in detail below with reference to the drawings. FIG. 2 shows an example of a counter circuit.

That is, this device performs a clock application counter operation. Of course, the counter circuit can have many configurations other than those shown in the figure.

FIG. 3 is an example in which the present invention is implemented in units of all counters without dividing into segments. System clock (1st bit)
6, the second pit 7, the third bit 8, and the output bit (fourth bit) 9 pass through 12 parity detection circuits and are outputted to an output screen 13. The parity detection circuit consists of an
, H1g are output from the output m13. B indicates a counter section.

On the other hand, bit output lines 6, 7, and 8.9 pass through 14 parity prediction circuits and 15 delay circuits to output line 1.
The signals output more than 6 are compared with parity 13, and 17
If they match (normal), "O11" and if they do not match (abnormal), "111" is output from OUT.

Furthermore, Table 1 was prepared for supplementary explanation of the parity prediction circuit, and shows each bit of a normal octal counter and the parity value. Depending on the value of each bit at a certain point in time, the value at the moment when the next clock pulse is input is uniquely determined, and of course its parity value is uniquely determined υ and can be predicted. It is easy to design a circuit that calculates the predicted parity from bit values.

Margin table below 1 Based on the above idea, a 2-bit parity prediction circuit,
A 3-bit parity prediction circuit is shown in FIGS. 4 and 5.

C is the second bit, D is the predicted parity, and E is the first pit (
(system clock), F is the second bit, G is the third bit, and H is the predicted parity. Further, the 15 delay circuits are circuits that delay the output of the prediction circuit by one clock, and can be constructed from flip-flops.

FIG. 6 shows an example in which an octal counter is constructed and implemented by dividing it into two segments, a 3-bit part and a 2-bit part, based on the present invention. In the figure, 18 is a 3-bit segment, and 19 is a 2-bit segment.
The delay circuits are each synchronized with the system clock and the third bit, and after each bit check is completed, the output is displayed by ORing. Furthermore, it is also possible to estimate the faulty part by connecting a decoder instead of the OR in B. Particularly in the case of a counter with a large number of bits, it is easier to divide the check into segments in this way, considering the number of stages and ease of turning. The advantage is that it can be divided into two types of segments: 3 bits and 2 bits.
This can be understood by comparing Figures 3 and 6.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an outline of the present invention, Fig. 2 is a circuit diagram showing an example of a counter, Fig. 3 is a circuit diagram of an octal counter self-diagnosis circuit, and Fig. 4 is a circuit diagram showing an example of a counter. FIG. 5 is a circuit diagram of a 3-bit parity prediction circuit shown in FIG. 6, and FIG. 6 is a circuit diagram of an embodiment of the present invention. In the figure, 1...counter, 2...parity extraction circuit, 3...parity prediction circuit, 4...delay circuit. 5..., X0J 1'... Count pulse (system clock), l"
... Reset signal line, 9... Fourth bit (output), 12... Parity detection circuit, 13... Parity signal line, 14... Parity prediction circuit, 15... Delay circuit, 16 ...Predicted parity signal line, 17...x6R. 18...3 bit part diagnostic circuit, 19...2 bit part diagnostic circuit, addition...3 bit part parity prediction circuit (Fig. 5), 21
...Delay circuit (~15), n...2-bit parity prediction circuit (Figure 4), n...
...OR0 Agent Patent attorney Noriyuki Chika (and 1 other person) Figure 4 C Figure 5 'ET&

Claims (2)

[Claims] (1) A self-diagnosis circuit that diagnoses failures in the counter section by comparing the parity signal and the predicted parity signal in a counter equipped with a parity extraction circuit and a parity prediction circuit extracted separately. . (2) In the above, the patented self-diagnosis circuit is characterized in that, especially in the case of a multi-bit counter, a circuit is provided which divides the bit into multiple parts and generates predicted parity for each part, and compares it with the actual parity.