JPS6087616A - Ratio differential relaying device - Google Patents

Ratio differential relaying device

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Publication number
JPS6087616A
JPS6087616A JP58195308A JP19530883A JPS6087616A JP S6087616 A JPS6087616 A JP S6087616A JP 58195308 A JP58195308 A JP 58195308A JP 19530883 A JP19530883 A JP 19530883A JP S6087616 A JPS6087616 A JP S6087616A
Authority
JP
Japan
Prior art keywords
suppression
circuit
amount
ratio
characteristic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58195308A
Other languages
Japanese (ja)
Inventor
高野 律朗
山浦 充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58195308A priority Critical patent/JPS6087616A/en
Publication of JPS6087616A publication Critical patent/JPS6087616A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は送電線、母線等の多端子系統を小電流域から大
電流にわたって保護する比率差動継電装置に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a ratio differential relay device that protects multi-terminal systems such as power transmission lines and busbars from small current ranges to large currents.

〔発明の技術的背景とその問題点〕・ る。[Technical background of the invention and its problems]・ Ru.

IJI図は従来の2端子保護用の表示線継電装置の構成
の1例を示したものである。第2図は第1図の構成によ
って得られる表示線継電装置の比率特性の1例を示す図
で大電流域での比率は主CT飽和等による誤差を考慮し
て小電流域の比率より大きくした折線特性を有するもの
が用いられる。
The IJI diagram shows an example of the configuration of a conventional display line relay device for protecting two terminals. Figure 2 is a diagram showing an example of the ratio characteristics of the display line relay device obtained with the configuration shown in Figure 1. The ratio in the large current range is greater than the ratio in the small current range, taking into account errors due to main CT saturation, etc. A material having enlarged broken line characteristics is used.

第1図において、A端子電流IA及びB端子電流IBは
それぞれ補助変流器IA及びIBにより適当な値に変換
されたのち、ベクトル和導出回路2により差動量Id(
ΣI)を、スカラー和導出回路3により抑制量ΣII+
を導出する。スカラー和導出回路3により導出された抑
制量は第1の抑制回路5Aにより抑制係数に1、第2の
抑制回路5Bにより抑制係数xt(>xt)倍されて、
それぞれ加算回路6A。
In FIG. 1, the A terminal current IA and the B terminal current IB are converted into appropriate values by auxiliary current transformers IA and IB, respectively, and then the vector sum derivation circuit 2 converts the differential amount Id (
ΣI) is reduced by the scalar sum derivation circuit 3 to the suppression amount ΣII+
Derive. The suppression amount derived by the scalar sum derivation circuit 3 is multiplied by 1 as a suppression coefficient by the first suppression circuit 5A, and multiplied by the suppression coefficient xt (>xt) by the second suppression circuit 5B.
Adder circuit 6A, respectively.

6Bで余波整流回路4により整流された差動量IId+
(lΣII)、すなわち動作量と演算され、低域通過フ
ィルタ回路7A、7B及びレベル検出回路8A。
Differential amount IId+ rectified by the aftermath rectifier circuit 4 at 6B
(lΣII), that is, the operation amount, and the low-pass filter circuits 7A, 7B and the level detection circuit 8A.

8Bを径てそれぞれ出力するようになっている。8B and outputs them respectively.

一点鎖線部12Aの第1の比率特性回路により1ΣII
−に、ΣIII≧に0 ・・・・・・(1)を判別し、
第2図の直線部aの比率特性を得、一点鎖線部12Bの
第2の比率特性回路により1ΣIl−に、ΣIII≧K
o−K ・’・(2)(KOp Kt ic、 p K
tは定数)を判別し、第2の直線部すの比率特性を得る
1ΣII by the first ratio characteristic circuit of the dashed-dotted line portion 12A.
-, ΣIII≧0... (1) is determined,
Obtain the ratio characteristic of the straight line part a in FIG.
o-K ・'・(2) (KOp Kt ic, p K
t is a constant) to obtain the ratio characteristic of the second straight line portion.

AND回路11により第1の比率特性(すなわち小電流
域の比率特性)と第2の比率特性(すなわち大電流域の
比率特性)のAND条件により第2図のような折線特性
の比率特性を得ている。
The AND circuit 11 obtains the ratio characteristic of the broken line characteristic as shown in FIG. ing.

第2図のF点のような外部事故では、第1の比率特性(
直線部a)は不動作体態から動作へ、第2の比率特性(
直線b)は動作状態から復帰するように応動する。9I
41の比率特性の動作が第2の比率特性の復帰時間より
速いと誤動作することになる。このため動作時遅延回路
9が前述の再特性の時間協調をとるために備えられてい
る。逆に1点外部事故から0点に事故回復した場合のた
めに動作時遅延回路10により時間協調がとられる。
In an external accident like point F in Figure 2, the first ratio characteristic (
The straight line part a) changes from the inactive state to the active state, and the second ratio characteristic (
Straight line b) responds to return from the operating state. 9I
If the operation of the ratio characteristic No. 41 is faster than the recovery time of the second ratio characteristic, a malfunction will occur. For this reason, an operating delay circuit 9 is provided for time-coordinating the above-mentioned re-characteristics. On the other hand, time coordination is performed by the operation delay circuit 10 in case the fault recovers from a 1-point external fault to a 0-point fault.

前述したように従来は第1の比率特性を有する要素と第
2の比率特性を有する要素の2要素から成っているので
その回路構成が大きくなること、また前記2要素のAN
D条件より1!電器特性を得ているため前記2要素の時
間協調が必要となり、これが、継電器の動作時間をより
高速度にするための障害になっていた。
As mentioned above, since the conventional method consists of two elements, an element having the first ratio characteristic and an element having the second ratio characteristic, the circuit configuration becomes large, and the AN of the two elements
1 from condition D! Since electric characteristics are obtained, time coordination between the two elements is required, and this has been an obstacle to increasing the operating time of the relay.

〔発明の目的〕[Purpose of the invention]

本発明は前述の点を鑑みてなされたもので、簡単な構成
で、しかも小電流域の比率特性と大電流域の比率特性と
の時間協調を不要にした高速度の比率差動継電装置を提
供することを目的としている。
The present invention has been made in view of the above-mentioned points, and is a high-speed ratio differential relay device that has a simple configuration and eliminates the need for time coordination between ratio characteristics in a small current range and ratio characteristics in a large current range. is intended to provide.

〔発明の概要〕[Summary of the invention]

小電流域の比率特性と大電流域の比率特性に応じた2つ
の抑制量のうち最大の抑制量を動作量と比較するように
構成することにより、第2図C二本すような比率特性を
得る。
By configuring the structure so that the maximum amount of suppression among the two amounts of suppression corresponding to the ratio characteristics in the small current region and the ratio characteristics in the large current region is compared with the operating amount, the ratio characteristics such as the two in Figure 2 C can be achieved. get.

〔発明の実施例〕[Embodiments of the invention]

(一実施例) 第3図に本発明による一実施例を示す。まず本実施例の
回路構成から説明する入端子電流IA、B端子電流IB
は補助変流器IA及びIBにより適当な値に変換され、
ベクトル和回路2とスカラー和回路3にともに導入され
る。ベクトル和回路2の出力は余波整流回路4により余
波整流される。一方、スカラー和回路3の出力は第1の
抑制回路5人及び第2の抑制回路5Bに導入され、それ
ぞれの出力は最大値検出回路13に導入され、検出され
た最大の抑制量と前記全波整流回路4の出力すなわち動
作量が加算回路6により演算される。加算回路6の出力
は低域通過フィルタ回路7及びレベル検出回路8を経て
出力回路11により最終出力となる。
(One Embodiment) FIG. 3 shows an embodiment according to the present invention. First, the input terminal current IA and B terminal current IB will be explained from the circuit configuration of this embodiment.
is converted to an appropriate value by auxiliary current transformers IA and IB,
It is introduced into both the vector sum circuit 2 and the scalar sum circuit 3. The output of the vector sum circuit 2 is subjected to aftereffect rectification by an aftereffect rectification circuit 4. On the other hand, the output of the scalar sum circuit 3 is introduced into the first five suppression circuits and the second suppression circuit 5B, and the respective outputs are introduced into the maximum value detection circuit 13, and the detected maximum suppression amount and the total The output of the wave rectifier circuit 4, that is, the amount of operation, is calculated by the adder circuit 6. The output of the adder circuit 6 passes through a low-pass filter circuit 7 and a level detection circuit 8, and then becomes a final output from an output circuit 11.

次に作用について説明する。第3図において、A端子電
流IAは補助変流器IAにより適当な値に変換され、B
端子電流IBも同様に補助変流器IBにより適当な値に
変換される。ベクトル和回路2により動作量(差動fi
)Id=Σ工が得られ、スカラー和回路3により抑制量
Σ1Il=IIAl+1tBlが得られる。スカラ和回
路3により得られた抑制量81月は、第1の抑制回路5
人によりに1ΣIIIに、第2の抑制回路5Bによりに
、 l I l−になる抑制量にそれぞれなる。最大値
検出回路13によりに、ΣIIIかに2Σlll−にの
大なる量が選択される。第1の比率特性(小電流域特性
)においては 1ΣII−に、ΣIII≧に0 なる特性式であり、第2図の直線aの特性となる。
Next, the effect will be explained. In Figure 3, A terminal current IA is converted to an appropriate value by auxiliary current transformer IA, and B
Terminal current IB is similarly converted to an appropriate value by auxiliary current transformer IB. The vector sum circuit 2 calculates the amount of operation (differential fi
) Id=Σ is obtained, and the scalar sum circuit 3 obtains the suppression amount Σ1Il=IIAl+1tBl. The amount of suppression obtained by the scalar sum circuit 3 is the amount of suppression obtained by the first suppression circuit 5.
Depending on the person, the amount of suppression will be 1ΣIII, and depending on the second suppression circuit 5B, the amount of suppression will be l I l-. The maximum value detection circuit 13 selects a large amount of ΣIII or 2Σllll-. In the first ratio characteristic (small current range characteristic), the characteristic equation is 1ΣII- and ΣIII≧0, which is the characteristic of straight line a in FIG.

第2の比率特性(大電流域特性)においては1Σ1t(
KtΣIII−K)≧KO 1゛、1ΣII−に、ΣIII≧に0−になる特性式で
第2図の直線すの特性となる。
In the second ratio characteristic (large current range characteristic), 1Σ1t(
KtΣIII-K)≧KO 1゛, 1ΣII-, and ΣIII≧, 0-, resulting in the characteristic of the straight line in FIG.

第2図において第1の比率特性(小電流域特性)と第2
の比率特性(大電流域特性辺交点nにおいて、抑制量は
に、Σl I l =に2Σlll−に、n点より大き
い電流域ではに2ΣIII K>KrΣIII、n点よ
り小さい電流域ではに、ΣrIl−K<KlΣIIIで
あるので第2図斜線部が動作域となる特性が得られる。
In Figure 2, the first ratio characteristic (small current range characteristic) and the second
(Large current range characteristic At the intersection n of the sides, the amount of suppression is Σl I l = 2Σllll-, in the current range larger than n point, 2ΣIII K>KrΣIII, in the current range smaller than n point, ΣrIl Since -K<KlΣIII, a characteristic is obtained in which the shaded area in FIG. 2 is the operating range.

前述のようにして検出された抑制量は加算回路6により
動作量1Σ11と演算され、加算回路6の出力は低域通
過フィルタフにより平滑されてレベル検出回路8でレベ
ル検出されて、出力回路11により最終出力となる。
The suppression amount detected as described above is calculated by the addition circuit 6 as the operation amount 1Σ11, and the output of the addition circuit 6 is smoothed by a low-pass filter, the level is detected by the level detection circuit 8, and the output circuit 11 This will be the final output.

本実施例によれば抑制量に1ΣIIIとに2Σl I 
l −にのうち最大のものを抑制量として、第2図の比
率特性を得ているので従来のような2つの比率特性の時
間協調が不要となり、高速度動作の比率差動継電装置が
得られ、しかも回路構成も簡単となる。
According to this embodiment, the suppression amount is 1ΣIII and 2Σl I
Since the ratio characteristics shown in Fig. 2 are obtained by taking the maximum amount of suppression in l - as the amount of suppression, there is no need for time coordination of the two ratio characteristics as in the past, and a ratio differential relay device with high speed operation can be used. In addition, the circuit configuration is simple.

(他の実施例) 以上は2端子系統について述べたが3端子以上の系統に
ついても同様に実施できることは言うまでもない。
(Other Embodiments) Although the above description has been made regarding a two-terminal system, it goes without saying that the same can be implemented for systems with three or more terminals.

さらに、2つの比率特性を有する場合について説明した
が、第4図のように3つの・比率特性を有する場合も同
様な効果が得られる。第4図のa、b。
Furthermore, although the case where there are two ratio characteristics has been described, the same effect can be obtained when there are three ratio characteristics as shown in FIG. Figure 4 a, b.

Cとの3つの比率特性を得るため第5図のように第1の
抑制回路5A、1g2の抑制回路5B、第3の抑制回路
5Cに応じた抑制量を最大値検出回路13(二よりこれ
らの最大値が抑制量となるようにすれば 4゜第4の特
性が得られる。このように第3の抑制回路5とを付加す
るのみで構成できるので非常にコンパクトになる。この
ようにすれば3つ以上の比率特性を有する場合も同様に
適用できる。
In order to obtain three ratio characteristics with C, as shown in FIG. If the maximum value of is set as the amount of suppression, the fourth characteristic of 4° can be obtained.In this way, it can be configured by simply adding the third suppression circuit 5, making it extremely compact. For example, it can be similarly applied to a case where the ratio characteristics have three or more ratio characteristics.

また、抑制量としてスカラー和を用いた場合について述
べたが他の方法例えば各端子電流の最大値を抑制量とし
た最大値抑制方式などを使っても同様の効果が得られる
Furthermore, although the case where a scalar sum is used as the suppression amount has been described, the same effect can be obtained by using other methods such as a maximum value suppression method in which the maximum value of each terminal current is used as the suppression amount.

表示線継電装置ばかりでなく FM電流差動継電装置、
母線保護装置などの他の比率差動継電装置にも適用でき
る。
Not only display line relay device but also FM current differential relay device,
It can also be applied to other ratio differential relay devices such as busbar protection devices.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明によれば第1の比率特性(小
電流域)と$2の比率特性(大電流域)の時間協調が不
要になり高速度動作が慴られ、抑制量の中の最大値が常
に抑制として働くから外部事故で誤動作するようなこと
はなく、更に内部の回路構成が簡単になり縮小化が図れ
る比率差動継電装置を得ることができる。
As described above, according to the present invention, there is no need for time coordination between the first ratio characteristic (small current range) and the second ratio characteristic (large current range), high-speed operation is preferred, and the amount of suppression is reduced. Since the maximum value of always acts as a restraint, there is no possibility of malfunction due to an external accident, and furthermore, the internal circuit configuration is simplified and a ratio differential relay device that can be downsized can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の表示線継電装置の構成図、第2図は第1
図に示した表示線継電装置の比率特性図、第3図は本発
明の一実施例を示す図、第4図は3つの比率を有する表
示線継電装置の比率特性図、第5図は第4図の特性を得
るための表示線継電装置の構成図である。 IA、IB・・・補助変流器 2・・・ベクトル和回路 i・・・スカラー和回路 4・・・全波整流回路 5A、5B、5C・・・抑制回路 6・・・加算回路 7・・・低域通過フイールタ回路 8・・・レベル検出回路 9・・・動作時遅延回路 10・・・動作時遅延回路 11・・・出力回路 12A・・−第1の比率要素 12B・・・第2の比率要素 13・・・最大値検出回路 (73j−7) 代理人 弁理士 則 近 憲 佑(ほ
か1名) 第1図 第2図 第3図
Figure 1 is a configuration diagram of a conventional display line relay device, and Figure 2 is a diagram of a conventional display line relay device.
3 is a diagram showing an embodiment of the present invention, FIG. 4 is a ratio characteristic diagram of the display wire relay device having three ratios, and FIG. 5 is a ratio characteristic diagram of the display wire relay device shown in the figure. 4 is a configuration diagram of an indicator line relay device for obtaining the characteristics shown in FIG. 4. FIG. IA, IB...Auxiliary current transformer 2...Vector sum circuit i...Scalar sum circuit 4...Full wave rectifier circuit 5A, 5B, 5C...Suppression circuit 6...Addition circuit 7. ...Low pass filter circuit 8...Level detection circuit 9...Operating delay circuit 10...Operating delay circuit 11...Output circuit 12A...-first ratio element 12B...th Ratio element 13 of 2...Maximum value detection circuit (73j-7) Agent Patent attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 被保護系統の各端子の電流を得て、各端子電流の和に応
じた動作量を発生する動作量導出回路と、各端子電流に
所定の演算を施して抑制量を発生する抑制量導出回路と
を備え、前記抑制量を少くとも2個以上の異なる抑制率
に応じた抑制量とし、これら抑制量の最大の抑制量と前
記動作量との大小関係に応動することを特徴とした比率
差動継電装置。
An operation amount derivation circuit that obtains the current of each terminal of the protected system and generates an operation amount according to the sum of each terminal current, and a suppression amount derivation circuit that performs a predetermined calculation on each terminal current to generate a suppression amount. The ratio difference is characterized in that the amount of suppression is a suppression amount corresponding to at least two or more different suppression rates, and the ratio difference is responsive to a magnitude relationship between a maximum suppression amount of these suppression amounts and the amount of operation. Dynamic relay device.
JP58195308A 1983-10-20 1983-10-20 Ratio differential relaying device Pending JPS6087616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58195308A JPS6087616A (en) 1983-10-20 1983-10-20 Ratio differential relaying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58195308A JPS6087616A (en) 1983-10-20 1983-10-20 Ratio differential relaying device

Publications (1)

Publication Number Publication Date
JPS6087616A true JPS6087616A (en) 1985-05-17

Family

ID=16338993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58195308A Pending JPS6087616A (en) 1983-10-20 1983-10-20 Ratio differential relaying device

Country Status (1)

Country Link
JP (1) JPS6087616A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5013860A (en) * 1973-06-11 1975-02-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5013860A (en) * 1973-06-11 1975-02-13

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