JPS6086976A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPS6086976A
JPS6086976A JP58194293A JP19429383A JPS6086976A JP S6086976 A JPS6086976 A JP S6086976A JP 58194293 A JP58194293 A JP 58194293A JP 19429383 A JP19429383 A JP 19429383A JP S6086976 A JPS6086976 A JP S6086976A
Authority
JP
Japan
Prior art keywords
signal
output
cod
vertical
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58194293A
Other languages
Japanese (ja)
Inventor
Takuya Imaide
宅哉 今出
Akihide Okuda
章秀 奥田
Ryushi Nishimura
龍志 西村
Michio Masuda
増田 美智雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58194293A priority Critical patent/JPS6086976A/en
Publication of JPS6086976A publication Critical patent/JPS6086976A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To suppress the low frequency noises and to improve the sensitivity with a solid-state image pickup device by subtracting the bias signal component which is transferred into a charge coupled element from the level of the output signal of said coupled element. CONSTITUTION:A photodiode group 8 is arrayed 2-dimensionally and connected to a charge coupled element 41 for horizontal transfer by a coupling part 5 and via plural vertical switches and vertical signal lines. The element 41 transfers the bias signal component even after it transferred the n-picture element signals within a horizontal scanning period tau1. Here a stage equivalent to (m) picture elements is set before a stage of (n) picture elements. Thus the m-picture element stage is not connected to the part 5. In such a way, it is possible to subtract the bias signal component from the output of the device 41.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は固体撮像装置に係シ、特に高感度化に好適な固
体撮像装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device suitable for increasing sensitivity.

〔発明の背景〕[Background of the invention]

半導体基板上に光電変換素子をプレイ状に設けた固体撮
像装置は、従来の真空管撮像装置に比べ大きさ、重量、
消費電力、焼付け、残像、寿命、安定性の点で有利であ
り、脚光を浴ひている。現在製品化されている固体撮像
装置は、MOS形、OPD形、CCD形の6種類である
このうちOPD形はMOS形とCCD形の長所を合わせ
持つ撮像装置として注目されている。
Solid-state imaging devices, in which photoelectric conversion elements are arranged in a play-like manner on a semiconductor substrate, are smaller in size, weight, and weight compared to conventional vacuum tube imaging devices.
It is attracting attention because of its advantages in terms of power consumption, burn-in, afterimage, lifespan, and stability. There are six types of solid-state imaging devices currently being commercialized: MOS type, OPD type, and CCD type. Of these, the OPD type is attracting attention as an imaging device that combines the advantages of the MOS type and the CCD type.

以下第1図〜第3図を用いてCPD形撮像装置の従来例
を説明する。
A conventional example of a CPD type imaging device will be described below with reference to FIGS. 1 to 3.

第1図はOPD形撮像装置の一従来例である1が水平転
送用00D(電荷結合素子)で、入力部2、転送部6、
出力部4から成る。8がオートダイオード部で、垂直信
号線9、垂直MOSトランジスタ10 オートダイオー
ド11 垂直ゲート線12から成る。5がCCD1とオ
ートダイオード部8を結合する結合部であゆ、本例では
MOS)ランジスタロと転送ゲート線7から成る。結合
部5は、垂直信号線9からC0D1への転送効率を上げ
るための回路や、垂直スメアなどの不要信号を外部へ掃
出す回路を設けて、通常、もっと複雑な回路構成となっ
ているが・本例では最も簡単な例を示している。
FIG. 1 shows a conventional example of an OPD type imaging device, in which 1 is a horizontal transfer 00D (charge coupled device), an input section 2, a transfer section 6,
It consists of an output section 4. Reference numeral 8 denotes an autodiode section, which includes a vertical signal line 9, a vertical MOS transistor 10, an autodiode 11, and a vertical gate line 12. Reference numeral 5 denotes a coupling section for coupling the CCD 1 and the autodiode section 8, and in this example, it consists of a transistor (MOS) transistor and a transfer gate line 7. The coupling section 5 usually has a more complicated circuit configuration, including a circuit for increasing the transfer efficiency from the vertical signal line 9 to the C0D1 and a circuit for sweeping out unnecessary signals such as vertical smear to the outside.・This example shows the simplest example.

13が垂直走査回路であシ、走査回路13の出力は垂直
ゲート線12に接続している。
13 is a vertical scanning circuit, and the output of the scanning circuit 13 is connected to the vertical gate line 12.

水平帰線期間に、指定のラインのホトダイオード11上
の信号電荷を垂山MO8)ランジスタ10を介して垂直
信号線9に読出し、その後結合部5を介してOOD転送
部6に読出す。
During the horizontal retrace period, the signal charge on the photodiode 11 of a designated line is read out to the vertical signal line 9 via the Taruyama transistor 10, and then read out to the OOD transfer unit 6 via the coupling unit 5.

次の水平走査期間でC0D1を走査して、COD出力部
4よシビデオ信号を得る。
In the next horizontal scanning period, C0D1 is scanned to obtain a video signal from the COD output section 4.

このビデオ信号に然るべき一信号処理を加えて、NTS
O(或いはPAL、或いはSEOAM)標準信号を得る
By adding appropriate signal processing to this video signal, NTS
O (or PAL, or SEOAM) standard signal is obtained.

00D1の転送効率と、垂直信号線9から0OD1への
転送効率を上げるためにバイアス電荷を用いるのが有効
である。このバイアス電荷はCOD入力部よシ注入する
It is effective to use bias charges to increase the transfer efficiency of 00D1 and the transfer efficiency from the vertical signal line 9 to 0OD1. This bias charge is injected from the COD input section.

第2図は0OD1の入力部お動作を説明する図であシ、
2相埋込みチャンネルCODを例にとっている。(α)
が断面構造図で、21がル型キパン、22がP型ウェル
、26がル型拡散層、24が例えばボッシリコンから収
るゲートである・Φ)がポテンシャル図で、水平位置は
(α)の断面構造図に対応させてある。斜線で示した6
10部分は負電荷を表わしている。(C)が駆動パルス
のタイミングチャートである。1it2 t3のタイミ
ングにおけるポテンシャル図を(b)に示している@こ
の図から明らかなように、IsゲートとIGゲートのポ
テンシャル差にISゲート容量を乗じた電荷が、バイア
ス電荷としてCODに注入される。この電荷注入法はポ
テンシャル平衝法と呼ばれ、層も安定な電荷注入法とさ
れている第3図は0CD1の出力部の動作を説明する図
で、同じく2相埋込みチャンネルCODを例にとってい
る。(α)が断面構造図で、25がル型拡散j−126
,27がM OS トランジスタ、28が抵抗である。
Figure 2 is a diagram explaining the operation of the input section of 0OD1.
A two-phase buried channel COD is taken as an example. (α)
is a cross-sectional structure diagram, 21 is a square hole, 22 is a P-type well, 26 is a square diffusion layer, and 24 is a gate made of, for example, bosilicon. Φ) is a potential diagram, and the horizontal position is (α). This corresponds to the cross-sectional structure diagram of . 6 shown with diagonal lines
The 10 portion represents a negative charge. (C) is a timing chart of drive pulses. The potential diagram at the timing of 1it2 t3 is shown in (b).@As is clear from this diagram, the charge obtained by multiplying the potential difference between the Is gate and the IG gate by the IS gate capacitance is injected into the COD as a bias charge. . This charge injection method is called the potential equilibrium method, and it is said to be a charge injection method that is stable in layers.Figure 3 is a diagram explaining the operation of the output section of 0CD1, also using a two-phase buried channel COD as an example. . (α) is a cross-sectional structure diagram, 25 is a Le-type diffusion j-126
, 27 are MOS transistors, and 28 is a resistor.

トランジスタ26は出力部拡散層25の電位をリセット
するだめのトランジスタで、トランジスタ27と抵抗2
8はフローティングゲートのソースホロ7型出力アンプ
を形成しているの)がポテンシャル図で、水平位ll1
lt、は(a)の断面構造図に対応させである。(C)
が駆!iυパルスのタイミングチャートである。
The transistor 26 is a transistor used to reset the potential of the output diffusion layer 25, and the transistor 27 and the resistor 2
8 forms a floating gate source Holo 7 type output amplifier) is the potential diagram, and the horizontal level ll1
lt corresponds to the cross-sectional structure diagram in (a). (C)
Drive! It is a timing chart of iυ pulse.

さて以上説明した従来のOp D形撮像装置では低周波
雑音が発生し感度を制限している・この雌性はモニタ画
面上では横引きもしくはフリッカ状の雑音となる。
Now, in the conventional Op D type imaging device described above, low frequency noise is generated and the sensitivity is limited.This noise becomes sideways drawing or flicker-like noise on the monitor screen.

第4図はOJ) D形撮惺装置哲のランダム雑音スペク
トラムの一例である。嶋い周波数ではほぼフラットなス
ペクトラムであるのに対し、低い周波数ではほぼ1/f
(パワースペクトル密度が周波数に反比例する)のスペ
クトラムを示す。
Figure 4 is an example of the random noise spectrum of the OJ) D-type camera. The spectrum is almost flat at low frequencies, while it is almost 1/f at low frequencies.
(power spectral density is inversely proportional to frequency).

前者は主として結合部5で発生するのに対し、後者は主
としてCODの入力部2と出力部4で発生する。
The former mainly occurs at the coupling section 5, while the latter mainly occurs at the input section 2 and output section 4 of the COD.

一般にMOS)ランジスタの1/f雑音は、チャンネル
中のトラップの影響で発生し、等測的にトランジスタの
ゲートに1/rのスペクトラムを持った雑音電圧源を挿
入した回路で表現される。これをCODの入力部に応用
すると、第2図でIsゲートのポテンシャルが1/fの
スペクトラムで揺らぐことになり、注入する/(イアス
ミ荷が1/fのスペクトラムで揺らぐ1、又、出力部に
応用すると、MOS)ランジスタ27のゲートが17f
のスペクトラムで揺らいでこの揺らぎはそのまま出力さ
れる。
Generally, 1/f noise in a MOS transistor is generated due to the effect of traps in the channel, and is expressed by a circuit in which a noise voltage source with a 1/r spectrum is isometrically inserted into the gate of the transistor. When this is applied to the input section of COD, the potential of the Is gate fluctuates with a spectrum of 1/f as shown in Figure 2, and the injected/(Iasumi charge fluctuates with a spectrum of 1/f). When applied to MOS), the gate of transistor 27 is
This fluctuation is output as is.

このような1/f雑音(低周波雑音)は視覚的に目立ち
やすく、画質を太きく損ねる・〔発明の目的〕 本発明の目的は、前記した低周波雑音を抑圧し感度を向
上した固体撮像装置を提供することにある。
Such 1/f noise (low frequency noise) is visually noticeable and seriously impairs image quality. [Object of the Invention] The object of the present invention is to provide a solid-state image sensor that suppresses the above-mentioned low frequency noise and improves sensitivity. The goal is to provide equipment.

〔発明の概要〕 本発明の要点は、CCD1の出力信号中に、C0D1の
みを転送してきたバイアス分だけから成る部分(以下0
0Dたれ流し信号と呼ぶ)を設け0OD1の出力信号と
CODたれ流し信号との差をとることによシ、低周波雑
音を抑圧することにある、低周波雑音抑圧の様子を第5
図に模式的に示す。第5図(α)は0OD1の出力信号
例で、ビデオ信号の合間にOODたれ流し信号があシ、
これらが大きな低周波雑音で変調されている様子を誇帳
して示している。
[Summary of the Invention] The main point of the present invention is that a portion (hereinafter referred to as 0
The low frequency noise is suppressed by providing a 0D overflow signal (called a 0D overflow signal) and taking the difference between the 0OD1 output signal and the COD overflow signal.
Schematically shown in the figure. Figure 5 (α) is an example of the output signal of 0OD1, where there is an OOD overflow signal between the video signals,
It shows off how these are modulated with large low-frequency noise.

同図(b)は、本発明の方法によ#)00D1の出力信
号からCODたれ流し信号を差引いたときの信号波形例
であり、低周波雑音が艮く抑圧されているのが判る0本
方法は光学黒(ホトダイオードを黒フィルタでおおった
部分)による直流再生法と良く似ているが、光学黒は結
合部で発生するランダム雑音を含むため、CODたれ流
し信号に比べ、クランプエラーもしくは引算によるラン
ダム雑音増加が大きい。
Figure (b) is an example of a signal waveform when the COD overflow signal is subtracted from the output signal of 00D1 using the method of the present invention, and it can be seen that low frequency noise is significantly suppressed using the 0 line method. is very similar to the DC regeneration method using optical black (a photodiode covered with a black filter), but since optical black includes random noise generated at the coupling part, it is less likely to be caused by clamp error or subtraction than the COD feed signal. Large increase in random noise.

〔発明の実施例〕[Embodiments of the invention]

第6図〜第8図を用いて本発明の詳細な説明する。 The present invention will be explained in detail using FIGS. 6 to 8.

第6図は、本発明の一実施例の固体撮像装置のCOD出
力信号を模式的に示した図である。
FIG. 6 is a diagram schematically showing a COD output signal of a solid-state imaging device according to an embodiment of the present invention.

斜線で示した部分がCODたれ流し信号でありル画素の
ビデオ信号の直後に位置する。水平走査期間(T 1)
にル画素の信号を転送した後もCO’Dの転送を続ける
ことによシ、図に示すようにCODだれ流し信号を得る
。水平帰線期間のうち、CODたれ流し信号を得る期間
(72)以外の期間(? 3)で、垂直MO8)ランク
2夕10及び結合部5を動作させ、指定のラインのビデ
オ信号をCODに転送する。
The shaded area is the COD feed signal and is located immediately after the video signal of the second pixel. Horizontal scanning period (T1)
By continuing to transfer the CO'D even after the signals of the pixels have been transferred, a COD overflow signal is obtained as shown in the figure. During the horizontal retrace period, during the period (? 3) other than the period (72) for obtaining the COD feed signal, operate the vertical MO8) rank 2/10 and the coupling unit 5 to transfer the video signal of the specified line to the COD. do.

第7図は本発明の他の一実施例を示し、(α)が00D
出力信号を模式的に示す図である。
FIG. 7 shows another embodiment of the present invention, in which (α) is 00D
FIG. 3 is a diagram schematically showing an output signal.

斜線で示した部分がCODたれ流し信号でありル画素の
ビデオ信号の直前に位置する。このCODたれ流し信号
を得るために、(b)に示すようにOOD 41の転送
部を長く設計する。1ステージで1画素の信号を転送す
るCODの場合、m画素分のOODたれ流し信号を得る
ためには、00 D 41の出力側のmステージを結合
部5と接続させない、第7図の実施例が第6図の実施例
に比べて優れている点は、低域通過フィルタを通した時
にビデオ信号の応答がCODたれ流し信号に影響しに<
<、信号処理が容易になることである。
The shaded portion is the COD feed signal and is located immediately before the video signal of the second pixel. In order to obtain this COD flow signal, the transfer section of the OOD 41 is designed to be long as shown in (b). In the case of a COD that transfers one pixel signal in one stage, in order to obtain OOD overflow signals for m pixels, the embodiment shown in FIG. is superior to the embodiment shown in FIG. 6 because the response of the video signal does not affect the COD overflow signal when it passes through a low-pass filter.
<The signal processing becomes easier.

第8図は本発明の他の一実施例を示し、(α)が00D
出力信号を模式的に示す図である・斜線で示した部分が
CODだれ流し信号であシビデオ信号と交互に出力させ
る。このようなCOD出力信号得るためには([))に
示すようにC0D 42を1ステージおきに結合部に接
続する。
FIG. 8 shows another embodiment of the present invention, in which (α) is 00D
This is a diagram schematically showing an output signal. The shaded part is a COD overflow signal, which is output alternately with a video signal. In order to obtain such a COD output signal, the COD 42 is connected to the coupling section at every other stage as shown in ([)].

この実施例が、第6図、第7図の実施例に比べて優れて
いる点はCODたれ流し信号の分布が密であることで、
このように一画素ごとに分布させると横びき雑音はほぼ
完全に抑圧することができる。
The advantage of this embodiment over the embodiments shown in FIGS. 6 and 7 is that the distribution of the COD overflow signal is dense.
When distributed pixel by pixel in this way, horizontal noise can be almost completely suppressed.

00D出力ビデオ信号とCODたれ流し信号との差をと
る回路は公知であるが、第9図と第10図に一例を示す
A circuit that takes the difference between the 00D output video signal and the COD feed signal is well known, and an example is shown in FIGS. 9 and 10.

第9図はクランプ回路の一例で、51が信号入力端子、
52が信号出力端子、56がクランプ 〔パルス入力端
子、54〜56が抵抗、5758がコンデンサ、59.
60がトランジスタ、61がダイオード、6265が電
圧源である。クランプノくルスとして、CODたれ流し
信号の期間に)飄イレペルとなるパルスを用いる。CO
Dたれ流し信号の期間ではトランジスタ60が導通し、
トランジスタ59のベースではCODたれ流し信号の期
間ごとに所定の電圧(電圧源62の電圧)にリセットさ
れ、第5図に示!〜たように低周波雑音を抑圧すること
ができる。
Figure 9 shows an example of a clamp circuit, where 51 is a signal input terminal;
52 is a signal output terminal, 56 is a clamp [pulse input terminal, 54 to 56 are resistors, 5758 is a capacitor, 59.
60 is a transistor, 61 is a diode, and 6265 is a voltage source. As a clamp pulse, a pulse that causes a sudden drop (during the period of the COD flow signal) is used. C.O.
During the period of the D-driving signal, the transistor 60 is conductive;
The base of the transistor 59 is reset to a predetermined voltage (the voltage of the voltage source 62) every period of the COD flow signal, as shown in FIG. - Low frequency noise can be suppressed.

第10図は減算回路の一例で、71が信号入力端子72
が信号出力端子、7374がサンプリングパルス入力端
子、75が差動アンプ、7677がサンプルホールド回
路である。76でビデオ信号をサンプルホールドし、7
7でCODたれ流し信号をサンプルホールドして、差動
アンプ75で両者の差をとる。816図、第7図の実施
例ではビデオ信号用のサンプルホールド回路76は不要
であるO 発明の効果〕 本発明の効果の一例を第11図に示す・第11図は水平
周期でCODだれ流し信号を設けてこの信号でクランプ
した場合のランダム雑音のパワースペクトル密度の一例
である。破線はクランプしない場合のパワースペクトル
密度であシ本発明によシ低周波雑音が大幅に抑圧できて
いる。
FIG. 10 shows an example of a subtraction circuit, and 71 is a signal input terminal 72.
is a signal output terminal, 7374 is a sampling pulse input terminal, 75 is a differential amplifier, and 7677 is a sample hold circuit. Sample and hold the video signal at 76,
7 samples and holds the COD feed signal, and a differential amplifier 75 calculates the difference between the two. In the embodiments shown in FIGS. 816 and 7, the sample and hold circuit 76 for video signals is not required. Effects of the Invention An example of the effects of the present invention is shown in FIG. 11. This is an example of the power spectrum density of random noise when a signal is provided and clamped with this signal. The broken line shows the power spectral density when no clamping is performed.Low frequency noise can be significantly suppressed by the present invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は従来例の固体撮像装置の説明図、第4
図は低周波雑音を説明するだめの線図、第5図は本発明
の詳細な説明図、第6図〜第10図は本発明の一実施例
の説明図、第11図は本発明の効果を示す線図である。 5・・・・・・結合部 10・・・・・・垂直MOSトランジスタ41・・・・
・・C0D 51・・・・・・信号入力端子 52・・・・・・信号出力端子 63・・・・・・電力源 ;t1 図 第2図 (2) CG) L、て21−3 →B″を塚1 t3図 (b) CG) t、t2−+昨閏 、?4図 周液数(HX) 才5図 (α) オ6図 オフ図 (α) i←I水千水平二 →El!間 (1)) 才8図 (0L) (b) f7図 ;f lo図 才11図 用液(欠(Hz)
Figures 1 to 3 are explanatory diagrams of conventional solid-state imaging devices;
The figure is a diagram for explaining low frequency noise, Figure 5 is a detailed explanatory diagram of the present invention, Figures 6 to 10 are explanatory diagrams of an embodiment of the present invention, and Figure 11 is an explanatory diagram of an embodiment of the present invention. It is a line diagram showing an effect. 5...Coupling section 10...Vertical MOS transistor 41...
...C0D 51...Signal input terminal 52...Signal output terminal 63...Power source; t1 Figure 2 (2) CG) L, te21-3 → B'' mound 1 t3 figure (b) CG) t, t2- + last leap, ?4 figure circumferential liquid number (HX) year 5 figure (α) O6 figure off figure (α) i←I water thousand horizontal two →El! period (1)) 8th figure (0L) (b) f7 figure; f lo figure 11th figure liquid (missing (Hz)

Claims (1)

【特許請求の範囲】[Claims] 1、二次元に配列された光電変換素子群と、該光電変換
素子をスイッチングする垂直スイッチ群と、それぞれ複
数個の上記垂直スイッチを介して、複数個の光電変換素
子と接続する複数の垂直信号線と、信号電荷を水平方向
に転送する電荷結合素子と、上記複数の垂直信号線と上
記電荷結合素子とを結合する結合部とを有す固体撮像装
置において、上記電荷結合素子の中だけを転送されて出
力される電荷レベルを周期的に検出する手段と、上記電
荷結合素子の出力電荷レベルから上記電荷レベルを差引
く手段を設けて低周波雑音を抑圧することを特徴とする
固体撮像装置。
1. A group of photoelectric conversion elements arranged two-dimensionally, a group of vertical switches for switching the photoelectric conversion elements, and a plurality of vertical signals connected to the plurality of photoelectric conversion elements via the plurality of vertical switches, respectively. a charge-coupled device that transfers signal charges in the horizontal direction, and a coupling portion that couples the plurality of vertical signal lines and the charge-coupled device; A solid-state imaging device characterized in that low frequency noise is suppressed by providing means for periodically detecting the charge level transferred and output, and means for subtracting the charge level from the output charge level of the charge-coupled device. .
JP58194293A 1983-10-19 1983-10-19 Solid-state image pickup device Pending JPS6086976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58194293A JPS6086976A (en) 1983-10-19 1983-10-19 Solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58194293A JPS6086976A (en) 1983-10-19 1983-10-19 Solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPS6086976A true JPS6086976A (en) 1985-05-16

Family

ID=16322180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58194293A Pending JPS6086976A (en) 1983-10-19 1983-10-19 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPS6086976A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61242182A (en) * 1985-04-15 1986-10-28 ゼネラル・エレクトリック・カンパニイ Camera

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61242182A (en) * 1985-04-15 1986-10-28 ゼネラル・エレクトリック・カンパニイ Camera

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