JPS6086626A - Program instruction address designating method of instruction processing device - Google Patents

Abstract

PURPOSE:To indicate immediately a jump destination address satisfying conditions by providing a jump destination table and changing and designating the lower bit of the jump destination address having plural branch destinations. CONSTITUTION:If external interrupt conditions are required on the way of execution of a normal program processing and these conditions are an external interrupt signal (a), a table selecting circuit 5 selects a jump destination table 6 corresponding to the signal (a). The table y sets the signal (a) to ''0'' and sends it to a selecting circuit 7. The circuit 7 converts a jump destination address AAAA consisting of 4 bits to an address AAA0 and designates this address AAA0. When this address is indicated by a program counter circuit PC3, an instruction memory circuit IM1 discriminates the jump destination address, namely, a data transmission processing instruction to execute a processing program. Thus, the jump destination address satisfying conditions is indicated immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an instruction processing device that has a storage section that stores a built-in program and a program counter that indicates the address of the storage section, and particularly relates to an instruction processing device that has multiple branch destinations. The present invention relates to a program instruction addressing method in an instruction processing device for selectively specifying the address of a jump instruction.

(b) Background of the Technology When one process is performed using instructions from a built-in program, the process is normally performed in accordance with the order of execution of the built-in program. However, if a condition is added during the instruction processing process, the program may escape from the normal execution order, jump to the program address specified by the five conditions, and execute the instruction.

As the processing conditions become more complex, the number of times jump instructions are processed increases, and efficient jump instruction processing influences the overall processing efficiency.

As a method for efficient jump instruction processing.

Various methods for efficiently selecting and specifying jump destination addresses have been studied.

<c> Prior Art and Problems A method of specifying a jump destination address in conventional program processing will be described with reference to the drawings, taking as an example a method of specifying a jump destination address in a communication control device.

FIG. 1 shows a method of specifying a jump destination address in a conventional communication control device, with (A) showing a circuit diagram and (B) showing an operation diagram.

In the figure, 1 is an instruction memory circuit (hereinafter abbreviated as group), 2 is an instruction register circuit (hereinafter abbreviated as IR), and 3 is a program counter path (hereinafter abbreviated as IR).
(hereinafter abbreviated as PC), 4 indicates a plus 1 circuit, respectively.

Note that ST-1 to ST-n in FIG. 1(B) indicate step numbers for determining the jump destination address, and the order of each step is specified by the built-in program.

FIG. 1 shows an IMI that stores program instructions for controlling a communication control device (not shown), an IR2, and an IMI that retrieve and hold program instructions to be read next from the IMI.
It is composed of a PC 3 that instructs the program instruction address stored in the MI, and a plus 1 circuit that advances the program instruction address one by one in accordance with the normal processing process.

In the communication control device (not shown) of this example, during normal processing without a jump request, program instructions are executed one by one according to the IMI execution order. During this processing process, if an interrupt request is made to the normal processing process due to an external condition connected to the communication control device (not shown), it will be processed sequentially according to the interrupt processing routine shown in Figure 1 (B). do.

The interrupt handling routine shown in FIG. 1(B) also performs processing according to the processing order of certain steps (ST-1 to ST-5T-n), so for example 5T-n is shown in the example of FIG. 1(B).
When there is an interrupt request for "internal interrupt word processing" in order n, a certain number of steps (ST -1 to ST
-n) to reach 5T-n, there is a drawback that it takes time to scan the request until the necessary jump destination address is specified.

(d) Object of the Invention The object of the present invention is to provide a method of addressing program instructions in a new instruction processing device that eliminates the above-mentioned drawbacks. A program for an instruction processing device that can immediately reach a jump destination address that meets the conditions by simply changing the lower bits of a jump destination address that has multiple branch destinations, without going through the processing process described above. The objective is to realize an instruction addressing method.

(e) Structure of the Invention The present invention provides an instruction processing device having a storage unit that stores a built-in program and a program counter that indicates an address of the storage unit, when executing a jump instruction that has a plurality of branch destinations when executing the built-in program. and an address table for selectively specifying a part of the jump instruction addresses with the plurality of branch destinations under predetermined conditions, and the part of the jump instruction addresses selected in the address table is sent to the program counter. This is achieved by a program instruction addressing method in an instruction processing device, which is characterized in that it is possible to immediately reach a predetermined jump destination address by replacing the lower bits of a jump instruction address specified by . I can do it.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 shows an embodiment of the instruction processing device according to the present invention.
A) shows a circuit diagram, and (B) shows a processing flow.

In the figure, 5 represents a table selection circuit, 6 represents a jump destination table, and 7 represents a selection circuit.

The same numbers as in Fig. 1 indicate the same contents, and ■.

■,■ are the contents of the address specified by PC3 (command word)
In the figure, ■ indicates an instruction type specification section, ■ indicates an instruction condition specification section, ■ indicates a jump destination address specification section, and a-n indicate an external interrupt signal, respectively.

The present embodiment shown in FIG. 2(A) has the IMI 1+72. A table that determines the lower bits of the jump destination address from the PC 3, plus 1 circuit 4, an external interrupt signal (a-n) caused by external conditions connected to the instruction processing device, and an internal interrupt signal caused by the internal conditions of the instruction processing device. Table selection circuit for selecting 5. A jump destination table 6 determines and outputs the lower bits of the jump destination address according to the table selected by the table selection circuit 5, and specifies an output from the jump destination table 6 or a jump destination address specified in advance in a built-in program. It is composed of a selection circuit 7 which selects the program instruction according to the instruction type (2) of the program instruction.

In this embodiment, the jump destination address consists of 4 bits and nodes, and the number of bits to be replaced according to the 9 interrupt classification is the lower 1 bit, and the jump destination address code for normal jump processing specified in the built-in program. is A
AAA'. Further, in the case of this embodiment, the jump destination address code of jump processing by the external interrupt signal (a-n) is 'AAAO°-'AAAn'. AAAO' to 'AAAn' shown in FIG. 2(B) indicate the jump destination address code and the processing program corresponding to the address code.

Next, the operation of this embodiment will be explained based on FIG.

2. When an external interrupt condition becomes necessary while executing normal program processing, and the external interrupt condition is external interrupt signal a, the table selection circuit 5 selects the jump destination corresponding to external interrupt signal a. Select table 6. The selected jump destination table 6 outputs the external interrupt signal a as "0" to the selection circuit 6. The selection circuit 6 learns from the instruction type of the program instruction that the jump destination address is currently being determined by an external interrupt, and selects the jump destination address "AAAA" consisting of 4 bits.
Convert ' to AAAO'.

If the jump destination address is determined by the built-in program, "AAAA" is directly indicated by the PC 3.

Convert the specified jump destination address to “AAAO”
When instructed by C3, the IMI determines that it is a jump destination address ``AAAO'', that is, a ``data transmission processing instruction'', and captures and executes the processing program.

The above example describes an example of determining a jump destination address by an external interrupt, but the process of determining a jump destination address by an internal interrupt is carried out in a similar manner. That is, as shown in FIG. 2(B),
A predetermined jump destination instruction address can be immediately specified by simply changing the least significant bit of the jump destination address.

(g) Effects of the Invention According to the present invention as described above, it is possible to provide an address specification method that can immediately specify and reach a jump destination address according to the classification of an interrupt of an instruction processing device.

[Brief explanation of drawings]

FIG. 1 shows a method of specifying a jump destination address in a conventional communication control device, and FIG. 2 shows an embodiment of an instruction processing device according to the present invention. In the figure, 1 is TM, 2 is II? , '3 is I'C,
4 is a plus 1 circuit, 5 is a table selection circuit, 6 is a jump destination table, and 7 is a selection circuit.

Claims (1)

[Claims] In an instruction processing device having a storage unit that stores a built-in program and a program counter that indicates an address of the storage unit, when executing the built-in program, a jump instruction with a plurality of branch destinations and a jump instruction with the plurality of branch destinations are executed. and an address table for selectively specifying a part of the instruction address under predetermined conditions, and the part of the jump instruction address selected in the address table is transferred to the lower part of the jump instruction address specified by the program counter. A method for specifying address of a program instruction in an instruction processing device, characterized by replacing the address with a bit.