JPS608638B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor circuit used as a memory device.

The ideal function of a storage device is that information can be written and retrieved at high speed and that the information is non-volatile.

Conventionally, a semiconductor memory device using a floating gate type or double insulating film gate type field effect transistor requires a writing time t of 1 microsecond to 1 millisecond per bit, and a large capacity memory device requires N bits. A writing time of N·t was required to write. Such a memory device is not only not ideal, but also has defects in general-purpose functions, and has many disadvantages in realizing an economical semiconductor memory device with increased mass productivity. An object of the present invention is to provide a semiconductor memory device having general-purpose functions.

Another object of the present invention is that information can be written and retrieved at high speed similar to conventional random access memory devices (RAM), and stored information can be held in a non-volatile manner. An object of the present invention is to provide a semiconductor memory device.

According to the present invention, memory cells each comprising a flip-flop circuit are arranged at matrix intersections formed by a plurality of row lines and a plurality of column lines, and the row lines and column lines are selected and transferred to a predetermined memory cell. In the memory device for transmitting and receiving information, at least one of the drive transistors of the flip-flop circuit is a memory transistor having a function of capturing and accumulating charges in a gate insulating film. It will be done.

In the memory device of the present invention, since the memory cells are constituted by flip-flop circuits, it is possible to write and output information as a RAM at high speed.

Furthermore, since the drive transistor has a charge storage function, the information held by the flip-flop circuit during a write operation can be stored in a nonvolatile manner. The time required for this non-volatile storage is as described below, because it is performed simultaneously with other memory cells, so even in large-capacity storage devices, the total bit writing time is short, about 1 microsecond to 1 millisecond. Complete. Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures. FIG. 1 shows a circuit diagram of an embodiment of the present invention. This embodiment includes a plurality of pairs of row lines D,,D,,D2,D2 and a plurality of column lines W,,W2.
Flips, which will be described later, are applied to the matrix intersections formed by and. Memory cells M, . ,M,2,M
2,, Earth 2 is placed. Row lines D,,D, and,D
2 and D2 are mutually complementary signal lines, and contribute to transmitting and receiving complementary signals with the memory cells. FIG. 2 is a circuit diagram of the memory cell of the embodiment shown in FIG.

In this embodiment, two drive transistors Q whose gates are connected to each other's drains and whose sources are coupled to a common ground terminal. ．． ,Q. 2 and each drive transistor Qo,,Q
As load elements of o2, two load transistors QL, ? whose sources and drains are coupled to the drain of the drive transistor and the power supply terminal Vo, respectively, and whose Kents are commonly connected to the Kent terminal Vc, are used as load elements of o2. Flip with QL2.

A flop circuit is configured. In addition, one of the drains and sources of the respective coupling transistors QT, Qr2 is coupled to the drain of the driving transistor QD, y Qo2, which is a contact point for transmitting and receiving input/output signals, and the other is connected to the row line D,
Each binds to D. This coupling transistor QT,,
The gates of QT2 are commonly connected to column line W. The body gate of each transistor is the same body terminal SB. Drive transistor Qo,? The gate structure of Qo2 includes a floating gate, and low breakdown voltage diodes D, D2 that affect this floating gate are provided at least in part of the drain junction. The anode of this diode is the base terminal SB. FIG. 3 is a cross-sectional view illustrating the drive transistor and low voltage diode shown in FIG. 2.

These circuit elements are preferably formed using a thick silicon layer on one surface of a P-type silicon single crystal substrate 301 with a specific resistance of 40 mm.
02 is formed in an active region surrounded by a peripheral oxide film 302. The surface of the substrate in the active area has a surface concentration of approximately 1 pi 1 skin-3,
N-type source and drain region 303 with junction depth 2〆
, 304, and 300A on the substrate surface between these areas.
A floating gate 306 made of polycrystalline silicon is provided through a Si02 film 305 of approximately 100 mL. The floating gate 306 is further insulated with a Si02 film 307 with an effective thickness of 2000A to prevent circuit conductive coupling, and the Si02 film 307
It has a capacitive coupling with the aluminum gate 308 via. Therefore, this gate structure includes a gate insulating film made of two layers of insulator between the gate 308 and the substrate surface of the active region;
A so-called M having a floating gate embedded in a gate insulating film
It is an OSOS structure. Drain region 304 is connected to base body 301
A PN junction is formed between the floating gate and the floating gate, but there is a poron acceptance region 309 with a surface concentration of about 1p7-3 directly below the floating gate, and a PN junction with a junction withstand voltage of about 14V is formed at the junction with this.
A junction diode is formed. Compared to the original drain junction breakdown voltage of about 30V, this serves as a low breakdown voltage diode. FIG. 4 is a characteristic diagram showing the operation of the transistor of the MOSOS structure shown in FIG.

The vertical axis of this figure shows the gate threshold value VT of the transistor as a value measured with drain voltage=5V and base potential=source potential=OV, and the vertical axis shows drain voltage Vo or base potential VsB. The transistor shown in Fig. 3 initially shows a gate threshold value of approximately IV, and when the gate voltage value is measured after applying a predetermined base potential VsB for 1 millisecond, the broken line 4
1, it shows a tendency to increase as the absolute value of the negative substrate potential VsB increases. The base voltage that starts to increase is from the breakdown point of the PN junction diode, and is thought to be due to negative charge accumulation due to electron injection during avalanche breakdown. In addition, the increased gate function value can be determined by applying a -5V body bias to the substrate and applying the drain voltage Vo for 1 millisecond and then measuring the gate function value in the same way, as shown by the solid line 42 in the figure. Decrease the value VT. This decrease in gate darkness value is thought to be due to negative charge dissipation from the floating gate due to the contribution of holes due to avalanche breakdown of the PN diode. These changes in the gate threshold value largely depend on the gate electric field at the time of avalanche breakdown, and when a positive voltage is applied to the gate electrode during negative charge accumulation, the increase in the gate threshold value increases by the applied voltage value.

Furthermore, when the negative charge disappears, the gate threshold value is prevented from decreasing by the voltage value of the positive voltage applied. In a flip-flop circuit, one drive transistor increases or decreases the gate function value clearly more than the other, and when both drain voltages are OV, the gate function values are the same. FIG. 5 shows an example of operating waveforms of the embodiment shown in FIGS. 1 to 4.

In the initial stage, the embodiment of FIG. 1 performs normal static type RAM operation, holds the information introduced at tw during writing, and applies a drop signal to the row line at tR during reading. Transmission and reception of these information is carried out by applying a column line voltage Vw, a row line voltage Vo, a gate voltage VG of the load transistor, and a base voltage VsB as shown in the figure while a drain power supply voltage of 20V is applied. After information has been introduced into all bits in the storage device, if it is desirable to fix the information in a non-volatile manner due to a power outage or if necessary, the gate voltage Vc is increased and the base voltage is decreased on the t side during non-volatile writing. As a result, the gate threshold values of the drive transistors each having a low gate voltage in the flip-flop circuits of all bits are reduced, and unbalance is restored in the flip-flop circuits after the power is cut off.
That is, in the flip-flop circuit after the power is turned on again, the drive transistor whose gate function value has decreased is always in a conductive state, and at the time of reading, at tR', an output that is inverted from that before non-volatile writing is sent to the row line. give. Since this state is a fixed memory operation, ROM operation is performed regardless of the presence or absence of the power supply, and the RAM is reused.
Returning to operation is performed by lowering the substrate voltage to -20V at tER during erasing. This erasing operation can also be performed on all bits in the memory device at once, and only the transistors whose gate thresholds in the flip-flop circuit have decreased have a positive voltage applied to their gate electrodes, effectively reducing the gate threshold value. It rises to match the characteristics of the other transistor, restoring the original RAM function. FIG. 6 shows another operational waveform diagram of an embodiment of the present invention.

In the voltage application shown in this figure, only the base voltage VsB is lowered from OV to -20V at tNw' during nonvolatile writing following RAM operation. According to this voltage manipulation, only the drive transistors in the conductive state inside the flip-flop circuit of all bits increase the gate threshold value due to the contribution of the positive gate voltage, and perform an unbalanced flip-flop circuit function. This voltage waveform also shows that each memory cell after non-volatile writing generates an inverted output at tR' during reading, and operates as a fixed memory device.Recovery from the non-volatile writing state is performed under a load similar to that during writing in Figure 5. Increasing the gate voltage of the transistor to increase the drain voltage of the drive transistor to near the power supply voltage value causes avalanche breakdown in the drain junction, and lowering the substrate voltage to remove the drain voltage of the drive transistor whose gate voltage has increased. Predominantly negative charge dissipation occurs to generate flip-flop circuit function. According to these embodiments, a storage device having RAM and ROM functions is obtained.

Also, it is possible to take measures against power outages to the RAM. Furthermore, a storage device that performs nonvolatile writing at high speed regardless of an increase in storage capacity can be obtained. FIG. 7 is a diagram of a detection circuit suitable for the above embodiment.

This detection circuit includes a first flip-flop circuit F/FI using an ordinary insulated gate field effect transistor;
It has a second flip-flop circuit F/F2 having the same circuit configuration as the memory cell, and a gate circuit G. Gate circuit G
are the complementary outputs 71-72, 7 of each flip-flop circuit.
It includes 3-74 AND circuits K, , K2, an inverting circuit 1 that inverts the output of one AND circuit K2, and the sum of this inverted output and the output of the other AND circuit K (or-another circuit). Since the second flip-flop circuit usually drives the first AND circuit K with a reset signal that is instantaneously applied, the information on the output signal lines D and D from the memory circuit section remains unchanged (output). Given. At the same time as non-volatile writing is performed on the memory circuit section, the gate function value of the second flip-flop circuit F/F2 also changes to the drive transistors Qo, Q'o2, and the second AND circuit K2 passes through the signal line 73. Therefore, the information on the output signal line is inverted and led out to the output out, and the read information before and after the original nonvolatile writing can be made the same. FIG. 8 shows another transistor structure of a drive transistor suitable for a memory circuit section according to another embodiment of the present invention.

This transistor does not have a low breakdown voltage diode at the drain junction as compared to the structure shown in FIG. In this structure, negative charges are dissipated through the approximately 1,000-layer Si02 film 801 obtained by thermal oxidation of the polycrystalline silicon on the upper surface of the floating gate 306, and by lowering the substrate voltage, approximately 1 to 6 layers are removed.
Charge recovery occurs from the interruption of the high concentration P-type region 802 into the channel region. FIG. 9 shows the gate threshold value VT-applied voltage Vc, VsB characteristics in the transistor structure of FIG. 8.

As the gate voltage VG increases, the floating gate loses negative charge and enters a positive charge accumulation state, so that the gate threshold value VT decreases as shown by a solid line 91. Furthermore, when the substrate voltage is lowered, the gate darkness value VT shows an increasing tendency, and these are called ion drift type and inversion layer breakdown type characteristics, respectively. Although the writing speed of the transistor of this embodiment is lower, it is advantageous in that the structure is simple, and the information in the normal rotation state can be fixed by a nonvolatile writing operation similar to that shown in FIGS. 6 and 7. I can do it.

That is, since the gate voltage value of the drive transistor in a conductive state with a high gate voltage before writing is lowered by the iondo IJ type effect, information on the conductive state is provided even after non-volatile writing. The memory circuit of this embodiment is exactly the same as that in FIG. FIG. 10 shows a sectional view of a drive transistor suitable for yet another embodiment of the invention.

This embodiment also has the same circuit configuration as that of FIGS. 1 and 2, and uses the transistor shown in FIG. 10 outside of the drive transistor. This transistor also has a normal drain junction, and only the gate structure differs from the previous embodiment. floating gate 306
' is made of semiconductive polycrystalline silicon with no additives, and is covered with an insulating film 1001 having a higher dielectric constant than the Si02 film 305, such as alumina or silicon nitride. Figure 11 shows the gate function value VT - gate voltage V of the transistor in Figure 10.
o or drain voltage Vo.

As shown in this figure, when the gate voltage Vc is increased outside the drive system used in this embodiment, the tunnel injection characteristics shown by a solid line 1101 and the avalanche injection characteristics shown by a broken line are shown. i.e. flip flop. In the circuit, a nonvolatile write operation is performed outside one of the drive transistors in which the gate voltage is high and the gate voltage is high, and the gate voltage falls in a nonvolatile write operation, while the other drive transistor fixes information in an inverted state in which the gate voltage falls. Although this embodiment has the advantage of high efficiency of non-volatile writing, recovery to RAM operation relies on UV irradiation to the floating gate. According to the embodiment described above, all bits are written nonvolatilely at the same time and R
A storage device capable of converting the functions of AM and ROM memories is obtained.

Note that the circuit functions, materials, etc. in the embodiments can be changed as necessary. For example, in addition to the above-mentioned transistors, a depletion type transistor, a reverse conduction channel type transistor, a pure resistor, or a charge pump type element may be used as the load element. Therefore, one of the transistors coupled to the flip-flop circuit can be omitted, and the number of row and column wires in the memory circuit can be reduced.

Other transistor structures that trap charges in an insulated gate film include two-layer insulated gate films with high dielectric constant and low dielectric constant such as MNOS and MAOS, although there is a problem of deterioration of characteristics during recovery of RAM and ROM. Structured transistors may also be used.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a memo IJ cell of an embodiment of the invention, Fig. 3 is a sectional view of the drive transistor of Fig. 2, and Fig. 4 is a circuit diagram of an embodiment of the invention. Fig. 3 is a characteristic diagram of the transistor, Fig. 5 is a voltage waveform diagram of Fig. 1, Fig. 6 is a voltage waveform diagram of another example of Fig. 1, and Fig. 7 is an output theory of the memory circuit of Fig. 1. FIG. 8 is a cross-sectional view of a drive transistor according to another embodiment of the invention, and FIG.
FIG. 11 is a characteristic diagram of the transistor shown in FIG. 10. FIG. In the figure, D,,D2 are row lines, D,,D2 are row lines used as complementary signal lines of D,,D2, W,,W2 are column lines, and Qo
,,Qo2 is a driving transistor with a floating gate structure, QL
,,QL2 is a load transistor, and QT・,QT2 is a coupling transistor. Traditional drawing Traditional drawing 2 drawing Rhizo 3 figure 4 sickle s figure mirror et al figure purple 7 figure surprise 8 figure ta figure Atsushi'o figure nephew, - figure

Claims (1)

[Claims] 1. In a semiconductor device having two driving transistors having a flip-flop configuration and a coupling transistor inserted between each output terminal of the two driving transistors and an output line, At least one of them is composed of a memory transistor that has the function of capturing and storing charge in its gate insulating film, and the driving transistor itself has both functions of writing and reading information and a function exclusively for reading information. Characteristic semiconductor devices.