JPS6084831A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6084831A JPS6084831A JP19167083A JP19167083A JPS6084831A JP S6084831 A JPS6084831 A JP S6084831A JP 19167083 A JP19167083 A JP 19167083A JP 19167083 A JP19167083 A JP 19167083A JP S6084831 A JPS6084831 A JP S6084831A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- impurity
- etching
- layers
- shaped grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体装置の製造方法に関し、特に集積化半
導体装置の能動領域を決定する素子分離領域(フィール
ド領域)形成のだめの、半導体基板への溝の形成に関す
るものである。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular for forming an element isolation region (field region) that determines the active area of an integrated semiconductor device. This relates to the formation of grooves.
(従来例の鑵虚、L−モの闇頚占)
半導体装置の高集積化が進むにつれて、能動領域とフィ
ールド領域の分離工程、いわゆる素子分離工程で、半導
体基板の素子分離領域に相当する箇所にU字形の溝を形
成する方法がよく用いられている。U字形の溝を形成す
る方法としては、反応性イオンエツチングに代表される
ドライエツチングが用いられているが、エツチング速度
のウェハー内の不均一性により、溝の深さがばらつき、
所定の深さの溝を安定して形成することが困難であった
。(Conventional example: 鑵空, L-Mo's dark neck) As the integration of semiconductor devices progresses, in the process of separating the active region and field region, the so-called element isolation process, a portion corresponding to the element isolation region of the semiconductor substrate is used. A commonly used method is to form a U-shaped groove. Dry etching, typically reactive ion etching, is used to form U-shaped grooves, but the depth of the grooves varies due to non-uniformity of the etching rate within the wafer.
It has been difficult to stably form grooves of a predetermined depth.
(発明の目的)
本発明は、素子分離領域の微細化のために、半導体基板
に再現性および制御性良くU字溝を形成することを目的
とするものである。(Objective of the Invention) An object of the present invention is to form a U-shaped groove in a semiconductor substrate with good reproducibility and controllability in order to miniaturize element isolation regions.
(発明の構成)
本発明は、半導体基板の素子分離領域に相当する箇所の
所定の深さに、イオン注入によシネ鈍物層を選択的に形
成し、その後、エツチング処理を施こし、前記不純物層
の深さまでの溝を形成する。(Structure of the Invention) The present invention involves selectively forming a film dulling material layer by ion implantation at a predetermined depth at a location corresponding to an element isolation region of a semiconductor substrate, and then performing an etching process to form the film at a predetermined depth. A trench is formed to the depth of the impurity layer.
この場合、イオン注入で形成された不純物層の工ッチン
グ速度が、半導体基板のエツチング速度に比較して数分
の1以下になることから、半導体基板のエツチングは、
上記不純物層で停止する也とになる。本発明により、半
導体基板に形成されたU字形の溝の深さは、イオン注入
により形成された不純物層の深さで決定され、その均一
性が向上する。In this case, the etching speed of the impurity layer formed by ion implantation is less than a fraction of the etching speed of the semiconductor substrate, so the etching of the semiconductor substrate is
It also stops at the impurity layer. According to the present invention, the depth of the U-shaped groove formed in the semiconductor substrate is determined by the depth of the impurity layer formed by ion implantation, and its uniformity is improved.
(実施例の説明) 以下、実施例を図面に基づいて説明する。(Explanation of Examples) Examples will be described below based on the drawings.
第1図は、本発明の一実施例を示したもので、まず、第
1図(a)に示したように、シリコン基板1上に1ホト
レジスト2からなる所要パターンが形成され、このホト
レジスト2をマスクとして、イオン注入法により酸素イ
オン(0+)が15oKevで7リコン基板1に注入さ
れる。本実施例では、ドースH1,2X 101815
で行なった。このときのグロジェクションレンジ(Rp
)は約04μmでアシ、この結果、第1図(b)に示
したように、仁の深さの領域にSiOx (X≧2)か
らなる0+注入膚3が形成される。この後、ホトレジス
ト2をマスクとして、塩素系ガスを主成分とするガスを
使用したドライエツチングによシシリコン基板lに異方
性エツチング処理を施し、第1図(C)に示したように
0字形溝4を得た。本実施例のエツチング条件下では、
イオン注入により形成されたSiOx層とSiのエツチ
ング速度比は、Si/SiOx ) 10が得られてい
る。FIG. 1 shows an embodiment of the present invention. First, as shown in FIG. 1(a), a required pattern consisting of one photoresist 2 is formed on a silicon substrate 1, and this photoresist 2 is Using as a mask, oxygen ions (0+) are implanted into the silicon substrate 1 at 15oKev by ion implantation method. In this example, the dose H1,2X 101815
I did it. The glojection range at this time (Rp
) has a reed of about 04 μm, and as a result, a 0+ injection skin 3 made of SiOx (X≧2) is formed in the region at the depth of the reed, as shown in FIG. 1(b). Thereafter, using the photoresist 2 as a mask, the silicon substrate 1 is anisotropically etched by dry etching using a gas containing chlorine gas as the main component, resulting in a 0-shape as shown in FIG. 1(C). Groove 4 was obtained. Under the etching conditions of this example,
The etching rate ratio between the SiOx layer formed by ion implantation and Si is 10 (Si/SiOx).
又、このエツチング条件でのSiエツチング速度の均一
性は、ウェハー内で、±5%である。Further, the uniformity of the Si etching rate under these etching conditions is ±5% within the wafer.
第2図は、本実施例のエツチング条件下で、従来法によ
シシリコン基板にU字形溝を形成した場合と、本発明方
法の場合とのウェハー内の溝の深さのばらつきを示した
ものである。これによると、本発明方法によるばらつき
は、従来法のそれに比較して1/10以下であり、測定
誤差の範囲に入る程小さいことがわかる。Figure 2 shows the variation in the depth of the grooves in the wafer when U-shaped grooves are formed in a silicon substrate by the conventional method and by the method of the present invention under the etching conditions of this example. It is. According to this, it can be seen that the variation according to the method of the present invention is 1/10 or less compared to that of the conventional method, and is so small that it falls within the measurement error range.
なお、本実施例では、イオン注入する不純物として酸素
を用いたが、他の不純物、例えば窒素でも可能である。In this embodiment, oxygen was used as the impurity to be ion-implanted, but other impurities such as nitrogen may also be used.
(発明の効果)
以上説明したように、本発明によれば、半導体基板に形
成される溝の深さは、エツチング速度のばらつきに依存
することなく、イオン注入にょシ制御されるため、ばら
つきが非常に小さなものとなり、工程の均一性、安定性
が得られ、半導体装置の品質の向上を図ることができる
。(Effects of the Invention) As explained above, according to the present invention, the depth of the groove formed in the semiconductor substrate is controlled by ion implantation without depending on the variation in the etching rate, so that the variation is reduced. It becomes extremely small, and uniformity and stability of the process can be obtained, and the quality of the semiconductor device can be improved.
第1図は、本発明の一実施例の製造工程を示す断面図、
第2図は、従来法と本発明方法により得られたU字形溝
の深さのばらつきを比較した図である。
1 ・・・・・・・・・7リコン基板、 2 ・曲面
ホトレジスト、3・・・・・・・・・0 注入層、 4
・・・・・・・・・U字形溝。
特許出願人 松下電子工業株式会社
代 理 人 星 野 恒 司 ・・。
第1図
(0)
第2図FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention;
FIG. 2 is a diagram comparing the variation in depth of U-shaped grooves obtained by the conventional method and the method of the present invention. 1 ・・・・・・・・・7 Recon board, 2 ・Curved surface
Photoresist, 3...0 Injection layer, 4
・・・・・・・・・U-shaped groove. Patent applicant: Matsushita Electronics Co., Ltd. Agent: Hisashi Hoshino. Figure 1 (0) Figure 2
Claims (2)
い、前記半導体基板の表面から所定の深さに不純物注入
層を形成する工程と、前記半導体基板の表面からiil
記不純物注入層に至る溝を形成する工程とを含むことを
特徴とする半導体装置の製造方法。(1) selectively implanting impurity ions into a semiconductor substrate to form an impurity implantation layer at a predetermined depth from the surface of the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising the step of forming a trench that reaches the impurity injection layer.
は窒素を用いることを特徴とする特許請求の範囲第(1
)項記載の半導体装置の製造方法。(2) Claim 1 (1) characterized in that oxygen or nitrogen is used as the impurity to be ion-implanted.
) The method for manufacturing a semiconductor device according to item 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19167083A JPS6084831A (en) | 1983-10-15 | 1983-10-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19167083A JPS6084831A (en) | 1983-10-15 | 1983-10-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6084831A true JPS6084831A (en) | 1985-05-14 |
Family
ID=16278500
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19167083A Pending JPS6084831A (en) | 1983-10-15 | 1983-10-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6084831A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01105543A (en) * | 1987-10-19 | 1989-04-24 | Fujitsu Ltd | Manufacture of semiconductor device |
US4997786A (en) * | 1986-06-13 | 1991-03-05 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a semiconductor device having buried insulation layer separated by ditches |
JP2008305870A (en) * | 2007-06-05 | 2008-12-18 | Spansion Llc | Semiconductor device and manufacturing method thereof |
JP2012500475A (en) * | 2008-08-15 | 2012-01-05 | クゥアルコム・インコーポレイテッド | Shallow trench isolation |
JP2013051439A (en) * | 2012-11-26 | 2013-03-14 | Spansion Llc | Semiconductor device and method for manufacturing the same |
CN103247517A (en) * | 2012-02-08 | 2013-08-14 | 郭磊 | Semiconductor structure and forming method thereof |
-
1983
- 1983-10-15 JP JP19167083A patent/JPS6084831A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4997786A (en) * | 1986-06-13 | 1991-03-05 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a semiconductor device having buried insulation layer separated by ditches |
JPH01105543A (en) * | 1987-10-19 | 1989-04-24 | Fujitsu Ltd | Manufacture of semiconductor device |
JP2008305870A (en) * | 2007-06-05 | 2008-12-18 | Spansion Llc | Semiconductor device and manufacturing method thereof |
JP2012500475A (en) * | 2008-08-15 | 2012-01-05 | クゥアルコム・インコーポレイテッド | Shallow trench isolation |
CN103247517A (en) * | 2012-02-08 | 2013-08-14 | 郭磊 | Semiconductor structure and forming method thereof |
JP2013051439A (en) * | 2012-11-26 | 2013-03-14 | Spansion Llc | Semiconductor device and method for manufacturing the same |
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