JPS6080318A - Driver circuit - Google Patents

Abstract

PURPOSE:To attain highly accurate timing accuracy and equalization of propagation delay times of two inputs by making number of logical operation stages equal to each other in a tri-state output driver circuit. CONSTITUTION:When a transistor (TR) T2 is turned on with a signal E at H level, two outputs of a differential amplifier C1 go to an identical level by two diodes D. Moreover, an output of post-stage differential amplifiers C2, C3 goes to the same logical level as D' and one of TRs T14, T15 is turned on depending on the level of the level of L, H of the D'. When the TRT1 is turned on with the signal E at L level on the other hand, although a voltage -VEE is fed to a base of a TRT3 and a voltage V' is fed to a base of a TRT6 respectively, an output of the differential amplifier C2 is always at L, a TRT15 is turned off at all times and the output of the amplifier C3 turns on/off the TRT14 at the same logical level as that of the input D'. Thus, the output is brought into the voltage V1 when the signals E and D' are at (H, H) and (L, H) and the output is brought into a voltage V2 when (H, L) and the output is brought into a high output impedance state when (L, L).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a driver circuit having a tri-state output function.

[Background of the invention]

A driver circuit that outputs a pulse waveform is required to have high speed, high timing accuracy, and a tri-state function, but it is generally difficult to satisfy these items at the same time.

A conventional circuit will be described below with reference to the drawings.

As shown in FIG. 1, the driver circuit having a tri-state function is composed of an output switch circuit 1.2 whose basic circuit is a solid-state switch, and a logic operation section 3 that functionally controls these circuits. .

The ability to have two potentials, high and low, and a high output impedance state in the output state is called tri-state capability, but in order to achieve a high output impedance state, the output circuit needs to be It needs to be in the form of a switch, not in the form of a switch. These switch circuits 1 and 2 generally include bipolar transistors, field effect transistors (
(hereinafter abbreviated as FET), two of these are prepared and connected to high and low voltage sources, respectively, and are alternately turned on and off to change the high and low output states, or both. By turning both off, high output impedance is output. This achieves tri-state functionality.

The logical operation 93 turns ON/O of the above switch circuits 1 and 2.
It is provided to functionally control F'F. A driver circuit with a tri-state function has two input terminals t1: a binary input that specifies two output potentials, high and low; and a binary input that specifies a potential output state and a high output impedance state. Providing t2 is beneficial for the functionality of the driver circuit. This logic circuit section 3 is provided in order to produce, by means of these two inputs, two outputs which control the respective switch circuits 1, 2 of the output section. The switch circuits 1 and 2 include, for example, PN
P) Transistor and NPN) Transistor, Pch, P
ET and Nch.

Complementary elements such as FETs have good characteristics and are common, so the logic operation unit 6 is a combination of logical product, sum, and negation, as shown in FIG. This circuit diagram includes a buffer circuit and a driving interface circuit necessary to match the drive timings of the switches.

Such conventional driver circuits with a tri-state function have problems such as poor output timing accuracy and unequal propagation delay times from two inputs to an output.

The former problem is due to the complexity of the logic operation section 30 circuit. All logic circuits involve propagation delay time and jitter, but in conventional circuits, the signals applied to the input terminals tt and t2 pass through a large number of logic circuit stages before reaching the output section. Variations in propagation delay times and jitter occurring in the stages accumulate and become large, deteriorating the timing accuracy of the driver output.

The latter problem is caused by the fact that in the circuit shown in FIG. 2, the number of circuit stages through which the signal passes differs between the input (2) and the input (@). In the figure, input @ has more circuit stages, so input
tiua is slower than that of input (2), and the control timing cannot be matched. If you want to achieve this consistency, you can do so by adding a buffer circuit to the path of the input Furthermore, since the number of circuit stages in the signal path increases, the former problem increases.

As explained above, conventional circuits have the drawbacks of poor output timing accuracy and unequal propagation delay times from two inputs to an output. The purpose of the present invention is to provide a Draino (circuit) having a tri-state function with high timing accuracy.

[A chest of inventions]

The present invention provides a ternary output having the ability to output two or more of the above six levels from each of two output terminals having a high level, a low level, and a 30th level between the two as output levels. a first differential amplifier, and a second differential amplifier whose input is the output of this first differential amplifier.
a third differential amplifier; The present invention is characterized in that the switching element is controlled by the output of the third differential amplifier.

[Embodiments of the invention]

The problems of timing accuracy and the difference in propagation delay time from two inputs explained in the conventional example are caused by the logic operation section circuit in the driver circuit.

If this part can be realized with a small number of elements and a circuit configuration that is symmetrical with respect to the two inputs so that the propagation delay times from the two inputs are equal, the above problem can be solved.

This can be realized if the circuit configuration of the logic operation section uses multivalued potentials. Conventionally, logic circuits have been constructed with a focus on the binary nature of voltage or current, but by focusing on multi-values and introducing a circuit that simultaneously calculates logical sum, product, and their negation. , the above problems are solved.

FIG. 6 shows a logic gate circuit using multi-value potentials. This circuit basically consists of a differential amplifier. The two differential amplifiers C2 and Cs near the output have a normal circuit configuration found in ECL logic circuits, etc., but the differential amplifier C1 connected to the input ■ has nonlinear characteristics using a diode DI, l)2. These are two types of circuits that use a combination of the circuit shown above and a resistor, and generate a combination of multi-value potentials.

Hereinafter, the circuit operation of the differential amplifier C1 will be explained.

Transistor T5. ．． Ill 6 forms a differential amplifier circuit together with constant current source (2). Diode D2 forms a current path from load resistor R2 to transistor T5. That is, the collector Ichihara of transistor 'r5 is 2
Two load resistors R1 and R2 are driven.

The diode D1 is provided for the purpose of compensating for the forward voltage drop of the diode D2.

Here, if the potential of the input (2) of the transistor T5 is higher than the potential of the pace of the transistor T6, the transistor T
Only transistor T5 conducts, and the collector current of this transistor T5 is equal to or greater than the source voltage VCC and the two load resistances L1. R2 and 2
It is supplied via two diodes D+ and D2. At this time, the two diodes D+, D217)
, two output terminals oT1. An equal potential v1 is obtained at oT2. This state will be called 81.

On the other hand, if the pace 'iJl of the transistor T6 is higher than that of the input
If only the path 2 is connected, the potential of the output terminal OT1 becomes equal to the power supply voltage +Vcc, and the potential of the output terminal OT2 becomes the value V2 obtained by subtracting the voltage drop due to the load resistance R2 and the current I from the power supply voltage Vcc. This state will be called 82.

In state S1, output terminal OT1. The output terminal OT2 has the same potential V1, and in state S2 the two potentials +VCC,
V2, a total of three types of potentials can be obtained. Here, the load resistance R
1, & are the same value, the potential V1 is the potential 0VCC,V
It becomes the arithmetic mean of 2, and the difference between the three potentials (Vcc-Vl)
and (Vl-V2) are equal.

In order to more clearly illustrate the operation of this circuit, the input/output characteristics of this circuit are shown in FIG. The right side of Fig. 4 is state S1.
, and the left side is state S2.

The basic properties of this circuit will be described below.

This circuit is based on a differential amplifier, which is a current circuit, and the active elements operate in the non-saturation region, allowing extremely high-speed operation. Diodes can operate at higher speeds than transistors, and the saturation characteristic of the emitter-collector voltage of a transistor absorbs the transient characteristics of the diode during state transition, contributing to the realization of high-speed operation. The same characteristic also absorbs the forward voltage drop of the diode and
Since the two diodes cancel their voltages with each other, the output potential is determined only by the constant current source I load resistance R+, R2, and the multiple values of the power supply voltage 10 Vcc. Therefore, the output potential is insensitive to changes in the characteristics of diodes and transistors.

Above, this circuit has been explained using a circuit using an NPN type bipolar transistor, but this circuit can be realized by changing the power supply voltage and the polarity of the diode! 1) It can be constructed using a PNP type bipolar transistor, or it can also be constructed using an FET.

- Now, FIG. 3 is a diagram showing a logic operation gate circuit to which the above-mentioned nonlinear differential amplifier C1 is applied.

In the figure, three sets of differential pair transistors are prepared, transistors T1. A differential amplifier circuit with T2 forms a nonlinear differential amplifier according to the invention. In the figure, diodes Ds, D< and transistors T7 to T+o
is provided for level shift for logic level correction,
The logic levels H (high potential side) and L (low potential side) for each person/output are common. Further, the voltage source E has a potential midway between levels H and L.

When level H is applied to input ■, nonlinear differential amplifier C1
outputs a signal V1 equal to the load resistance R1°R24 in the state aQst described above. At this time, if the circuit constants are set so that the potential V1 is an intermediate potential between the logic levels H and L, the differential amplifiers C2 and C5 consisting of the transistor pairs Tl, T2 and Ts, T4 will have outputs 0 to ■. Each outputs a signal with the same logic level as human power ■.

Furthermore, when level L is applied to input ■, nonlinear differential amplifier dc1 enters the above-mentioned state S2, and its output potential becomes two, Vcc and v2, but here Vcc is higher than level H. If circuit constants are selected so that , V2 has a potential lower than the level L, the outputs (1) to (2) will have the levels shown in FIG. 5, depending on the logic level of the input (2).

That is, the logic of the output (2) is the logical product of the signals of the inputs (2) and (2), and the logic of the output (2) is the logical sum of the inversion of the signal of the input (2) and the signal of the input (2). Also, in the figure, transistors T2 and Ts
Outputs @ and ■ from the collector electrodes obtain the logic of negation of outputs ■ and ■, respectively.

The relationship between the potentials of the outputs of the two multi-value generating circuits on the input side of the tab is shown in Figure 5.The output '1' of each output is compared by the subsequent differential amplifiers CI and C2, and the logic gate In the circuit shown in Figure 3, for the input signals A and B of the inputs ■ and ■ in the figure, the outputs ■l e I■, ■ +[, A
-11, A-H, A-1-8°.

FIG. 6 shows a driver circuit having a tri-state function with high speed and high timing accuracy, which is constructed by introducing a logic gate circuit using this multi-level potential.

Transistors TI, T2 . of the logic operation section of this circuit. ,,
Tl.

T4. Ts and T6 are transistors T in the circuit diagram of FIG.
s, T6. Tl, T2, Ts, T4 K compatible site.

Transistor T7 in this circuit. T8 is the output part, the slave circuit is female, and the transistor TA2. T13 is a constant current circuit, and transistors Tp and T+o are provided to turn on and off this constant current circuit. The same operation as in the block diagram of this circuit shown in FIG. 1 is performed.

In this circuit, the logic gate circuit processing shown in Fig. 3 is changed to shift the potential, and the load of the differential amplifier at the subsequent stage is made into a constant current source. , the function of the driving interface is realized using the elements of the logic operation section. Therefore, the number of circuit elements is small.

As the circuit in Figure 6 shows, in this driver circuit, the paths leading to the two solid-state switches are the same up to the input of the last differential amplifier in the logic operation section, so the timing of driving both solid-state switches is accurate. Matches well. '1fC1 This logic operation section is a simple two-stage stationary amplifier, and has fewer passing elements than the conventional two-stage logic circuit with a complex internal circuit shown in FIG. , less. Thus, the timing accuracy of this driver circuit is good.

Furthermore, as is clear from the circuit diagram of FIG. 6, since the number of stages of the circuit from the two inputs to the solid-state switch is equal, the propagation delay time from both inputs is equal.

As described above, this driver circuit has excellent characteristics in that timing accuracy is high and the propagation delay times of the two inputs are equal.

Furthermore, the pace of transistors T14 and T15 in Fig. 6.

The diodes connected between the emitters and the rear terminals are diodes for limiting the drive signal voltage amplitude, and constitute a nine-mitting circuit based on the emitter electrodes of the transistors T1a and T+s that receive the drive signal. There is. As a result, both the transient time and the propagation delay time can be changed at the rise and fall of the signal. This contributes to the uniformity of the buildings.

〔Effect of the invention〕

The present invention improves the timing accuracy of the driver and equalizes the propagation delay time of the two-man power by introducing a logic operation circuit method that focuses on multi-value potential into a driver circuit with a tri-state function. The biggest effect is that he became able to perform.

Even when this do-wiper circuit is constructed with ordinary high-speed elements,
Timing accuracy is 0.1rnS, the difference in propagation delay time for two inputs is approximately 3n8, and if this is configured with an easily available ultra-sieving speed converter, both values are 10 pS and 50 pS or less, respectively. It is also possible to do this.

This is an extremely large improvement compared to the two values of 50 to 1 oop 8 degrees and 1 to 2 nS when the logic operation section is configured with embedded circuit elements, and it is clear that the present invention is very superior. becomes.

In explaining the present invention, we have focused on circuits using bipolar transistors, but it is also possible to configure a circuit to which the method of the present invention is applied even if FB'l' etc. are used. Of course.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the basic configuration of a driver circuit with a tri-state function, Figure 2 is a conventional driver circuit, and Figure 3 is a logic gate circuit using multi-value potential used in the present invention. , FIG. 4 is an explanatory diagram of the internal potential of the differential amplifier C1 in FIG. 3, FIG. 5 is an explanatory diagram of the internal potential related to the operation of the logic gate circuit of FIG.
The figure is a circuit diagram of an embodiment of a driver circuit according to the present invention. T1-T15...Bipolar transistor, D...
・Diode, Zl, 2... Zener diode, Vcc...
・Positive power supply voltage, Vmz...Negative power supply voltage, D...High/low level designation signal Kugata and its inverted input 5 Attorney Akio Takahashi'tJ3 口λ力■ Figure 4 Input type, 4 Madness Figure S procedural amendment (spontaneous) Indication of the case Patent application No. 188i3 of 1988 Name of the invention Relationship with the person making the driver circuit correction 11 cases Patent applicant name Name 1510144 Shikikai 11 Manufactured by Hitachi
Contents of amendments to Figure 2 of the representative drawing Figure 2

Claims (1)

[Claims] It has a 30th level between the high level and the low level as an output level, and has the ability to output two or more of the above six levels from each of its two output terminals. 1 differential amplifier, and second and third differential amplifiers each having an output of the first differential amplifier as one input, the second . A driver circuit characterized in that it is configured to control a switching element by the output of a third differential amplifier.