JPS6079429A - Floating point computing element - Google Patents

Abstract

PURPOSE:To omit arithmetic of ineffective digits and to realize high-speed arithmetic processing by inputting input data having arithmetic numerals represented in code, etc., to respective computing elements and displaying effective digits of a result of arithmetic which is performed by referring to effective digits. CONSTITUTION:A couple of input registers 1 and 2 constituting a floating point computing element consist of exponent parts Ex and Ey which fetch codes Sx and Sy of operands and an exponent E, mantissa parts Mx and My which fetch a mantissa M, and effective digit parts Px and Py which input an effective digit P. An arithmetic part 3, on the other hand, consists of a shift register SR, etc., and an exponent arithmetic part AE compares both exponents with each other and operates the shift register SR so that they coincide with each other. A mantissa arithmetic part MA performs the arithmetical operation of the mantissas after decimal-point matching, and an effective digit arithmetic part PA compares effective digits to hold a smaller digit as a new effective digit, and also normalizes and corrects the arithmetic result of the exponent arithmetic part EA. The respective arithmetic results are sent out to an output register 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to floating point arithmetic technology, and for example, to a technology effective for floating point arithmetic units such as automatic control requiring high reliability.

[Background technology]

The conventional floating point arithmetic method is performed by the following four steps. (Refer to Chapter 9, “Normalized Floating Point Arithmetic Unit” in “High-Speed Arithmetic Methods for R Computers,” published by Kindai Kagakusha, translated by Yasushi Horikome.) (1) Zero check for operands (2) Mantissa to match the exponents of both operands (3) Addition/subtraction of addends (4) Normalization of operation results The inventor's research has revealed that this type of floating point arithmetic system has the following drawbacks. Ta.

For example, for ease of understanding, x-3,
15X10-5. When performing the addition of y=-3, 14X10-', the calculation result 2 can be calculated as follows.

The above +1+ is used to determine that it is not zero (if either X or y is zero, the operation is omitted and only the sign thereof is processed). If both are not zero, the indices are matched according to 2) above. In this example, since they match, the calculation (3, 15-3, 14) x 10-5 is performed according to (3) above. This result z = 0. Since OI X 10'-', normalization is performed to 1.00X10-' according to (4) above.

On the other hand, x=5.04X10-8. y=4.99xlO-
When adding e, z'=10.03 in the same way as above.
X10-', and by rounding off by normalization, it becomes 1.
00X10-'. The above calculation results 2 and 2° represent the same numerical value, but their contents (accuracy) are different. That is, due to rounding, the effective digits of 2 are up to the 10-1 digit, whereas 2' is up to the 10-9 digit obtained by rounding off 10-10.

In other words, in 2'', the 0s up to 10-9 have meaning, whereas in 2, only the 1s in the 10-1 digit are meaningful, so 10-8. 0 in the 10-9 digit. This is because they are simply added as part of a completely meaningless normalization process.

Therefore, when using the above 2 and 2 in the next operation or evaluating the result, there is a serious flaw in that conventional floating point arithmetic methods cannot distinguish between them and have to treat them as the same thing. be.

(Object of the Invention) An object of the present invention is to provide a floating-point arithmetic unit that guarantees the accuracy of calculation results.

Another object of the present invention is to provide a floating point arithmetic unit that realizes high-speed arithmetic processing.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, input data in which a calculated value is expressed as a sign, an exponent, a mantissa, and a significant digit are each input to a computing unit, and the significant digits of the operation result are output by performing the respective operations with reference to the above-mentioned significant digits. , the calculation of invalid digits in mantissa calculation is omitted.

〔Example〕

The drawing shows a block diagram of a floating point arithmetic unit according to the present invention.

In this embodiment, numerical values (operands) are expressed as follows. That is, one numerical value has a sign S, an exponent E, a mantissa M, and a new significant digit (precision) P.

Therefore, the pair of input registers 1.2 constituting the floating point arithmetic unit of this embodiment has the sign S of the above operand.
x, Sy + exponent The exponent parts Ex and Ey are taken in, and the mantissa part Mx is taken in.

My, and significant digit parts px and py that take in the significant digit P. Although not particularly limited, the calculation section 3 includes a shift register SR, an exponent calculation section EA that performs exponent calculation, a mantissa calculation section MA that performs mantissa calculation, and a significant digit calculation section that performs calculation of significant digit data. It is composed of PA.

Although not particularly limited, the data in the mantissa part Mx of one of the input registers 1 is the shift register S.
input to R. This is to perform a digit alignment operation for both operands. That is, the exponent part Ex, By
The exponent operation unit AE, which receives the data, compares both exponents and operates the shift register SR so that the exponent of the exponent part Ey of the input register matches the exponent of the numeral part Ex. . The mantissa operation unit MA performs arithmetic operations on the mantissas of both operands whose digits have been aligned by the operation of the shift register SR.

Further, the significant digit calculation unit PA compares the significant digit information shown in the form of exponents of both operands, and holds the smaller significant digit as new significant digit information. Further, the correction is performed according to the normalization (rounding) operation of the calculation result of the exponent calculation unit EA.

The calculation results of each of the above calculation units are a sign part Sz, an exponent part Ez,
It is sent to an output register 4 consisting of a mantissa part MZ and a significant digit part Pz.

The arithmetic operation by the above floating point arithmetic unit will be explained by specifically showing numerical values.

As before, for ease of understanding, the operands expressed in decimal numbers x = 3.15X10-', y = -3,14X10
When performing addition of -5, both significant digits of x and y are 10-1
Therefore, the exponent -7 is added (. In this example, since both significant digits are the same, the operation result 2 can be obtained in the same way as described above. In other words, the above +11 makes both operands Check that is not zero using the mantissa calculation unit MA (if either X or y is zero, omit the calculation,
(process only that sign). If both x and y are not zero, the indices are made to match according to (2) above. In this example, they match, so according to (3) above, (3,15-
3, 14) x 1 (1-5 calculation is performed. This result is 2 = 0.0IX10-5, so normalization is performed to 1.00x10-I using <4) above. . In this case, since the effective digit is -7, it is added to the calculation result 2 as is.

On the other hand, operand x = 5.04 x 10-8. y
When performing the addition of =4.99X10-8, -10 is added because both effective digits are 10-10. Then, the calculation result 2 is calculated as z'=10.03 in the same way as above.
XlO-8, and rounding off by normalization gives 1.
00X10-'. 10-1 due to the above normalization process
Since the 0 digit has been rounded off, its effective digit becomes 10-9, so it is corrected to show that the effective digit is -9.

Therefore, although the above calculation results 2 and 2゛ formally represent the same numerical value, their significant digits are different, such as -7 and -9. It's easy to know.

In this way, in addition to being able to express precision, this embodiment is useful for high-speed arithmetic processing.

For example, X=3.14X10-5.7-3.15X10
When the significant digits are different, such as -1, the calculation of the numerical value below the smaller significant digit is omitted. That is, since the 10-8 digits of X are within the error range, the numerical values after the 10-8 digits of y are necessarily within the error range. Therefore, the addition in this case is (314+3)xlO-'=3
17xlO-' and normalize it. As a result, (314,00+3.15) X
Since the number of digits to be processed can be omitted compared to an operation with a larger number of digits such as 10-', the speed of the operation can be increased. This means that if one of the two numbers has less than the significant digits, the calculation process can be completely omitted, and the calculation result can be obtained only by the same process as in the floating point calculation processing step (11). It will be done.

〔effect〕

(1) By adding significant digit information to the numerical value,
This has the effect of being able to express the weight of the accuracy of the calculation result.

(2) By adding significant digit information and omitting meaningless numerical calculations in the error range of one numerical value,
One effect is that high-speed processing can be achieved while maintaining accuracy.
be qed.

(3) Since meaningless digits can be omitted, memory capacity can be saved.

(4) By being able to cancel a dangerous operation that increases the error caused by calculating a numerical value within the error range of one numerical value, it is possible to obtain highly accurate calculation results.

The invention made by the inventor Kei has been specifically explained above based on examples, but it goes without saying that this invention is not limited to the above examples and can be modified in various ways without departing from the gist of the invention. Nor. The configuration of the arithmetic circuit other than the part that calculates significant digit information can take various embodiments. For example, the arithmetic unit may use one arithmetic unit having an arithmetic logic unit and a shift register function in a time-sharing manner. Furthermore, the output register 4 may be omitted and the calculation result may be sent to one input register. In addition, the input register and output register are RAM
(Random access memory) may also be used. In this case, it is useful for the mantissa calculation operation to have a function of omitting calculations for parts outside the effective digits in order to perform high-speed calculations as described above.

Furthermore, when converting from the numerical representation method according to the present invention to the conventional numerical representation method (normalization), select a format appropriate for the precision (significant digits) from single precision double ellipse or extended double precision. It is.

[Application field]

The present invention can be widely applied to various floating point arithmetic units, and is particularly effective for plant control, measurement control, etc., which require high precision, or electronic computers, microcomputers, etc., which require high-speed calculation.

[Brief explanation of the drawing]

A block diagram showing one embodiment of the invention is shown in the drawings.

Claims (1)

[Claims] 1. A pair of registers into which input data in a format consisting of a sign, an exponent, a mantissa, and a significant digit are respectively input for one numerical value, a mantissa calculator that calculates the mantissa taken into the register, and An exponent calculator that calculates the loaded exponent, a shift register that receives the mantissa data of one of the registers and matches the exponents of the data loaded into both registers, and a significant digit loaded into the register. and a significant digit arithmetic unit that receives the data and forms significant digit data of an operation result based on the smaller significant digit. 2. The floating point arithmetic unit according to claim 1, wherein the mantissa arithmetic unit omits arithmetic processing of mantissa values that are out of significant digits.