JPS6077453A - Packaging method of hybrid ic - Google Patents
Packaging method of hybrid icInfo
- Publication number
- JPS6077453A JPS6077453A JP58185543A JP18554383A JPS6077453A JP S6077453 A JPS6077453 A JP S6077453A JP 58185543 A JP58185543 A JP 58185543A JP 18554383 A JP18554383 A JP 18554383A JP S6077453 A JPS6077453 A JP S6077453A
- Authority
- JP
- Japan
- Prior art keywords
- hybrid
- substrate
- substrates
- resin
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
(ω 発明の技術分野
本発明はハイブリッドICのパッケージング方法の改良
に係る。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to improvements in packaging methods for hybrid ICs.
(ロ)技術の背景
ハイブリッドICはセラミック基板例えばアルミナ基板
の表面に半導体集積回路を形成し、さらに所望の個別部
品を実装した後に、偏頼性の向上J−AM白e+45に
凋1σ)?−1/NIffjtif171411M上誌
aIffN:”2+111J一端子を除いて樹脂封止す
るのが可逆である。(b) Background of the technology Hybrid ICs are manufactured by forming a semiconductor integrated circuit on the surface of a ceramic substrate, such as an alumina substrate, and then mounting desired individual components. -1/NIffjtif171411M above aIffN: "2+111J It is reversible to seal with resin except for one terminal.
また通信機器、磯子機器などの小形化、高性能化の要求
に伴い、ハイブリッドICも小形でかつプリント板など
に高密度に搭載容易なことが要求されている。In addition, with the demand for smaller size and higher performance of communication equipment, Isogo equipment, etc., hybrid ICs are also required to be small and easy to be mounted on printed boards and the like at high density.
(C) 従来技術と問題点
第1図は従来のハイブリッドIOの一例を示す図でろシ
(イ)は樹脂封止前の斜視図、(ロ)は樹脂封止パッケ
ージング後の斜視図である。(C) Prior art and problems Figure 1 shows an example of a conventional hybrid IO. (a) is a perspective view before resin sealing, and (b) is a perspective view after resin sealing packaging. .
同図(イ)に〉いて、lは短形状のセラミック基板で、
一方の側縁部には端子3が直付けされ、基板lの表面に
並行して突出している。基板lの表面には図示していな
い半導体集積回路と個別部品2122 が実装されてい
る。In the same figure (a), l is a rectangular ceramic substrate,
A terminal 3 is directly attached to one side edge and protrudes parallel to the surface of the substrate l. A semiconductor integrated circuit and individual components 2122 (not shown) are mounted on the surface of the substrate l.
(ロ)においては、(イ)の如く構成されたハイプリン
トIOが、樹脂例えばエポキシ樹脂、フェノール樹脂な
どでトランスファーモルトされ″C,樹脂封止され、長
方体状のパッケージ4内に端子3以外はすべて封入され
て、ノ・イブリッドIO5が完成されている。In (b), the high print IO configured as in (a) is transfer-molded with a resin such as epoxy resin or phenol resin, and sealed with resin, and terminals 3 are placed in a rectangular package 4. Everything else has been sealed, and No-Ibrid IO5 has been completed.
第2図は第1図ハイブリラドIO5がプリント板に搭載
さね、た斜視図である。FIG. 2 is a perspective view of the HybridRAD IO5 of FIG. 1 mounted on a printed board.
同図において、ハイブリッドl05iJ:端面より突出
した端子3が、プリント板6のスルーホール11人され
て、垂直に並設さね、ている。In the figure, a hybrid 105iJ has terminals 3 protruding from the end face through 11 through holes in a printed board 6 and arranged vertically in parallel.
なお、プリント板6に4他の搭載部品7か多数高密度に
並設されている。Note that a large number of other mounting components 7 are arranged in parallel on the printed board 6 at high density.
このようにハイブリッドI05は、細長い端面より端子
3を突出せしめてちるので、プリント板60表面上に広
い平面部を載置するよりに、はるかに高密度に搭載出来
るものである。In this way, since the hybrid I05 has the terminals 3 protruding from the elongated end surface, it can be mounted at a much higher density than if a wide flat area is mounted on the surface of the printed board 60.
しかし乍ら、個別部品の高さが高い場合には特にパッケ
ージの厚さが大きくなり、また、個々のバイア’ l)
ラドIC間に搭載間隔が必要であるので、搭載スペース
が大きくなるという問題点がある。However, the thickness of the package becomes large, especially when the height of the individual components is high, and the thickness of the individual vias increases.
Since a mounting interval is required between the RAD ICs, there is a problem that the mounting space becomes large.
コスト高となるおそれもちる〇
(山 発明の目的
本発明の目的に上記従来の問題点が除去されたハイブリ
ッドICのパンケージング方法を提供することにある。Object of the Invention An object of the present invention is to provide a hybrid IC pancasing method that eliminates the above-mentioned conventional problems.
(e) 発明の構成
この目的を達成するために本発明に、同形状のセラミッ
ク基板上VC宿1戎された2つのノ\イブIJ ラド1
0が、該基板を外11+11にして重ねた場合に、それ
ぞれの該基板上の114別部品が接触しないように実装
されてlχす、かつ端子が対向するl1lll!朱より
突出するように重11た状態で、樹脂封止し一体化せし
めるようにするものてあゐ。(e) Structure of the Invention In order to achieve this object, the present invention includes two nozzles IJ rad 1 formed on a ceramic substrate of the same shape.
0 is mounted so that the 114 separate parts on each board do not contact each other when the boards are stacked with the outside facing 11+11, and the terminals are facing each other. The weight 11 is placed so as to protrude from the vermilion, and is then sealed with resin and integrated.
(1) 発明の笑M4例
以下図示実hIすを参照して本発明について詳S1uに
説明する。(1) Example of the Invention The present invention will be explained in detail in S1u with reference to the illustrated examples.
第3図は本発明の一実施例の(イ)は/%()゛))ラ
ド■Cケ重ねた状態の斜4jA図、(ロ)は(イ)のも
のの樹脂封止パッケージング後の斜視図でろろ。Figure 3 shows an example of the present invention (A) is /% ()゛))RAD ■ C . It's a perspective view.
第3図(イ)において、ノ\イブリッド108の+5形
板状のセラミック基板9に1所望の図示してない半導体
集積回路が形成され、さらに詞別部、情9192 が実
装され−Cいる。個別114品!ノ1と92の間隔は1
1^1別郡品9v)1%、;よりも大きく、実装されて
いる。In FIG. 3(a), a desired semiconductor integrated circuit (not shown) is formed on the +5-shaped ceramic substrate 9 of the hybrid 108, and furthermore, an information section 9192 is mounted. 114 individual items! The interval between No. 1 and 92 is 1
1^1 separate county product 9v) 1%,; is larger than and implemented.
また基板9の側を号より、基4FL9の表面に並行して
突出しC端子10が並設さnている。Further, from the side of the substrate 9, C terminals 10 are provided in parallel to the surface of the base 4FL9, protruding from the surface.
ハイブリッドI(J11&X、基板9と同形状のセラミ
ック基板120表面に、所望の図示してない半、!$体
体積積回路形成さJtl さらに、個別部品9192
と同形状の個別部品121.122 が)\イブリッド
IO8と同I装置で実装されている。また基板12の(
llll斥には)・、に子10に対応して端子13が並
設Jiしている。即ちハイブリッドl0IIとハイブリ
ッドI(J8とはすべ゛C同形、火のものである。Hybrid I (J11 &
Individual parts 121 and 122 with the same shape as )\IBRID IO8 and the same I device are mounted. Also, the board 12 (
Terminals 13 are arranged in parallel to correspond to Nikko 10. That is, Hybrid 10II and Hybrid I (J8 are all C isomorphic and fire).
この2つのハイブリッドIO8とハイブリッドI011
とを基板9と基板12とが外側になる如くに重ねると、
個別部品91と個別部品92との間に個別部品122か
個別部品9り側方に個別部品121がそれぞれ嵌入する
ごとくに重なるので、基板9と基板12の間隔扛、はぼ
、高さの一番高い個別部品の高さに等しくすることが出
来る。These two hybrid IO8 and hybrid I011
If you stack them so that the substrate 9 and the substrate 12 are on the outside,
Since the individual parts 122 are fitted between the individual parts 91 and 92 and the individual parts 121 are fitted laterally, the distance, width, and height between the boards 9 and 12 are not the same. It can be made equal to the height of the tallest individual component.
(に)においてに、ハイブリッド108および11のピ
ッチをプリント板の害体格子の整数倍になる如くした後
に例えばエポキシ樹脂にてトランスケ−モールドして樹
脂封止し、長方体状のパックー)14内に端子10 、
13以外をすべて封入して一体化しである。In (2), the pitch of the hybrids 108 and 11 is made to be an integral multiple of the harmful grid of the printed board, and then transke molded and resin-sealed with, for example, epoxy resin to form a rectangular pack (14). Terminal 10 inside,
All except 13 are enclosed and integrated.
このようにしてされた一体上ノ・イブリッドICl3の
パッケージ14の厚さは、従来方法のパッケージの2個
分よりも非常に薄くて、プリント板上に高密度Qこ、搭
載することが出来る。またノくツケージングエ数も2つ
のノXイブリッドICを同時に行うので従来のほぼ、半
分であり樹脂の使用量もまたほぼ半分で済むものである
。The thickness of the integrated hybrid ICl3 package 14 made in this way is much thinner than that of two conventional packages, and can be mounted on a printed circuit board with high density. Furthermore, since two hybrid ICs are simultaneously processed, the number of packaging operations is approximately half that of the conventional method, and the amount of resin used is also approximately half.
なお本発明(1図示実施例に限定されるものでなく、例
えば異なるハイプリントICを重ねてバクケージングす
る、牛だ2つ以上の)・イブリントICを重ねてパンケ
ージングし°r−+・1化するとか、あるいt工樹脂封
止す石のにモールドでなくディッピング、ポツテング方
法などで一体化してパンケージングするなど特許請求の
範囲内で適宜変形実施(ω 発明の詳細
な説明したように本発明は、複数のハイブリッドICを
小形な形状に一体化することが出来てプリント板などに
高密度に搭載すること75;出来、かつパッケージング
のコストが低コストであるなどといった実用上ですぐカ
フた効果のあるハイブリッドICのパンケージング方法
である。Note that the present invention (not limited to one illustrated embodiment, for example, stacking different high-print ICs for back-caging, two or more high-print ICs for pan-caging), stacking high-print ICs for pan-caging, etc. It is possible to carry out appropriate modifications within the scope of the patent claims, such as by integrating the stone into a T resin-sealed stone by dipping, potting, etc. instead of molding and pancaging (ω) As described in the detailed description of the invention. The present invention has practical advantages such as being able to integrate a plurality of hybrid ICs into a compact shape, allowing for high-density mounting on a printed circuit board, etc.75; and low packaging cost. This is a hybrid IC pancaging method that has a cuffing effect.
第1図は従来のハイブリッドICの一例の(イ)は樹脂
封止前の斜視図、(ロ)に樹脂封市パッケージノグ後の
斜視図、第2図は第1南のハイブリッドICをプリント
板に搭載した斜視図、第3図は本発明の一実施例の(イ
)はハイブリッドICを重ねた状態の斜視図、(→に(
イ)のものの樹脂封止パンケージング饅の斜視図である
。
図中1.9.12はセラミンク基版、 21.22.9
s。
92、1’21.122 は個別部品、3,10,13
は端子4.141−jパッケージ、5.8.11 F′
r、ハイブリッドυ15は一体化ハイブリラドIOf、
y:示f。Figure 1 shows an example of a conventional hybrid IC, (a) is a perspective view before resin sealing, (b) is a perspective view after resin sealing and packaging, and Figure 2 shows the first south hybrid IC on a printed board. Figure 3 is a perspective view of one embodiment of the present invention, (A) is a perspective view of the hybrid IC stacked on top of each other.
It is a perspective view of the resin-sealed pancasing rice cake of (a). In the figure, 1.9.12 is a ceramic base plate, 21.22.9
s. 92, 1'21.122 is an individual part, 3, 10, 13
is terminal 4.141-j package, 5.8.11 F'
r, hybrid υ15 is an integrated hybrid IOf,
y: Indication f.
Claims (1)
ッドICが、該基板を外側にして重ねた場合に、七れぞ
ルの該基板上の個別部品が接触しないように実装されて
なシ、かつ端子が対向する側醜より突出するように重ね
た状態で、樹脂封止し一体化することを特数とするノ・
イブリントI(3のパッケージング方法。If two hybrid ICs configured on ceramic substrates of the same shape are stacked on top of each other with the substrates on the outside, the individual components on each of the substrates must not come into contact with each other, and The special feature is that the terminals are stacked so that they protrude from the opposite side and are sealed with resin and integrated.
Evelint I (3 packaging methods.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58185543A JPS6077453A (en) | 1983-10-04 | 1983-10-04 | Packaging method of hybrid ic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58185543A JPS6077453A (en) | 1983-10-04 | 1983-10-04 | Packaging method of hybrid ic |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6077453A true JPS6077453A (en) | 1985-05-02 |
Family
ID=16172639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58185543A Pending JPS6077453A (en) | 1983-10-04 | 1983-10-04 | Packaging method of hybrid ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6077453A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5812952B2 (en) * | 1975-05-16 | 1983-03-10 | 三菱レイヨン株式会社 | Jiyuunanna Cellulo - Sukeifushiyokufuno Seizouhou |
-
1983
- 1983-10-04 JP JP58185543A patent/JPS6077453A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5812952B2 (en) * | 1975-05-16 | 1983-03-10 | 三菱レイヨン株式会社 | Jiyuunanna Cellulo - Sukeifushiyokufuno Seizouhou |
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