JPS6077453A - Packaging method of hybrid ic - Google Patents

Packaging method of hybrid ic

Info

Publication number
JPS6077453A
JPS6077453A JP58185543A JP18554383A JPS6077453A JP S6077453 A JPS6077453 A JP S6077453A JP 58185543 A JP58185543 A JP 58185543A JP 18554383 A JP18554383 A JP 18554383A JP S6077453 A JPS6077453 A JP S6077453A
Authority
JP
Japan
Prior art keywords
hybrid
substrate
substrates
resin
gap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58185543A
Other languages
Japanese (ja)
Inventor
Toshihiko Yamamoto
俊彦 山本
Hidenori Tanizawa
谷沢　秀徳
Hideyuki Kurosawa
黒沢　秀行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP58185543A priority Critical patent/JPS6077453A/en
Publication of JPS6077453A publication Critical patent/JPS6077453A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To enable to place a package reduced in small size on a printed board in high density by securing a hybrid IC on two ceramic substrates of the same shape, opposing the IC side so as not to contact with the IC, superposing the substrate, connecting to the terminal of the peripheral edge of the substrate through the gap, and then sealing with resin. CONSTITUTION:Two ceramic substrates 9, 12 of the same shape from which a plurality of terminals 10 are projected at the peripheral edge are used, and a plurality of individual parts 91, 92 are secured at the prescribed wide gap on one surface of the substrate 9. When the substrates 9, 12 are also superposed on one surface of the other substrate 12, parts 121, 122 to be introduced into the gap between the parts 91 and 92 are secured, and connecting wirings are connected to the terminal 10 of the terminal group 13 through the gap of the substrates 9, 12. Thereafter, the terminal group 13 are externally exposed, and the substrates 9, 13 are sealed with resin and packaged. Thus, the package can be reduced in size and in cost.

Description

【発明の詳細な説明】 （ω　発明の技術分野 本発明はハイブリッドＩＣのパッケージング方法の改良
に係る。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to improvements in packaging methods for hybrid ICs.

（ロ）技術の背景 ハイブリッドＩＣはセラミック基板例えばアルミナ基板
の表面に半導体集積回路を形成し、さらに所望の個別部
品を実装した後に、偏頼性の向上Ｊ−ＡＭ白ｅ＋４５に
凋１σ）？−１／ＮＩｆｆｊｔｉｆ１７１４１１Ｍ上誌
ａＩｆｆＮ：”２＋１１１Ｊ一端子を除いて樹脂封止す
るのが可逆である。(b) Background of the technology Hybrid ICs are manufactured by forming a semiconductor integrated circuit on the surface of a ceramic substrate, such as an alumina substrate, and then mounting desired individual components. -1/NIffjtif171411M above aIffN: "2+111J It is reversible to seal with resin except for one terminal.

また通信機器、磯子機器などの小形化、高性能化の要求
に伴い、ハイブリッドＩＣも小形でかつプリント板など
に高密度に搭載容易なことが要求されている。In addition, with the demand for smaller size and higher performance of communication equipment, Isogo equipment, etc., hybrid ICs are also required to be small and easy to be mounted on printed boards and the like at high density.

（Ｃ）　従来技術と問題点 第１図は従来のハイブリッドＩＯの一例を示す図でろシ
（イ）は樹脂封止前の斜視図、（ロ）は樹脂封止パッケ
ージング後の斜視図である。(C) Prior art and problems Figure 1 shows an example of a conventional hybrid IO. (a) is a perspective view before resin sealing, and (b) is a perspective view after resin sealing packaging. .

同図（イ）に〉いて、ｌは短形状のセラミック基板で、
一方の側縁部には端子３が直付けされ、基板ｌの表面に
並行して突出している。基板ｌの表面には図示していな
い半導体集積回路と個別部品２１２２　が実装されてい
る。In the same figure (a), l is a rectangular ceramic substrate,
A terminal 3 is directly attached to one side edge and protrudes parallel to the surface of the substrate l. A semiconductor integrated circuit and individual components 2122 (not shown) are mounted on the surface of the substrate l.

（ロ）においては、（イ）の如く構成されたハイプリン
トＩＯが、樹脂例えばエポキシ樹脂、フェノール樹脂な
どでトランスファーモルトされ″Ｃ，樹脂封止され、長
方体状のパッケージ４内に端子３以外はすべて封入され
て、ノ・イブリッドＩＯ５が完成されている。In (b), the high print IO configured as in (a) is transfer-molded with a resin such as epoxy resin or phenol resin, and sealed with resin, and terminals 3 are placed in a rectangular package 4. Everything else has been sealed, and No-Ibrid IO5 has been completed.

第２図は第１図ハイブリラドＩＯ５がプリント板に搭載
さね、た斜視図である。FIG. 2 is a perspective view of the HybridRAD IO5 of FIG. 1 mounted on a printed board.

同図において、ハイブリッドｌ０５ｉＪ：端面より突出
した端子３が、プリント板６のスルーホール１１人され
て、垂直に並設さね、ている。In the figure, a hybrid 105iJ has terminals 3 protruding from the end face through 11 through holes in a printed board 6 and arranged vertically in parallel.

なお、プリント板６に４他の搭載部品７か多数高密度に
並設されている。Note that a large number of other mounting components 7 are arranged in parallel on the printed board 6 at high density.

このようにハイブリッドＩ０５は、細長い端面より端子
３を突出せしめてちるので、プリント板６０表面上に広
い平面部を載置するよりに、はるかに高密度に搭載出来
るものである。In this way, since the hybrid I05 has the terminals 3 protruding from the elongated end surface, it can be mounted at a much higher density than if a wide flat area is mounted on the surface of the printed board 60.

しかし乍ら、個別部品の高さが高い場合には特にパッケ
ージの厚さが大きくなり、また、個々のバイア’　ｌ）
ラドＩＣ間に搭載間隔が必要であるので、搭載スペース
が大きくなるという問題点がある。However, the thickness of the package becomes large, especially when the height of the individual components is high, and the thickness of the individual vias increases.
Since a mounting interval is required between the RAD ICs, there is a problem that the mounting space becomes large.

コスト高となるおそれもちる〇 （山　発明の目的 本発明の目的に上記従来の問題点が除去されたハイブリ
ッドＩＣのパンケージング方法を提供することにある。Object of the Invention An object of the present invention is to provide a hybrid IC pancasing method that eliminates the above-mentioned conventional problems.

（ｅ）　発明の構成 この目的を達成するために本発明に、同形状のセラミッ
ク基板上ＶＣ宿１戎された２つのノ＼イブＩＪ　ラド１
０が、該基板を外１１＋１１にして重ねた場合に、それ
ぞれの該基板上の１１４別部品が接触しないように実装
されてｌχす、かつ端子が対向するｌ１ｌｌｌ！朱より
突出するように重１１た状態で、樹脂封止し一体化せし
めるようにするものてあゐ。(e) Structure of the Invention In order to achieve this object, the present invention includes two nozzles IJ rad 1 formed on a ceramic substrate of the same shape.
0 is mounted so that the 114 separate parts on each board do not contact each other when the boards are stacked with the outside facing 11+11, and the terminals are facing each other. The weight 11 is placed so as to protrude from the vermilion, and is then sealed with resin and integrated.

（１）　発明の笑Ｍ４例 以下図示実ｈＩすを参照して本発明について詳Ｓ１ｕに
説明する。(1) Example of the Invention The present invention will be explained in detail in S1u with reference to the illustrated examples.

第３図は本発明の一実施例の（イ）は／％（）゛））ラ
ド■Ｃケ重ねた状態の斜４ｊＡ図、（ロ）は（イ）のも
のの樹脂封止パッケージング後の斜視図でろろ。Figure 3 shows an example of the present invention (A) is /% ()゛))RAD ■ C . It's a perspective view.

第３図（イ）において、ノ＼イブリッド１０８の＋５形
板状のセラミック基板９に１所望の図示してない半導体
集積回路が形成され、さらに詞別部、情９１９２　が実
装され−Ｃいる。個別１１４品！ノ１と９２の間隔は１
１＾１別郡品９ｖ）１％、；よりも大きく、実装されて
いる。In FIG. 3(a), a desired semiconductor integrated circuit (not shown) is formed on the +5-shaped ceramic substrate 9 of the hybrid 108, and furthermore, an information section 9192 is mounted. 114 individual items! The interval between No. 1 and 92 is 1
1^1 separate county product 9v) 1%,; is larger than and implemented.

また基板９の側を号より、基４ＦＬ９の表面に並行して
突出しＣ端子１０が並設さｎている。Further, from the side of the substrate 9, C terminals 10 are provided in parallel to the surface of the base 4FL9, protruding from the surface.

ハイブリッドＩ（Ｊ１１＆Ｘ、基板９と同形状のセラミ
ック基板１２０表面に、所望の図示してない半、！＄体
体積積回路形成さＪｔｌ　さらに、個別部品９１９２　
と同形状の個別部品１２１．１２２　が）＼イブリッド
ＩＯ８と同Ｉ装置で実装されている。また基板１２の（
ｌｌｌｌ斥には）・、に子１０に対応して端子１３が並
設Ｊｉしている。即ちハイブリッドｌ０ＩＩとハイブリ
ッドＩ（Ｊ８とはすべ゛Ｃ同形、火のものである。Hybrid I (J11 &
Individual parts 121 and 122 with the same shape as )\IBRID IO8 and the same I device are mounted. Also, the board 12 (
Terminals 13 are arranged in parallel to correspond to Nikko 10. That is, Hybrid 10II and Hybrid I (J8 are all C isomorphic and fire).

この２つのハイブリッドＩＯ８とハイブリッドＩ０１１
とを基板９と基板１２とが外側になる如くに重ねると、
個別部品９１と個別部品９２との間に個別部品１２２か
個別部品９り側方に個別部品１２１がそれぞれ嵌入する
ごとくに重なるので、基板９と基板１２の間隔扛、はぼ
、高さの一番高い個別部品の高さに等しくすることが出
来る。These two hybrid IO8 and hybrid I011
If you stack them so that the substrate 9 and the substrate 12 are on the outside,
Since the individual parts 122 are fitted between the individual parts 91 and 92 and the individual parts 121 are fitted laterally, the distance, width, and height between the boards 9 and 12 are not the same. It can be made equal to the height of the tallest individual component.

（に）においてに、ハイブリッド１０８および１１のピ
ッチをプリント板の害体格子の整数倍になる如くした後
に例えばエポキシ樹脂にてトランスケ−モールドして樹
脂封止し、長方体状のパックー）１４内に端子１０　、
１３以外をすべて封入して一体化しである。In (2), the pitch of the hybrids 108 and 11 is made to be an integral multiple of the harmful grid of the printed board, and then transke molded and resin-sealed with, for example, epoxy resin to form a rectangular pack (14). Terminal 10 inside,
All except 13 are enclosed and integrated.

このようにしてされた一体上ノ・イブリッドＩＣｌ３の
パッケージ１４の厚さは、従来方法のパッケージの２個
分よりも非常に薄くて、プリント板上に高密度Ｑこ、搭
載することが出来る。またノくツケージングエ数も２つ
のノＸイブリッドＩＣを同時に行うので従来のほぼ、半
分であり樹脂の使用量もまたほぼ半分で済むものである
。The thickness of the integrated hybrid ICl3 package 14 made in this way is much thinner than that of two conventional packages, and can be mounted on a printed circuit board with high density. Furthermore, since two hybrid ICs are simultaneously processed, the number of packaging operations is approximately half that of the conventional method, and the amount of resin used is also approximately half.

なお本発明（１図示実施例に限定されるものでなく、例
えば異なるハイプリントＩＣを重ねてバクケージングす
る、牛だ２つ以上の）・イブリントＩＣを重ねてパンケ
ージングし°ｒ−＋・１化するとか、あるいｔ工樹脂封
止す石のにモールドでなくディッピング、ポツテング方
法などで一体化してパンケージングするなど特許請求の
範囲内で適宜変形実施（ω　発明の詳細 な説明したように本発明は、複数のハイブリッドＩＣを
小形な形状に一体化することが出来てプリント板などに
高密度に搭載すること７５；出来、かつパッケージング
のコストが低コストであるなどといった実用上ですぐカ
フた効果のあるハイブリッドＩＣのパンケージング方法
である。Note that the present invention (not limited to one illustrated embodiment, for example, stacking different high-print ICs for back-caging, two or more high-print ICs for pan-caging), stacking high-print ICs for pan-caging, etc. It is possible to carry out appropriate modifications within the scope of the patent claims, such as by integrating the stone into a T resin-sealed stone by dipping, potting, etc. instead of molding and pancaging (ω) As described in the detailed description of the invention. The present invention has practical advantages such as being able to integrate a plurality of hybrid ICs into a compact shape, allowing for high-density mounting on a printed circuit board, etc.75; and low packaging cost. This is a hybrid IC pancaging method that has a cuffing effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のハイブリッドＩＣの一例の（イ）は樹脂
封止前の斜視図、（ロ）に樹脂封市パッケージノグ後の
斜視図、第２図は第１南のハイブリッドＩＣをプリント
板に搭載した斜視図、第３図は本発明の一実施例の（イ
）はハイブリッドＩＣを重ねた状態の斜視図、（→に（
イ）のものの樹脂封止パンケージング饅の斜視図である
。 図中１．９．１２はセラミンク基版、　２１．２２．９
ｓ。 ９２、１’２１．１２２　は個別部品、３，１０，１３
は端子４．１４１−ｊパッケージ、５．８．１１　Ｆ′
ｒ、ハイブリッドυ１５は一体化ハイブリラドＩＯｆ、
ｙ：示ｆ。Figure 1 shows an example of a conventional hybrid IC, (a) is a perspective view before resin sealing, (b) is a perspective view after resin sealing and packaging, and Figure 2 shows the first south hybrid IC on a printed board. Figure 3 is a perspective view of one embodiment of the present invention, (A) is a perspective view of the hybrid IC stacked on top of each other.
It is a perspective view of the resin-sealed pancasing rice cake of (a). In the figure, 1.9.12 is a ceramic base plate, 21.22.9
s. 92, 1'21.122 is an individual part, 3, 10, 13
is terminal 4.141-j package, 5.8.11 F'
r, hybrid υ15 is an integrated hybrid IOf,
y: Indication f.

Claims (1)

【特許請求の範囲】[Claims] 同形状のセラミック基板上に構成された２つのハイブリ
ッドＩＣが、該基板を外側にして重ねた場合に、七れぞ
ルの該基板上の個別部品が接触しないように実装されて
なシ、かつ端子が対向する側醜より突出するように重ね
た状態で、樹脂封止し一体化することを特数とするノ・
イブリントＩ（３のパッケージング方法。If two hybrid ICs configured on ceramic substrates of the same shape are stacked on top of each other with the substrates on the outside, the individual components on each of the substrates must not come into contact with each other, and The special feature is that the terminals are stacked so that they protrude from the opposite side and are sealed with resin and integrated.
Evelint I (3 packaging methods.
JP58185543A 1983-10-04 1983-10-04 Packaging method of hybrid ic Pending JPS6077453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58185543A JPS6077453A (en) 1983-10-04 1983-10-04 Packaging method of hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58185543A JPS6077453A (en) 1983-10-04 1983-10-04 Packaging method of hybrid ic

Publications (1)

Publication Number Publication Date
JPS6077453A true JPS6077453A (en) 1985-05-02

Family

ID=16172639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58185543A Pending JPS6077453A (en) 1983-10-04 1983-10-04 Packaging method of hybrid ic

Country Status (1)

Country Link
JP (1) JPS6077453A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812952B2 (en) * 1975-05-16 1983-03-10 三菱レイヨン株式会社 Jiyuunanna Cellulo - Sukeifushiyokufuno Seizouhou

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812952B2 (en) * 1975-05-16 1983-03-10 三菱レイヨン株式会社 Jiyuunanna Cellulo - Sukeifushiyokufuno Seizouhou

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