JPS6074969A - Pwm inverter controller - Google Patents

Abstract

PURPOSE:To enable to PWM-control with good performance inexpensively by reading out a PWM pattern as a serial data from an ROM, and distributing it as 3-phase parallel data to the phases, thereby improving the utility rate of the ROM. CONSTITUTION:A voltage command data given to a multiplexer 5 selects the bit position of an ROM4, and produces only data corresponding to the desired output voltage pattern. The frequency command given to a rate multiplier 2 is altered in response to the output frequency of an inverter, thereby deciding the read-out speed of an ROM data. The PWM data stored in the ROM4 is read out at the speed proportional to the frequency of the inverter. When 3-bit data, i.e., the data of U, V and W phases are aligned in a 3-phase latch circuit 6, 3-phase PWM signals are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] This invention relates to a method for applying "on" to each switching element of a pulse width modulation (PWM) inverter circuit.

Paoff” control signal (hereinafter also referred to as PWM pattern)
Read-only memory (hereinafter also simply referred to as ROM)
The present invention relates to a control device for a PWM inverter which stores the logic pattern of 0 at t 1 pp and controls the content by reading it out by a counter or the like operating at a clock frequency proportional to the inverter output frequency.

[Prior art and its problems]

Figure 1 is a principle diagram for explaining the principle of PWM pattern generation, in which a modulated wave (sine wave) Sl representing a desired output (voltage) waveform is compared with a carrier wave (triangular wave) S2, and the modulated wave S1 is In the area larger than the carrier wave S2, it is turned on, for example, logic ``1'', and in the area smaller, it is turned off, and the logic uO'' is set to 5, respectively.
The PWM pattern in the case shown in the same figure (A) is shown in the same figure (B).
The output (voltage) waveform of the inverter is shown as shown in FIG.

Figure 2A is a circuit diagram showing an example of the inverter main circuit;
Figure B shows the modulated wave Sl (phase voltage SIU y SIV p S
FIG. 2C is a waveform diagram showing the relationship between IW and the triangular wave S2, and FIG. 2C is a waveform diagram showing the patterns and output voltage waveforms for PW8 of each phase. That is, in a three-phase PWM inverter consisting of switching elements 'ri-'r, as shown in Fig. 2A, the phase voltage SIU y with a waveform as shown in Fig. 2B is
To output 5IVy S1'W, see Figure 2C (a)
, (b), ().) The on/off control of each of the switching elements T1 to T6 can be performed based on the PWM patterns such as , (b), and (). When this field is on, the other is off, and by reversing one pattern, you can create the other pattern.The following explanation focuses on six switching elements. do. In addition, FIG. 2C (d) is a waveform diagram showing the output voltage (UV) voltage waveform.

In this way? The PWM pattern to be υ is ROM (01
It is stored sequentially for each minimum electrical angle division representing a bit, but
For example, the following storage methods are known.

FIG. 3 is an explanatory diagram for explaining a conventional example of a storage method for storing a PWM pattern in a ROM.

That is, it is assumed that the voltage pattern of each phase to be output is expressed as shown in FIG.
Assuming that there are bits, for example, data UOs representing a U-phase PWM pattern U1...U1023
to n, the bit position of OM, and similarly the V phase data Vo
, Vl...V 1023 to bit position D1
Also, the W phase data wO, w,...-W1o23
are respectively stored in the bit position D2. In this case, the electrical angle of 0 to 360 degrees is the ROM capacity (address: 1024
), the electrical angular resolution is 560.
degree/1024-o, which means 352 degrees. Also,
If we set it to 5 like this, five bit positions D3 to D7 remain, so we can create an output voltage pattern different from the one shown above (B
), it is possible to store just one more pattern.

Therefore, by specifying one address position, it is possible to read out the U-phase, V-phase, and W-phase patterns simultaneously and in parallel.

By the way, when using a 6-phase inverter, once a PWM pattern from 0 to 120 degrees can be obtained, a 360-degree PWM pattern can be obtained for all phases by performing predetermined logical operations. In this case, please refer to the same figure (C
), for example, a pattern for 120 degrees is created using 256 bits, and the electrical angular resolution is 120 degrees/256 = 0.
At 469 degrees, an output voltage pattern of 8 (2×4) is obtained to make effective use of the ROM. In addition, FIG. 2(B).

In (C), the ROM data is actually shown in Figure 1 (B).
It is stored in a pattern of 1" It Q # as shown in FIG. 1, but this is represented here as U, V, and W phase data.

However, according to the above storage method, the normal 8
The key to creating a three-phase pattern in a ROM is that two bit positions, namely bit positions 6 and 7 in the examples in Figure 2 (B) and (C), are not available;
The disadvantage is that the utilization rate of

[Purpose of the invention]

The present invention has been made in view of this problem, and an object of the present invention is to provide a PWM inverter control device that is inexpensive and capable of high-precision control by making effective use of ROM.

[Key points of the invention]

The key point is that the three-phase PW for a given output voltage pattern
The M pattern is stored in a predetermined bit position of the ROM according to the phase order of the three phases, is read as serial data (time series data) by a counter, etc., and the data is extracted according to the phase order and converted into six-phase parallel data. The point is that PVli control is performed by distributing the signal to each phase.

[Embodiments of the invention]

FIG. 4 is an explanatory diagram for explaining one embodiment of the PWM pattern storage method according to the present invention.

In this method, one output voltage pattern is stored in correspondence with a predetermined bit position in the ROM.
goes to bit position Do, pattern block 2 goes to bit position tDI, etc., and the number of bits in the ROM (8)
Only PWM patterns are stored. In this case, data for each phase is stored in horizontal rows in ascending order of electrical angle, as shown in Figure (B), so data for 6 phases will be stored for 1024 addresses. Therefore, if this corresponds to one period (360 degrees) of the output pattern, the electrical angular resolution of one phase is 360 degrees/(
-X 1023 )=1.056 degrees.

In addition, the data for each phase in this case is shown in the same figure (A) or (
As shown in B) (U 6- U340, Vo ~ v3
4. , W.

~W34o. In addition, the address is 1024 (0 to 1
Since there are up to 026), the remaining amount will be treated as free space. In other words, while the conventional method explained in FIG. 3 stores data for each phase in parallel for one address, this method stores data in series in correspondence with bit positions. This is intended to make effective use of ROM. However, in this case, since the PWM data of each phase is extracted as a time-series signal, separate processing is required, but this point will be described later. By storing the PWM data of each phase in series in this manner, more output patterns can be stored than at least the conventional example shown in FIG. 3(B').

FIG. 5 is an explanatory diagram for explaining another embodiment of the PWM pattern storage method according to the present invention and an example of its reading method.

That is, according to the system shown in Fig. 4, eight output patterns can be stored, but its electrical angular resolution is poor compared to the conventional example shown in pAE2 Fig.
While the conventional example is 0.469 degrees, this method stores the output cover turns for a period of 120 degrees, so the number of output cover turns is the same <8fit.
Although it is a similar type, its electrical angular resolution is 120 degrees/341
=0.352.

The storage method in the ROM in this case will be explained below. Here, the three phases of the voltage pattern of the U phase, for example,
PWM patterns of other phases are created using 60 degrees as a reference. This U-phase voltage pattern is expressed as P in Figure 5(A), and is expressed as the number of ROM addresses (1
024), PWM between 0 and 120 degrees of U phase
The data can be immediately understood from the data for the waveforms in (A, ) in the same figure, and the PWM data between 0 and 120 degrees (point 0 to point ■) of the V and W phases is 240 to 3
Between 60 degrees (points 0 to ■), 120 to 240 degrees (points 0 to
It is possible to create each from the data of point @). For example, while the U-phase data Uo at zero electrical angle can be used as is without any processing,
W phase data Vo, Wo are U phase division points 683, 342
120 in the same way below.
Data regarding the degree period (points ■ to ■) can be obtained. The PWM data thus determined is stored in the ROM as shown in FIG. Note that (B) in the same figure represents the address, and the numbers in (C) in the same figure represent the addresses (
It corresponds to the numbers 0 to 1026 in A), and is actually '
°1"' or 0" data.

Next, the reading method will be explained.

Now, 7) Correlate the zero response data to the electrical angle zero of the U phase, and use the ROM data stored as shown in (C) in the same figure below.
When reading sequentially using a binary counter or the like and making each 6 addresses correspond to the U phase, the final address 1023 becomes 1.
There will be a surplus of 341, but here is the dividing point 341 of the U phase.
The corresponding data shall be stored. In this way, the first data read from the ROM for the second time will be the V-phase data, and the next data corresponding to the U-phase will be the RO
The data generated at the M address 2 position and read out for the third time in the same way becomes the W phase data, and the data corresponding to the U phase is generated at the ROM address 1 position. When all addresses 0 to 1023 of the ROM are read out six times, the U-phase data returns to the data at the ROM address zero, one cycle is completed, and the same read operation is repeated thereafter.

That is, the data in the ROM is not fixed to one phase, but the same data is shared by all of the U, V', and W phases. Note that although the above description has been made focusing on the U phase, the same can be considered when using the ■ phase and W phase as the reference. In addition, the above is a case where the ROM capacity is 1 byte (8 x 1024), but if this is 2 bytes, the two addresses, the final address (2047) and the previous address (2046), are each The first phase of phase j- (U phase in the above example), the second phase of phase 10 (
Similarly, if the PWM data of (phase 2) is stored, the 4th time after reading the contents of the ROM 3 times, similar to the above-mentioned Iai,
You can return to the original pattern.

FIG. 6 is a block diagram showing an embodiment of the control circuit according to the present invention. In the figure, 1 is an oscillator, 2 is a rate multiplier, 3 is a binary counter, 4 is a ROM in which PWM patterns are stored, 5 is a multiplexer, and 6 is a
The leading ring counter and the closing circuit are 6-phase switching circuits.

The voltage command data given to the multiplexer 4 is RO
The bit position of M4 is selected and only the data corresponding to the desired output voltage pattern is extracted.The frequency command given to the rate multiplier 2 is changed according to the output frequency of the inverter, and the ROM data is read out. Determine speed.

Therefore, the rate multiplier 2 calculates the proportionality constant K (K < 1) defined by the frequency command data to the fixed frequency (f) given from the oscillator 1 (
K, f), a frequency signal proportional to the inverter frequency is output. This signal is counted by the binary counter 3, and the ROM 4 is addressed by its output, so that the PWM data stored in the ROM 4 is read out at a speed proportional to the inverter frequency. The output of ROλ, f4 has a pit position of 8.
If there is, there will be 8 bits, but the multiplexer 5 selects only the data at one pit position corresponding to the voltage command data, and inputs the data bit by bit to the 6-phase switch circuit B as a serial signal. On the other hand, the frequency signal from the rate multiplier 2 is counted by the hexadecimal ring counter 7, and therefore, when the 6-pit data, that is, the data of the U, V, and W phases, is collected in the 6-phase switch circuit B, the frequency signal is counted by the hex ring counter 7. , is output as a 3-phase PWM signal, and by repeating the same operation, each switching element of the f inverter circuit is controlled. Voltage pattern 8 @ class, electrical angular resolution 660 degrees/IO
24,=0.352 degrees, but by using a ROM with a larger capacity and applying the same idea as above, it is possible to obtain even more voltage patterns and higher electrical angular resolution. . For example, 8X204
If a B-bit ROM is used and the ROM bank is switched according to the frequency data as explained in Fig. 6, the electrical angular resolution is 0.352, and it is possible to obtain 16 types of PWM patterns with voltage patterns. .

〔Effect of the invention〕

According to this invention, a PWM pattern corresponding to 360 degrees of one phase is read out as serial data every 120 electrical degrees in correspondence with one bit position of the ROM, and then distributed to each phase as 6-phase differential sequence data. As a result, all bits of the ROM can be used effectively, resulting in improved ROM utilization compared to the conventional method, which has the advantage of being able to perform PWM control at low cost and with good performance. be.

[Brief explanation of drawings]

Fig. 1 is a principle diagram for explaining the principle of PWM pattern generation, Fig. 2A is a circuit diagram showing an example of a three-phase PWM inverter main circuit, and Fig. 2B is a waveform diagram showing the relationship between three-phase voltage and triangular wave. , Fig. 2C is a waveform diagram showing the PWM pattern and output voltage waveform of each phase, Fig. 3 is a waveform diagram showing the PWM pattern and the output voltage waveform.
FIG. 4 is an explanatory diagram for explaining a conventional example of a storage method for storing data in M, FIG. An explanatory diagram for explaining another embodiment, FIG. 6 is a block diagram showing an embodiment of the control device according to the present invention. Code explanation 1...Oscillator, 2...Rate multiplier, 5---= Binary counter, 4...
・Read-only memo! J (ROM), 5...-
・Multiplexer 6 phase gap circuit, 7... Ternary ring counter agent Patent attorney Akio Namiki Patent attorney Kiyoshi Matsuzaki Figure 1 Figure 3 (A) Figure 3 (C) 4-pan □-1)

Claims (1)

[Claims] 1) On/off control signals to be applied to each switching element of a pulse width modulation (PWM) inverter circuit are stored in a predetermined memory in a logic pattern of "to 1 pp, at O" (PW
A 5PWM inverter control device that stores the 5PWM inverter control device as a 5PWM inverter (M pattern) and performs control based on the stored content,
In the memory, a predetermined electrical angle of a PWM pattern of each switching element corresponding to a predetermined waveform to be output is sequentially stored in a predetermined phase order along with a predetermined bit of each address, and the stored P Vv' M pattern is A PWM characterized in that the control is performed by repeating the operation of sequentially reading data at a speed proportional to the output frequency, latching it for a predetermined number of phases, and distributing it to each switching element.
Inverter control device. 2. The PWM inverter control device according to claim 1, wherein the PWM pattern stored in the memory corresponds to one cycle of the output waveform.
Inverter control device. 6) In the PWM inverter control device according to claim 1, the PWM pattern stored in the memory is for 1/6 cycle of the output waveform, and the PWM pattern for one cycle is read out three times. A PWM inverter control device characterized by obtaining a pattern.