JPH065989B2 - Inverter PWM signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a variable voltage variable frequency (VVVF) type pulse width modulation (PWM) used for driving an electric motor, for example.
The present invention relates to a PWM signal generator for an inverter.

[Prior art and its problems]

FIG. 1 is a characteristic diagram showing the relationship between the voltage and frequency of an inverter in the conventional method.

Conventionally, as a method of generating a PWM signal of a VVVF type PWM inverter, a plurality of PWM signal patterns (which correspond to the output voltage of the inverter) are stored in advance in a read-on memory (ROM) to correspond to the inverter frequency. Then, there is a method of selecting any one of the patterns and reading the content at a speed proportional to the frequency of the inverter. In this case, in general, the number of PWM signal patterns stored in the ROM is smaller than the number of frequency modes that the inverter can take because of the limitation of the ROM capacity. Therefore, as shown in FIG. The number N is divided into even divisions, and one PWM pattern is associated with each of the divided areas. On the other hand, in the case of a VVVF type inverter for driving a motor,
Since it is necessary to have a proportional relationship between the voltage V and the frequency f, the amount of voltage change ΔVn is also constant for a constant frequency change Δfn. Therefore, when the inverter frequency moves from one region to the next and the PWM pattern, that is, the voltage pattern switches, the absolute value of the voltage change becomes the same in all frequency regions. , The voltage change rate ΔVn / Vn becomes relatively large as the frequency becomes lower, and the large current fluctuation,
There was a large torque fluctuation.

[Object of the Invention]

According to the present invention, even if the ROM capacity is the same as the conventional one, that is, the number of PWM patterns (the number of voltage patterns), the voltage pattern and the frequency domain are set so that the voltage change rate becomes constant in the entire frequency domain when switching the voltage pattern. It is an object of the present invention to make the amount of change in current constant over the entire frequency range by making the above-mentioned correspondences, and in particular to prevent large current fluctuations and torque fluctuations from occurring in the low frequency range.

[Main points of the invention]

According to the present invention, an ON / OFF control signal of a switching element which constitutes a main circuit of an inverter is pulse width modulated (PW
M) In the pattern format, the read-only memory stores the logical pattern of 1, 0, and the stored contents are sequentially read at a speed related to the inverter output frequency,
In a PWM signal generator for an inverter used for controlling the switching element, a plurality of PWM patterns are prepared corresponding to an inverter output voltage, and the PWM patterns are assigned to a predetermined frequency region of the inverter to change the frequency of the inverter. At the same time, when the PWM patterns to be read are sequentially switched, the output voltage change amount depending on the frequency when the PWM patterns are switched so that the change rate of the output voltage at the time of switching becomes the same in any frequency region. The PWM pattern is read in a different form.

That is, assuming that the amount of change in the phase voltage at the time of switching the PWM pattern (this corresponds to the voltage pattern) is ΔV, the amount of change in the phase current ΔI at that time is Here, Z is the impedance of the motor 1 phase, l is the inductance of the motor 1 phase, and f is the frequency of the inverter. Note that, of the impedance of one phase of the electric motor, the resistance component is ignored. Therefore, if ΔV / f = K ₁ (K ₁ = constant) (2), then ΔI becomes constant. However, l is constant.
On the other hand, in the VVVF inverter for driving a motor, the output voltage V and the frequency f are selected so as to be in a proportional relationship, so V = K ₂ f (K ₂ = constant) (3) (2), (3) Therefore, ΔV / f = ΔV / (V / K ₂ ) = K ₁
Therefore, the relation ΔV / V = K ₁ / K ₂ = K (K = constant) (4) holds. That is, if the voltage pattern is switched so that the voltage change rate ΔV / V becomes constant, the amount of change in current at the time of switching the voltage pattern also becomes constant. Also,
To achieve this, let N be the total number of voltage patterns,
The switching frequency of the M-th frequency region to a voltage pattern assigned of which the if _{F M F M = AR M-} 1 ...... (5). Where A is the lowest frequency, R is a constant, M is 1,
2, 3, ... N. That is, the common ratio is expressed as a geometric series of R, and this is illustrated in FIG. 2 is a characteristic diagram showing the relationship between the voltage and the frequency of the inverter according to the present invention. In addition, here, although the explanation is centered on the method in which the voltage change rate is constant when the voltage pattern is switched, in practice, the output voltage change amount can be set to a low frequency even if the entire area change rate is not always constant. By storing the voltage pattern so that it is small in the region and large in the high frequency region, the initial purpose can be sufficiently achieved.

Example of Invention

FIG. 3 is an explanatory diagram for explaining a method of storing a voltage pattern in a ROM, and FIGS. 4A, 4B, and 4C are explanatory diagrams for explaining details of a data storage method for one of the voltage patterns in FIG. FIG. 5 is a block diagram showing an embodiment of the present invention.

In Fig. 3, 2 Kbytes of ROM have V _{1 as shown
16} voltage patterns of V ₁₆ are stored. The voltage pattern in this case is such that the inverter output voltages V _n and V _n-1 are as shown in FIG. To be satisfied. In other words, the voltage values V _{1 to} V ₁₆ having the relationship shown in FIG. 2 are 0 to 1023,
The data is stored in addresses 1024 to 2047 as patterns of "1" and "0" by changing their bit positions.

FIG. 4a shows a three-phase voltage pattern taking the one voltage pattern in FIG. 3 as an example. What is stored in the ROM is 360 degrees of the U-phase voltage pattern indicated by the solid line, and other V-phase and W-phase voltage patterns are created based on this. For example, taking the voltage pattern of the 3-phase 0-120 degree period as an example, the U-phase is 0-120 degrees (-
), The V phase can be made from 240 to 360 degrees (~) of the U phase, and the W phase can be made from 120 to 240 degrees (~) of the U phase.

FIG. 4 [b] shows stored data at a certain bit position in addresses 0-1023 of one bit position (see FIG. 3) of the ROM. That is, one cycle of 360 degrees of the U-phase voltage pattern is divided into 1024 minute electrical angle sections, and the PWM pattern (for example, a sine wave and a triangular wave) calculated at the electrical angle corresponding to the decomposition points 0 to 1023 is divided. The "1" and "0" signals generated by comparison are stored according to the phase order. In FIG. 4b, the numbers 0, 68 of the minute electrical angle divisions that give "1" and "0" of the PWM signal are shown.
3, 342 ..., but the actual ROM data is the PWM pattern at the electrical angle corresponding to the number shown in the figure.
That is, it is a logical pattern of "1" or "0".

The data of address 0 stored as shown in FIG. 4 [b] is made to correspond to the electrical angle 0 of the U phase, and the ROM data is read by the binary counter below, and every 3 addresses is made to correspond to the U phase as shown in FIG. 4 c. The final address of the ROM is 1022
At the address, all three phases are read up to the same number, 340, and ROM
The data at the final address 1023 of the above corresponds to the U phase 341 (here, 0 to 120 degrees ends). Then, in the next cycle, the data of the ROM address 0 is read out again, but unlike the first read cycle, this corresponds to the next of the U phase, that is, the 341 of the V phase, and the next U As the data corresponding to the phase, the data of the ROM address 2, that is, 342 is read, and the U phase is 120 to
The pattern automatically shifts to 240 degrees. When the third reading is completed after the second reading is completed, the first data corresponding to the U phase becomes the data of the ROM address 1, and the U phase becomes 2
The pattern shifts to 40 to 360 degrees. Thus, ROM
When all the addresses 0 to 1023 of are read three times, the U-phase data returns to the data of the ROM address 0, one cycle is completed, and thereafter, it is similarly repeated. That is, the ROM data is not fixed to one phase but the same data is U,
It is used for both V and W. Although the above description has focused on the U phase, the same applies to the V phase and the W phase. In addition,
This is done in order to effectively use the memory. A specific example of the control circuit according to the present invention will be described below with reference to FIG. In the figure, 1 is an arithmetic and control unit (cpu) such as a microcomputer, 2 is an oscillator, 3 is a rate multiplier, 4 is a counter, and 5 is a counter.
Is a read-on memory (ROM), 6 is a multiplexer,
Reference numeral 7 is a ternary counter, 8 is a latch circuit, and 9 is a signal distributor.

After reading the frequency command value, the cpu 1 sets a rater value R corresponding to the inverter frequency in the rate multiplier 3 by performing a predetermined process. On the other hand, since the oscillator 2 supplies the clock of the fixed frequency f _{0 to} the rate multiplier 3, the rate multiplier 3 multiplies the fixed frequency f ₀ and the rate value R (R ≦ 1) to obtain the rate multiplier. The output signal has a frequency of Rf ₀ . This signal is a signal having a frequency proportional to the inverter frequency, and this signal is decoded by the binary counter 4 and used as the address signal of the ROM 5,
The address of is sequentially changed at a speed proportional to the inverter frequency, so that the ROM data is also read at a speed proportional to the addressing frequency. Then, the multiplexer 6 is selected from the 8 bits of the ROM output.
Only one bit position (for example, the data as shown in FIG. 4b) corresponding to the voltage pattern selection signal (channel select signal (3 bits) of the multiplexer) is selected by the ROM 5 in the three-phase latch circuit 8.
Are input as serial signals arranged in the order of the addresses. This serial signal is sequentially latched by the ternary counter 7 operated by the output of the rate multiplier 3, and when the 3-phase data is complete, it is distributed as a 3-phase PWM signal from the signal distributor 9 to the switch elements of each phase of the inverter. It
Here, the bank switching signal of the ROM and the multiplexer channel selection signal are given from cpu1 corresponding to the inverter frequency at that time.

FIG. 6 shows a processing flow chart of a cpu for generating a selection signal (ROM bank selection signal and multiplexer channel selection signal) for selecting a corresponding voltage pattern from frequency data. This program is started by a fixed-cycle interrupt signal. First, the inverter frequency setting is read (see a), the frequency to be output this time is calculated from the specified acceleration / deceleration time specified value (see b), and the program is executed at the program address corresponding to the frequency obtained as a result. Move. The transfer destination program is given a transfer instruction to the output program (subroutine) of the voltage pattern selection signal to be output when the program is executed (see C). The voltage pattern selection signal, that is, the ROM bank selection signal and the multiplexer channel selection signal are output by executing the subroutine designated by the instruction (see D).

〔The invention's effect〕

According to the present invention, when the voltage pattern is changed, the voltage pattern changing method is such that the voltage change rate is always constant in any frequency region, so that the current sudden change amount when changing the voltage pattern is constant in any frequency region. It will be constant. As a result, it is possible to eliminate a large current sudden change in the low frequency region or a small current sudden change in the high frequency region, which has occurred in the conventional method, and the number of required voltage patterns (ROM capacity) may be the same as the conventional one. It will be brought.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a characteristic diagram showing voltage and frequency patterns of a conventional inverter, FIG. 2 is a characteristic diagram showing voltage and frequency patterns of an inverter according to the present invention, and FIG. 3 is according to the present invention. FIG. 4 is an explanatory diagram for explaining an example of a voltage pattern storage method, FIG. 4 is an explanatory diagram for explaining an example of ROM data according to the present invention, FIG. 5 is a configuration diagram showing an embodiment of the present invention, and FIG. 6 is a flowchart for explaining a voltage pattern selection procedure by a microcomputer for FIG. Reference numeral 1 ... Arithmetic control unit (cpu), 2 ... Oscillator, 3 ... Rate multiplier, 4 ... Counter, 5 ... Read-on memory (ROM), 6 ... Multiplexer, 7 ... 3
Binary counter, 8 ... Latch circuit, 9 ... Signal distributor.

Claims (1)

[Claims] 1. An ON / OFF control signal for a switching element that constitutes a main circuit of an inverter is pulse width modulated (PW).
M) Inverter PWM, which is stored in a read-only memory in the form of patterns as 10 logical patterns, and the stored contents are sequentially read at a speed related to the inverter output frequency and used for controlling the switching element. In the signal generator, a plurality of the PWM patterns are prepared corresponding to the inverter output voltage, and these are assigned to a predetermined frequency region of the inverter, and the PWM pattern to be read is sequentially switched as the frequency of the inverter changes. At this time, the PWM pattern is read in such a manner that the change amount of the output voltage is changed depending on the frequency at the time of switching the PWM pattern so that the rate of change of the output voltage at the time of switching is the same in any frequency region. Characteristic inverter PWM signal generator.