JPS6074327U - clip circuit - Google Patents
clip circuitInfo
- Publication number
- JPS6074327U JPS6074327U JP16651383U JP16651383U JPS6074327U JP S6074327 U JPS6074327 U JP S6074327U JP 16651383 U JP16651383 U JP 16651383U JP 16651383 U JP16651383 U JP 16651383U JP S6074327 U JPS6074327 U JP S6074327U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- reference signal
- input signals
- generation circuits
- signal generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案回路を適用し得るノイズリダクション回
路の一例を示すブロック系統図、第2図及び第3図は夫
々従来のクリップ回路の各側を示す回路図、第4図は本
考案回路の第1実施例を示す回路図、第5図A、 Bは
夫々第4図図示回路の動作説明用信号波形図、第6図は
本考案回路の第2実施例の要部を示す回路図である。
1・・・・・・再生輝度信号入力端子、4・・・・・・
クリップ回路、6・・・・・・再生輝度信号出力端子、
7,13゜14.30・・・・・・入力端子、12.2
6.36・・・・・・出力端子、31〜35.37〜3
9・・・・・・定電流源、Q1〜QIO・・・・・・N
PNトランジスタ、C□、 C2・・・・・・コンデン
サ。Figure 1 is a block diagram showing an example of a noise reduction circuit to which the circuit of the present invention can be applied, Figures 2 and 3 are circuit diagrams showing each side of a conventional clip circuit, and Figure 4 is the circuit of the present invention. 5A and 5B are signal waveform diagrams for explaining the operation of the circuit shown in FIG. 4, and FIG. 6 is a circuit diagram showing the main parts of the second embodiment of the circuit of the present invention. It is. 1...Reproduction brightness signal input terminal, 4...
Clip circuit, 6... Reproduction brightness signal output terminal,
7,13゜14.30... Input terminal, 12.2
6.36...Output terminal, 31~35.37~3
9... Constant current source, Q1~QIO...N
PN transistor, C□, C2... Capacitor.
Claims (4)
流分に関連した基準信号を得る第1、第2の基準信号発
生回路と、該第1、第2の基準信号発生回路よりの直流
基準信号がベースに供給される第1、第2のトランジス
タと、該第1、第2の入力信号を一定レベルだiレベル
シフトする第1、第2のレベルシフト回路と、該第1、
第2のレベルシフト回路よりの信号がベースに供給され
る第3、第4のトランジスタと、第1及び第2の定電流
源と、該第3、第4のトランジスタのエミッタを該第1
、第2メトランジスタのエミッタと該第1、第2の定電
流源とに夫々接続する第1、第2の抵抗と、該第3、第
4のトランジスタのコレクタから夫々取り出された信号
を差動増幅して前記第1又は第2の入力信号のクリップ
された信号を出力する差動増幅器とより構成したクリッ
プ回路。(1) First and second reference signal generation circuits that obtain reference signals related to DC components of first and second input signals that are in opposite phases to each other; and the first and second reference signal generation circuits. first and second transistors whose bases are supplied with a DC reference signal; first and second level shift circuits that shift the first and second input signals by a constant level; 1,
third and fourth transistors whose bases are supplied with the signal from the second level shift circuit; first and second constant current sources; and the emitters of the third and fourth transistors are connected to the first transistor.
, first and second resistors connected respectively to the emitter of the second transistor and the first and second constant current sources, and signals taken out from the collectors of the third and fourth transistors, respectively. A clipping circuit comprising a differential amplifier that dynamically amplifies and outputs a clipped signal of the first or second input signal.
トランジスタである実用新案登録請求の範囲第1項記載
のクリップ回路。(2) Each of the first to fourth transistors ct is NPN;
The clip circuit according to claim 1, which is a transistor.
2の入力信号を平滑化するコンデンサと、該コンデンサ
に供給される信号に所望の電圧降下を生じさせる手段と
から夫々なる実用新案登録請求の範囲第1項又は第2項
記載のクリップ回路。(3) The first and second reference signal generation circuits include a capacitor for smoothing the first and second input signals, and means for causing a desired voltage drop in the signal supplied to the capacitor. A clip circuit according to claim 1 or 2 of the respective utility model registration claims.
2の入力信号を加算合成する第3及び第4の抵抗と、該
第゛3及び第4の抵抗の接続中点、 に一端が接続さ
れた第5の抵抗と、該第5の抵、抗の他端に一端が接続
され、その接続点より該 −第1及び第2のトラン
ジスタの各ベースに夫々直流基準信号を共通に出力する
定電流源とより構成した、実用新案登録請求の範囲第1
項又は第′2項記載のクリップ回路。 \(4) The first and second reference signal generation circuits are connected to third and fourth resistors that add and synthesize the first and second input signals, and the third and fourth resistors. a fifth resistor, one end of which is connected to a point, and one end of which is connected to the other end of the fifth resistor; Utility model registration claim 1 consisting of a constant current source that outputs a signal in common
The clip circuit according to item 1 or '2. \
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16651383U JPS6074327U (en) | 1983-10-27 | 1983-10-27 | clip circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16651383U JPS6074327U (en) | 1983-10-27 | 1983-10-27 | clip circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6074327U true JPS6074327U (en) | 1985-05-24 |
Family
ID=30364526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16651383U Pending JPS6074327U (en) | 1983-10-27 | 1983-10-27 | clip circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6074327U (en) |
-
1983
- 1983-10-27 JP JP16651383U patent/JPS6074327U/en active Pending
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