JPS607427B2 - Time-division channel continuity test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a continuity test method for communication paths in time-division communication switching network equipment.

In this type of switching network equipment, there is a conventional technique as shown in FIG. 1 as a method for testing continuity of communication paths.

FIG. 1 is a diagram schematically showing a switching network in order to explain the conventional continuity test method.
0' is a multiplexer (multiplexing device), 12 and 12' are primary channel memories, and 14 and 14' are signal receiving memories.
16, 16 are the memories 12 and 14, 12' and 1
4' control memory, 18 is a gate switch group, 20, 20' is a secondary channel memory, 22, 22
' is a memory for signal transmission, and 24, 24' are the memories 20.
22, 20' and 22' respectively, 26 and 26' are demultiplexers (multiplexing devices), A and A' are continuity test test pattern transmitting devices, B
, B' respectively indicate the test pattern receiving device for the guidance test pattern. The test data T transmitted from the continuity test test pattern transmitter A is sent to the multiplexer 1.
01 is multiplexed and accommodated in time slot i. Assuming that the content of address i in control memory 16 is i, test data T is written to the location of address i in primary channel memory 12. Since reading of the channel memory 12 is performed sequentially, the test data T is stored in the time slot J at the output and sent to the secondary channel memory 20' via the exchange point switch 18a of the gate switch group 18. It will be done. Since writing to the communication path memory 20' is also performed sequentially, the test data T is written to the address j of the communication path memory 20'. By setting the contents of the address k of the control memory 24' to j, the test data T is outputted for time slots k' at the output of the channel memory 20', and sent to the continuity test test pattern receiving device via the demultiplexer 26'. B
′ is reached. By comparing the data received by the receiving device B' with the data transmitted by the transmitting device A, a communication path memory 12, a gate switch group quantity 8, a communication shortcut memory 2
Whether it is normal or not can be determined by the continuity of the communication path for time slot j of 0'. The communication path to be tested is designated by changing the contents of the control memories 6, 24', thereby allowing continuity testing of any communication path. However, in the conventional test method as described above, a test pattern transmitting device and a receiving device for continuity testing are required. This is problematic because it needs to be prepared for each switching network.

Moreover, according to the conventional method, it is difficult to manage the continuity test using software from the central processing unit side, resulting in problems such as the inability to perform the test easily and the inability to easily change the contents of the test data.

The present invention therefore aims to overcome the above-mentioned problems of the prior art.

A feature of the present invention that achieves the above-mentioned objects is a time-division communication path in which the contents of any input time slot can be written into a signal reception memory, and the contents of the signal reception memory can be transmitted to any output time slot. In the switching network device, a return connection means capable of returning and transferring the contents of a specific output time slot to a specific input time slot corresponding to the output time slot is provided, and the contents of the signal receiving memory are transferred to the first output time slot. forwarding the contents of the first output timeslot to the corresponding first input timeslot via the loopback connection means;
transmitting the contents of the input timeslot of the input timeslot to a second output timeslot via the communication path under test in the switched network equipment, and transferring the contents of the second output timeslot to the corresponding second input timeslot. The contents of the second input time slot are transferred via the return connection means, and the contents of the second input time slot are written to the signal reception memory, and the contents written to the signal reception memory and the contents sent from the signal reception memory are combined. The purpose is to compare the conductive state of the communication path under test.

The present invention will be explained in detail below with reference to Examples.

FIG. 2 is a configuration diagram of an embodiment of the present invention. In the figure, a multiplexer 10, a primary channel memory 12, a signal receiving memory 4, a control memory 16, a gate switch group 18, a secondary channel memory 20, a signal receiving memory 22
, control memory 24, and demultiplexer 26 are similar to those shown in FIG. 1 in the slave technique. Further, in FIG. 2, reference numeral 28 indicates a control memory 30 for controlling the gate switch group 18, which is a central processing unit; 32, a central processing unit, each control memory 6, 24, 28, and a signal receiving memory 14;
C is an interface device with the signal transmission memory 22, C is a data extraction device that extracts only data of a specific time slot, and D is a data extraction device C via a return path 34.
Each figure shows a data insertion device that inserts data sent from a specific time slot into a specific time slot. Figure 3 shows the second
This is a diagram schematically representing the embodiment shown in the figure, and the operation of this embodiment will be explained below using FIG. 3.

Predetermined test data T is written at the address a of the signal receiving memory 22 according to a command from the central processing unit 30 shown in FIG.

As is well known, this signal reception memory 22 can be accessed by all three central processing units. If the content of address i in the control memory 24 is a, test data T
is the time slot i at the input of the data extraction device C.
be accommodated in. In this case, the data extraction device C extracts only the data of time slot j and passes the data of other time slots to the demultiplexer 26. The test data T extracted by the data extracting device C is transferred to the data inserting device D via the return path 34. Data insertion device D is configured to insert data returned from data extraction device C into time slot i. Therefore, at the output of the data insertion device D, the test data T is accommodated in the time slot i, and the data from the multiplexer 10 is accommodated as is in the other time slots. By setting the contents of address i in the control memory 16 to j, the test data T
is written at address i in the primary channel memory 12. Thereafter, operating in exactly the same manner as in the prior art of FIG. 1, test data T is stored in time slot k' at the output of secondary channel memory 20'. The data extraction device 〇 extracts the data of only the time slot k, whereby the test data T is extracted and transferred to the data insertion device D' via the return path 34'. The data insertion device inserts the data from the data extraction device C' into the time slot k', so that the test data T is accommodated in the time slot k at the output of the data insertion device O. By setting the content b of the address k of the control memory 16', the test data T is written to the address b of the signal receiving memory 14'. The contents of this signal receiving memory 14' are stored in the central processing unit 30 (second
), the central processing unit 30
The content of the address b of the signal receiving memory 14', that is, the test data T, is read in response to a command from the address b of the signal receiving memory 14', and this is compared with the test data written to the address a of the signal transmitting memory 22. 12. It is possible to test whether the continuity of the communication path related to time slot i of the gate switch group 18 and the communication path memory 20' is normal or not. The communication path to be tested, ie, the time slot, is designated by changing the contents of the control memories 16', 24', thereby allowing continuity testing of any communication path. Although the example in FIG. 3 shows the case of a continuity test between different switching networks sandwiching the gate switch group 18, this test can also be performed on communication paths in the same switching network. As explained above, according to the system of the present invention, only the return connection means, that is, the data extraction device C, the return path 34, and the data insertion device D in the above embodiment, are received at the input/output portion of the switching network. , there is no need to provide a special continuity test test pattern transmitting device and receiving device. When conducting tests at the time of installation or expansion of a switching network, continuity tests can be performed using only the switching network equipment under software control from the central processing unit without installing extra test equipment. . Furthermore, since the continuity test can be managed by software, the test operation becomes simple and the test can be performed reliably. Furthermore, since arbitrary test data can be created by the central processing unit, tests can be diversified and reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a conventional test system, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a schematic diagram of the embodiment of FIG. 10, 10'... multiplexer, 12, 12', 20
, 20'...Call path memory, 14, 14'...
...Signal reception memory, 16, 16', 24, 24',
28...Control memory L 18...Gate switch group, 2
2, 22'... Memory for signal reception, 26, 26'... Demultiplexer, 30... Central processing unit, 34, 34'
...turning passage, C,〇...data extraction device, D,〇...data insertion device. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In a time-division channel switching network device in which the contents of any input time slot can be written to a signal reception memory and the contents of the signal reception memory can be sent to any output time slot, A return connection means capable of returning the contents to a specific input time slot corresponding to the output time slot is provided, and the contents of the signal transmission memory are sent to the first output time slot. The contents of the first input time slot are transferred to a corresponding first input time slot via the loopback connection means, and the contents of the first input time slot are transferred to a second output time slot via the communication path under test in the switched network equipment. The content of the second output time slot is transferred to the corresponding second input time slot via the loop connection means, and the content of the second input time slot is transferred to the signal receiving memory. and comparing the contents written in the signal reception memory with the contents sent from the signal reception memory to check the continuity state of the communication path under test. Road continuity test method.