JPS6073469A - Decision making system for analog signal - Google Patents

Abstract

PURPOSE:To decide the mutual relation between a pulsating analog signal and a reference level on the basis of probability regardless of the output level of the analog signal by deciding whether the input analog signal is within a range centering the reference level by the counted value of a counting means within a specific period. CONSTITUTION:The input analog signal AS is sampled by a sampling circuit 1 with a sampling signal SP of specific frequency to obtain a time-series sampled analog signal ASP. Then, a synchronizing signal SYS with a period of a specific observation time (t) is added by a synchronizing signal superposing circuit 2 to obtain a measurement signal ASP'. Counters 7 and 8 count the number of pulses of the analog signal which are not within the specific range between an upper- limit and a lower-limit level based upon the reference level as the center. The 3rd slicing circuit 6, on the other hand, generates an output pulse T3 when the sampled analog signal ASP is larger than the specific level (a) and the value of the 3rd counter which counts said pulse indicates the total number of samples.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention describes the relative relationship between an analog signal whose waveform amplitude has meaning as information and a reference level for its determination by J,
This invention relates to an analog signal determination method that determines lJ and determines the relative relationship, and in particular, relates to an analog signal determination method that determines the relative relationship by measuring the probability that the analog signal is within or outside a predetermined level range centered on a reference level. 3 [Background of AI, Prior Art and Problems] In amplitude-modulated analog signals, the amplitude has meaning as information, so it is important to determine the magnitude of the amplitude. Generally, as a method for determining the magnitude of this amplitude, as shown in Fig. 1, a predetermined threshold level SL is set as a reference level, and the relative relationship with the input analog signal AS is determined. The magnitude of the amplitude is determined. However, since the amplitude-modulated analog signal actually causes pulsations as shown by the dotted line in Figure 1, a range of a constant width W centered around the threshold level S H is set, and the range is set from the upper limit level SL'H to the lower limit level. If the analog signal As falls within the SLL, it is determined that the analog signal AS is information indicating the reference level. Setting such a reference level to a certain value is extremely important because it serves as a reference for determining the level of an analog signal. In particular, when a large amount of information is set for the amplitude of an analog signal, the amplitude levels at which each piece of information is set are close to each other, and therefore the corresponding reference levels must also be close to each other, making it impossible to maintain the constant width W mentioned above. Therefore, a reference level setting value is required. Setting the reference level of a signal tester that tests the level of most analog signals requires precision, and a highly accurate method for determining the reference level is required. In the above case, the standard level is judged to be good or bad, but conversely, it is assumed that the reference level is correct, and it is also necessary to judge whether the analog signal level is correct. In order to determine the reference level or analog signal level, it is sufficient to measure the relative relationship between the reference level and the analog signal level.

As mentioned above, since analog signals pulsate, combined with the narrow fixed width mentioned above, there is a problem that it is rare for all such analog signals to fall within a fixed width centered on the reference level, making it difficult to judge. there were.

[Object of the Invention] An object of the present invention is to provide an analog signal determination method that can easily determine the relative relationship between an analog signal and a reference level.

[Structure of the invention]

In order to achieve the above object, the present invention includes means for sampling an input analog signal, means for detecting whether or not the sampled signal is within a range centered on a predetermined reference level; means for counting the presence of a sampled signal within or outside the range, and the input analog signal is within a range centered on the reference level by the count of the counting means over a predetermined period of time. It is characterized by determining whether or not.

[Embodiments of the invention]

FIG. 2 is a block diagram of one embodiment of the present invention.

In the figure, l is a sampling circuit that samples the input analog signal AS with the sampling signal SP;
Reference numeral 2 denotes a synchronization signal providing circuit, which applies a synchronization signal sys indicating the measurement period of the input analog signal ASP sampled by the sampling circuit 1 to the sampled analog signal ASP; 3 is a synchronization signal separation circuit; The synchronization signal sys is separated from the measurement signal ASP' (synchronization signal sys added to the sample analog signal ASP) from the signal generation circuit 2, and the sample analog signal ASP between the synchronization signals SYS is sent to a subsequent stage as a signal to be measured. 4 is a first slice circuit, which supplies an upper limit threshold level S L based on the sample analog signal ASP and the reference level S H.
5 is a second slice circuit which outputs the first pulse TI when the sample analog signal sequence ASP is larger than the upper limit level S L H. The second pulse T2 is output when the sampled analog signal ASP is smaller than the F limit threshold level SLL.

6 is a third slicing circuit which slices the No. 1 sample analog signal ASP at a predetermined level a and converts the sample analog signal into a third pulse T3; 7. '8.9
are the first. Second. a third counter, respectively a first .
Second. Third slice circuit 4, 5, 6 . output pulse T
I, T2. It counts T3 and is reset by the reset signal of the synchronization signal separation circuit 3. Next, regarding the operation of the embodiment configuration shown in FIG.
The explanation will be based on waveform diagrams of each part of the diagram configuration.

In the following example, a reference signal having a DC level of a specific value is input as an input analog signal, and it is determined whether the set reference level SL (i.e., upper and lower threshold levels SLH, 5LL) is set correctly. An example will be explained below.

First, the input analog signal AS of a specific level is converted into a sampling signal SP of a predetermined frequency in the sampling circuit 1.
1 time series sample analog signal ASP
is converted to Next, from a synchronization signal generation circuit (not shown),
A synchronizing signal SYS having a period of a predetermined observation time t is applied by the synchronizing signal applying circuit 2 to become a measurement signal ASP' (see FIG. 3). As a result, the sample analog signal ASP sandwiched between the synchronization signal SYS becomes the measurement target.

The period t sets the observation time. The measurement signal ASP' is input to the synchronization signal separation circuit 3, where the synchronization signal SYS is separated, thereby generating a reset signal. Second. Reset the third counter 7.8.9. On the other hand, the synchronization signal separation circuit 3 sends a separated time series sample analog signal ASP of the synchronization signal SYS to each slice circuit 4, 5.
．． given to 6. The first slice circuit 4 generates an output pulse T when the sample analog signal ASP exceeds the upper limit level SLH, and the first counter 7 counts the number of output pulses T1. The second slice circuit 5 generates an output pulse T2 when the sample analog signal ASP becomes lower than the lower limit level SLL, and the second counter 8 counts the number of output pulses T2. Therefore, the first counter 7 counts the number of sampled analog signals that are above the upper limit level SLH, and the second counter 8 counts the number of sampled analog signals that are below the lower limit level SLL.
8, the number of existing analog signals outside the range of the upper limit level and lower limit level centered on the reference level is counted. On the other hand, the third slice circuit 6 outputs an output pulse T when the sample analog signal ASP is higher than the predetermined level a.
3 occurred.

An output pulse T3 is generated for each sample analog signal ASP, and the value of the third counter 9 that counts this pulse indicates the total number of samples. When the counting for one observation time t is completed in this way, the first counter 7 has a number of samples equal to or higher than the upper limit level, and the second counter 8
The number m of samples below the lower limit level remains in the third counter 9, and the total number n of samples remains as a count value in the third counter 9. Therefore, the probability that the analog signal AS exists outside the upper and lower limit level ranges is (J+m)/n, and the relative relationship between the analog signal As and the reference level SL becomes clear.

In Figure 9, this probability is (3+3)/16-about 37%. Similarly, the reference level (JII, upper and lower limit levels) is slightly changed, similar measurements are made, and the reference level with the lowest probability of being outside the range is set as the optimal reference level.

Conversely, if similar measurements are performed using an analog signal actually used as the input analog signal AS, distortion or level drop in the analog signal can be detected.1For example, it can be used to adjust the gain of an AGC circuit. .

FIG. 4 is a circuit diagram of an embodiment of the synchronization signal input circuit configured in FIG. 2. In FIG. 4(A), a synchronization signal SYS is input to the base of the transistor Tr, a sample analog signal is input to the collector of the transistor Tr via a capacitor C, and the measurement signal ASP is output from the collector of the transistor Tr.
It is configured to obtain '. The operating point of this collector output is determined by the ratio of resistors R1 and R2 connected to the collector and emitter of the transistor Tr, respectively.
Therefore, the reference level of the sample analog signal is Vcc-R
+/(R1+R2,). Furthermore, R.A.

RB is a bias resistance of the transistor Tr.

FIG. 4(B) shows another embodiment, and the difference from the configuration in FIG. 4(8) is that the resistor Rl connected to the emitter of the transistor Tr is omitted, and the resistor Rl connected to the collector is omitted. The point is that the resistor R2 is divided into resistors R2' and R2'' and configured in an emitter follower type.

In FIG. 4(B), if the analog signal ASP is input to the collector of the transistor Tr via the capacitor C, then
A signal of the same magnitude as the Kugata signal is present at the collector output through the resistor R.
The DC level obtained by dividing the power supply voltage by resistors R2' and R2'' is superimposed as a reference level.This collector output is superimposed with the DC level obtained by dividing the voltage by resistors R2'' and R2'', so the analog signal The amplitude does not change and can be transmitted to the next stage while being preserved.

FIG. 4(C) is a circuit for amplifying the collector output of FIG. 4(A) or (B). That is, when the width needs to be increased due to the necessity of the subsequent circuit, the measurement signal ASP' is configured to be input to the base of the transistor Tr via the capacitor C.
An amplified output is obtained from the collector of the transistor Tr. In this case, the measurement signal ASP' is input as an absolute value with respect to ground.

Since all Vcc is applied between the collector and emitter when the base of the transistor Tr is cut off, a voltage in phase opposite to the voltage drop across the resistor RL due to the output current is applied between the collector and emitter, eliminating the need for an emitter resistor.

In the two embodiments, the sampling signal SP is shown as a modulated wave with a predetermined frequency, but it may also be a summing pulse signal with a predetermined period. Similarly, a synchronizing signal is used to specify the observation time, but this may be replaced with a timer to control the counting time of the counters 7, 8, and 9. In this case.

Synchronization signal providing circuit 2. The synchronizing signal A11 circuit 3 is unnecessary.

Furthermore, the configuration of the embodiment shown in FIG. 2 can be completely digitalized. That is, the sampling circuit 1 of the configuration shown in FIG. 2 is an analog-to-digital conversion circuit, converts an input analog signal into a digital value at a predetermined sampling pulse timing, converts one time-series encoded signal to fL, and further slices circuits 4, 5, . 6
are changed to comparators respectively, and the synchronizing signal providing circuit 2. It may be constructed by removing the synchronizing signal separation circuit 3. In this case, if the outputs of the comparators 4 and 5 are set to output a number of pulses corresponding to the difference between the C upper limit and lower limit levels, more detailed determination can be made.

That is, not only the number of samples outside the range between the upper and lower 1; ■ levels, but also the distance from the sample analog signal outside the range can be measured, making detailed measurement possible.

〔Effect of the invention〕

As explained above, according to the present invention, there are provided a means for sampling an input analog signal, a means for detecting whether or not the sampled signal is within a range centered on a predetermined reference level; means for counting the presence of a sampled signal within or outside the range, and determining whether or not the input analog signal is within a range centered on the reference level by the count of the dI counting means over a predetermined period of time; This method has the advantage that the relative relationship between the pulsating analog signal and the reference level can be determined based on probability. Furthermore, since the analog signal is sampled and treated as a time-series signal, This also has the effect of making it possible to make a determination without being influenced by the magnitude of the output level of the analog signal.

In particular, it is effective in determining whether or not the setting of a reference level is acceptable, which has recently become more rigorous, and greatly contributes to improving the performance of testers.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the relationship between analog signals and reference levels that are the subject of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a waveform diagram of each part in the configuration of FIG. 2, and FIG. 4 2 is a main part circuit diagram of the configuration shown in FIG. In the figure, 1-sampling circuit, 4', 5. 6-slice circuit (detection circuit),
7,8.9-Counter (counting circuit) Patent applicant Fujitsu Co., Ltd. Representative patent attorney Akira Yamatani Eisai 1112] ′:A″ 21 3rd entry 3

Claims (1)

[Claims] means for sampling an input analog signal; means for detecting whether the sampled signal is within a range centered on a predetermined reference level; and the presence of a sampled signal within or outside the range. and determining whether or not the input analog signal is within a range centered on the reference level based on the count value of the counting means during a predetermined period. method.