JPS6070374A - Surge receiving and measuring control circuit of trouble point locating apparatus - Google Patents

Abstract

PURPOSE:To attain to enhance the reliability of locating operation accuracy, by comparing the time interval between trouble surge and succeeding surge with a predetermined set time and controlling an opening and closing surge gate corresponding to the compared result. CONSTITUTION:After trouble surge is received, counting is started by a counter circuit 5 and, in cooperation with a trouble surge detector 2, the time interval between the trouble surge and the succeeding surge is compared with a predetermined set time by a comparator 21 and the possibility of trouble surge is performed corresponding to the compared result by a memory circuit 3. With respect to opening and closing surge, an opening and closing surge input gate 24 is opened by a breaker opening and closing order signal 7a obtained directly before the opening and closing surge and, after a time capable of generating the opening and closing surge is elapsed, the gate 24 is closed. Therefore, even if non-trouble surge arrives during a time before the signal 7a is obtained directly before the trouble surge and the opening and closing surge, erroneous locating operation is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a surge reception measurement control circuit for a power line failure point locating device that uses failure surges and switching surges to locate failure points in power transmission lines.

As is well known, failure point locating devices using fault surges have been widely put into practical use, and failure point locating devices using fault surges and opening/closing surges are also known techniques. A method has already been proposed for locating the fault point of a power line by capturing a large number of surges, including fault surges and open/close surges, that occur during power line accidents. The purpose is achieved by performing surge measurements independently at each location, and has the advantage that a synchronization line, such as a micro line or a power line carrier line, which handles extremely accurate time (on the order of μS), which was conventionally required, is not required.

By the way, these devices are designed to locate fault points by associating fault surges and switching surges with the operation of power line fault detectors and measuring the time interval between two surges. This is based on the assumption that no surges other than fault surges and switching surges will occur between the time the switching surge is received and the switching surge is received. However, the above assumption does not always hold, and especially when assuming an accident caused by lightning, it is conceivable that a visiting lightning will occur for a short period of time at a point slightly R1γ after a lightning flash accident. ,
In such a case, the location will be erroneously located, and the reliability of the location accuracy will decrease.

For this reason, recently, applications have been filed first (%Application No. 55-99339).
After receiving the fault surge, the counting circuit starts counting, and if the fault detector operates within the set time, it will be considered as a fault surge and the count will start. Otherwise, the received surge is treated as a non-failure surge and the counting circuit is reset to prepare for the next failure. Also,
Regarding the circuit breaker opening/closing surge, after receiving the fault surge,
A surge receiver that opens the opening/closing surge input dart only between the shortest and longest arrival times of the opening/closing surge, and when a surge is detected within that time, it is regarded as an opening/closing surge, and the counting circuit is stopped by the detection signal. A measurement circuit is proposed. Finally, this circuit allows reception of circuit breaker opening/closing surges only between the shortest and longest possible arrival times, and surges at other times are not treated as opening/closing surges. However, the shortest and longest time that a switching surge can arrive is due to a ground fault,
Since it is not constant depending on the type of failure such as short circuit, it is necessary to determine the shortest and longest times for various types of failures and set the shortest and longest times so that switching surges can be caught for any type of failure.

A failure point locating device that uses fault surges and switching surges is installed at both ends of the power line to capture fault surges and switching surges and locate the fault point, but depending on the power line system configuration and the location of the fault point. Since the circuit breakers at both ends of the power line operate at different times, the switching surge to be utilized is made to catch the circuit breaker that opened or closed earlier. Therefore, since the shortest and longest times of switching surge input darts are determined by the type of fault mentioned above, the power line system configuration, and the location of the fault point, these conditions should be taken into consideration, and switching surge input darts should be set during this period. I'm trying to open the input dart.

Therefore, hypothetically, if the power line failure corresponds to the longest time, the switching surge input dart will open at the shortest time because it will open from the shortest time set first. If a non-failure surge is input during the trench that captures the opening/closing surge corresponding to the longest time since then, misorientation will occur.

This invention was made in view of the above circumstances, and in the event of a failure or surge, after receiving the signal, a counting circuit starts counting, and in conjunction with an accident detector, a predetermined time interval between subsequent surges is determined. is compared with πH (fixed time), and it is determined whether it is a fault surge or not according to the comparison result.The circuit breaker switching surge is obtained just before the switching surge, and the circuit breaker switching surge is detected by the interrupter switching command signal. By opening the input dart and closing the switching surge input dart after a period of time during which a switching surge could occur, a non-fault condition occurs between the fault surge and the breaker opening/closing command signal obtained immediately before the switching surge. It is an object of the present invention to provide a surge reception measurement control circuit for a failure point locating device that can improve the reliability of locating accuracy without erroneous locating even when a surge arrives.

An embodiment of the present invention will be described below with reference to the drawings. In the fault point locating device that is the object of this invention, when detecting fault surges and opening/closing surges of the surge reception type, there is a means for determining fault surges in conjunction with an accident detector, and a means for measuring surge detection points. Substitute observation point (The surge detection point is the time of the surge rise point υ, but in reality the rise point υ is often unknown due to noise etc.)
Although various methods have been proposed in the past for these means, and they are not the main part constituting this invention, their explanation will be omitted here. Furthermore, the fault point locating device that is the object of the present invention is installed at both ends of a monitoring line, and when the time interval between a fault surge and a switching surge is widened, it is possible to transmit the measured values at both ends and the transmitted measured values. The arithmetic device that calculates the failure point by computing is also not a main part of this invention, so its explanation will be omitted.

FIG. 1 shows a surge reception measurement control circuit of a failure point locating device according to the present invention. The same circuit is set at both ends of the monitoring line, and since it is the same circuit, only one circuit will be explained. In Fig. 1, 1 is a surge input terminal, 2 is a fault surge detector, 3 is a fault surge detection signal storage circuit that stores the fault surge detection signal, 4 is a clock pulse generator, and 5 is a switch from the fault surge detection to opening/closing surge. A counter circuit counts the time interval until detection, and 6 is an open side value storage circuit that stores the value counted by the counter circuit 5. Further, 7 is a breaker opening/closing command signal terminal, 8 is a modulation circuit for converting the breaker opening/closing command signal into an appropriate modulation signal, and 9 is a breaker opening/closing command signal modulated by the modulation circuit 8. 1o is a transmission line for transmitting a breaker opening/closing command signal at the other end that is similarly modulated by the locating device at the other end, and 11 is a transmission line. This is a demodulation circuit that demodulates the modulated signal transmitted through the path 1o. 12 is for the time when opening/closing surge may occur while inputting the breaker opening/closing command signal.
13 is an opening/closing surge detector; I4 is an opening/closing surge detection signal storage circuit for storing the opening/closing surge detection signal; 15 is an opening/closing surge detection signal storage circuit for storing the opening/closing surge detection signal; A reset signal input terminal 16 is a reset signal input terminal due to failure of the accident detector, which is input manually after counting the time interval or from an arithmetic unit (not shown). Furthermore, 21, 22, 23.24 are AND circuits (sometimes called keto circuits), 25.26
is an OR circuit, and 27.28 is an inverter circuit.

Above, the AND circuit 2 adds the output of the fault surge detection signal storage circuit 3 inverted by the inverter circuit 27 and the output signal of the fault surge detector 2, and when the AND condition is satisfied, outputs a "1" level signal as a fault. This signal is supplied to the surge detection signal storage device 3. Further, the AND circuit 22 receives the output signal of the clock pulse generator 4, the output signal of the failure surge detection signal storage circuit 3, and the output signal 14b of the switching surge detection signal storage circuit 14 inverted by the inverter circuit 28, and the AND condition When is satisfied, “1”
``level signal is added to the counter circuit 5.Next, the AND circuit 23 receives the output signal of the failure sir/zo detection signal storage circuit 3, the breaker opening/closing command signal inputted from the input terminal 7, and the signal supplied from the demodulation circuit 11. Either one of the opening/closing command signals 2)) is supplied through the OR circuit 25, and when the AND condition is satisfied, a 1# level signal is supplied to the opening/closing surge gate signal generating circuit 12. Furthermore, the AND circuit 24 outputs the output signal of the opening/closing surge/dart signal generation circuit 12 and the output signal of the opening/closing surge detector 1.
3 is supplied, and when the AND condition is satisfied, an "IH level signal" is added to the switching surge detection signal storage circuit 14.

On the other hand, the OR circuit 26 is connected to the reset signal input terminal 15°16.
When a reset signal is applied, a ``1#'' level signal is supplied to the failure surge detection signal storage circuit 3, counter circuit 6, and opening/closing surge detection signal storage circuit 14 to reset each of them.

Next, the operation of the surge receiving circuit of the failure point locating device configured as described above will be explained with reference to the timing chart shown in FIG. In FIG. 1, parts corresponding to those in FIG. 2 are given the same reference numerals.

In FIG. 1, when the surge shown in FIG. 2 is input to the surge input terminal 1, this surge 1a is supplied to the fault surge detector 2 and the opening/closing surge detector 13. Now, the fault surge 1 al is supplied to the fault surge detector 2, and when the surge level reaches the detection level L, the fault surge detector 2 outputs the fault surge detection signal 2a, and this signal is sent to one input terminal of the AND circuit 21. added to.

At this time, the output signal "0" level of the failure surge detection signal storage circuit 3 is inverted by the inverter circuit 27 and is supplied to the other input terminal of the AND circuit 2 as a '1' level. Since the output signal of the AND circuit 21 is at the O" level when the fault surge detector 2 is not detecting the fault surge, the output signal of the fault surge detection signal storage circuit 3 is also at the P0" level. Therefore, the inverter circuit 27 The output signal of is at the '1' level, and the AND circuit 21 is always in the standby state.

Therefore, as mentioned above, when the fault surge Jul is detected by the fault surge detector 2 and the surge detection signal 2a is supplied to the AND circuit 21, the AND circuit 21 uses this as the fault surge detection signal 2b to open the dart. The surge detection signal storage circuit 3 stores it. Since the output signal 3a of the failure surge detection signal storage circuit 3 changes from the ``0'' level to the ``1# level,'' the output signal 3b of the impurity circuit 27 changes from the ``1# level to the tOH level. Nasi,
The gate of the AND circuit 2I is closed and the subsequent non-fault surge 1a2. The storage of the surge detection signal for the opening/closing surge 1a3 is locked.

Furthermore, when the output signal 3a of the failure surge detection signal storage circuit 3 reaches the 1" level, the AND circuit 23 is put into a standby state, and the breaker opening/closing command signal input terminal 7 or the breaker opening/closing command signal of the other end is transmitted to the transmission path lθ and When supplied to 25 via the demodulator 1, a breaker opening/closing command signal 7a is output from the OR circuit 25, and this signal 7a is
3. Then, the AND condition is satisfied and the AND circuit 23 supplies the breaker opening/closing command signal 7b to the opening/closing surge gate signal generation circuit 12. When a new breaker opening/closing command signal is input to the breaker opening/closing command signal input terminal 7, the modulation circuit 8 converts the signal into an appropriate modulation signal, and transmits it to the locating device at the other end (not shown) via the transmission line 9. be done.

In the location device at the other end, this signal is similarly used as a breaker opening/closing command signal via a demodulation circuit.

Next, the switching surge gate signal generation circuit 12 detects switching surges r- only during the time ta when switching surges can occur after the above-mentioned switch 11j [instrument closing command signal 7b is supplied]
) A signal 12m is supplied to the AND circuit 24. For this reason,
While the switching surge detection dart No. 1h 12a is at the "ln level," the AND circuit 2 is activated only during the time ta when the switching surge can occur after the breaker opening/closing command signal 7b is input.
4, the circuit breaker switching command signal 7b of the switching surge detection gate signal 12 & of the detection signal 13a of the surge 1a input to the switching surge detector 13 is inputted to the switching surge detection gate signal 12& to put the circuit breaker switching command signal 7b into the standby state. When the 1" and 1 closed two-judge 1a3 detected between 1 and 1 are supplied to the AND circuit 24, the AND condition of the AND circuit 24 is satisfied at this point, and the open/close signal 13b outputs the open/close ZAZ detection signal. Therefore, the output signal 14a of the switching surge detection signal storage circuit 14 is stored between the time 1a between the breaker and the input of the command signal 7b, when the switching surge may occur, after the fault surge is detected and stored. Even if the switching surge detection unit 13 detects a surge during removal, the "θ" level state continues, and if a surge is detected between the input of the breaker opening/closing command signal 7b and the time t8 when a switching surge may occur, the level is "1".
'' level. t,b switching surge detection signal storage circuit 14 detects fault surge IIL1, breaker opening/closing command signal 7b
It does not operate in the case of a non-fault surge Ja2 that occurs before the input of , but a switching surge occurs after the breaker opening/closing command signal 7b is input, and the surge detected between time t8 is regarded as the switching surge 1a3, and the circuit operates. Therefore, the output signal 14a of the switching surge detection signal storage circuit 14 is the switching surge detection signal 1a.
3f: The output signal 14b of the inverter circuit 28 is at the '0# level until it is input, and when the trench opening/closing surge Ja3 is input, it becomes the '1'' level and is supplied to the inverter circuit 28. From this, the output signal 14b of the inverter circuit 28 is The opening/closing surge detection signal is input to the storage circuit 14.
When the opening/closing surge 7a3 is input at the "0" level, it becomes the "0" level.

On the other hand, the AND circuit 22 receives the output signal 3a of the failure surge detection signal storage circuit 3, the signal 14b obtained by inverting the output signal 14a of the switching surge detection signal storage circuit 14 by the inverter circuit 28, and the output signal of the clock pulse generator 4. 4
a has been added. The AND circuit 22 outputs the fault surge detection signal storage circuit 3 as the detection signal 26 of the fault surge Jal.
is memorized and the output Itami changes from the O" level to the "1" level. Until the switching surge Ja3 is stored in the switching surge detection signal storage circuit 14 (the output signal of the inverter circuit 28 reaches the "0" level). The counter circuit 5 is supplied with a signal 4b synchronized with the clock pulse 4a supplied by the 171 clock pulse generator 4.

Therefore, in this counter circuit 5, the fault surge 1a
1 is stored in the failure surge detection signal storage circuit 3, and then the switching surge 7a3 is stored in the switching surge detection signal storage circuit 14.
, +1, the clock pulses 4b are counted, and the time interval from the detection of the fault surge 111H to the detection of the opening/closing surge 1a3 is counted.

The counted value of this counter circuit 5 is stored in a measured value storage circuit 6.

This completes the operation of counting the time interval between the fault surge 1a1 and the opening/closing surge 1a3, but in this case, the power line fault detector at the reset signal input terminal I5 does not operate within the set time after the surge is detected. If the surge is determined to be a non-fault surge and a reset signal is input, or if a reset signal is input manually or from an arithmetic device to the reset signal input terminal 16 after the measurement operation is completed, the entire OR circuit 26 is passed through and the fault signal is input. A reset signal 15g is supplied to the surge detection signal storage circuit 3, the opening/closing sir/zo detection signal symbol storage circuit 14, and the measured value storage circuit 6, and the device is brought into an initial state and placed in a standby state for the next surge input.

With such a configuration, after a fault surge is detected and stored, the input gate of the AND circuit 21 is closed by the output signals of the fault surge detection signal storage circuit 3 and the inverter circuit 27, and the subsequent non-fault surge is closed. Surge, opening/closing surge is locked.

Furthermore, regarding switching surges, it is possible to prevent accidental surges and breaker switching by setting the AND circuit 24 in a standby state only during the time ta when switching surges can occur from the breaker opening/closing command signal input obtained immediately before the occurrence of switching surges. In order to prevent the switching surge detection signal storage circuit 14 from operating due to a non-fault surge that occurs before the input of the switching command signal, it is possible to prevent the switching surge detection signal storage circuit 14 from operating due to a non-fault surge that occurs before the input of the switching command signal. The time interval between a failure surge and an opening/closing surge can be reliably measured without measuring the interval.

1, the breaker opening/closing command signal at the own end is modulated by the modulation circuit 8, and transmitted to the location device at the other end via the transmission line 9, and the breaker opening/closing command signal at the other end is also sent to the demodulation circuit via the transmission line 10. 10, it is possible to reliably capture the opening/closing surge of the one that opens and closes earlier, which is to be utilized, among the opening/closing surges of both circuit breaker.

In addition, since the transmission line 9-10 for the breaker opening/closing command signal is handled for several milliseconds to an hour, it is similar to the micro line or power line carry-in line used for the return signal line of a conventional surge receiving locator. does not handle extremely accurate time (about μ8). For this reason, it cannot be said that a simple and inexpensive transmission line is of any use. Further, the present invention is not limited to the embodiments described above and shown in the drawings, and it goes without saying that various modifications can be made without changing the gist of the invention.

As described above, according to the present invention, when a fault surge occurs, the surge receiver starts counting in the counting circuit, and in conjunction with the busy accident detector, compares the time interval between subsequent surges and a predetermined set time. Then, it is determined whether there is a fault surge or not according to the comparison result, and in the case of a switching surge, the circuit breaker opens and closes according to the breaker opening/closing command signal obtained just before the switching surge. By fully closing the opening/closing surge input dart after a certain period of time has elapsed, even if a non-fault surge arrives between the fault surge and the breaker opening/closing command signal obtained immediately before the switching surge, misorientation will not occur. It is possible to provide a surge reception measurement control circuit for a failure point locating device that can improve the reliability of locating accuracy without having to do so.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of a surge reception measurement control circuit of a failure point locating device according to the present invention, and FIG. 2 is a timing diagram shown to explain the operation of FIG. 1. 1... Surge input terminal, 2... Failure surge detector,
3... Failure surge detection signal storage circuit, 4... Clock pulse generator, 5... Counter circuit, 6... Measurement candy storage circuit, 7... Breaker opening/closing command signal input terminal, 8... ...Modulation circuit, 9, 10...Transmission line, 11...
・1 sorrow circuit, 12... Opening/closing surge detection signal storage circuit, 13... Opening/closing surge detector, 14... Opening/closing surge detection signal storage circuit, 15.16... Reset signal input terminal, 21-24 ...AND circuit, 27°28...
Inverter circuit, 25.26...OR circuit.

Claims (1)

[Claims] In a fault point locating device that utilizes the fact that a fault surge that occurs when a power line fault occurs occurs before a switching surge due to the operation of circuit breakers at both ends of the faulty power line, there is provided a fault surge detector that detects a fault surge from an input signal, and an input signal. a switching surge detector for detecting switching surges in the signal; outputting a signal of a predetermined length of time according to the output signal of the failure surge detector and a breaker switching command signal from the own end or the other end; means for outputting only switching surges detected within this time; counting is started by the first fault surge detected by the fault surge detector; counting is ended by switching surges detected within the predetermined time; What is claimed is: 1. A surge reception measurement control circuit for a failure-Mlk point locating device, characterized in that it is equipped with a counter.