JPS6066453A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS6066453A
JPS6066453A JP58174573A JP17457383A JPS6066453A JP S6066453 A JPS6066453 A JP S6066453A JP 58174573 A JP58174573 A JP 58174573A JP 17457383 A JP17457383 A JP 17457383A JP S6066453 A JPS6066453 A JP S6066453A
Authority
JP
Japan
Prior art keywords
lead
circuits
lead pins
hybrid integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58174573A
Other languages
Japanese (ja)
Inventor
Tadayoshi Takahashi
忠義 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58174573A priority Critical patent/JPS6066453A/en
Publication of JPS6066453A publication Critical patent/JPS6066453A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To form the terminals of circuits to be insulated mutually with a lead frame, and moreover to secure the necessary insulating distance between the terminals at manufacture of a hybrid integrated circuit by a method wherein lead pins of two pieces interposing lead pins not to be connected to the lead frame between them are utilized. CONSTITUTION:Wiring conductors 2 are formed according to printed thick films on an insulating substrate 1 consisting of ceramics, and circuit parts are soldered to construct circuits. A photo coupler 3 is to connect the adjoining two circuits, amd the primary side and the secondary side thereof are connected to the lead pins 5 of a lead frame 4 to be connected to outside circuits through the wiring conductors 21, 22. the photo coupler 3 is connected interposing lead pins of two pieces in the middle to obtain the necessary creeping distance for the primary side and the secondary side, and the edge parts of the lead pins positioning at the middle positions 51, 52 are cut off along a cut line A-A. The surface of the substrate is covered with resin for protection hereafter.

Description

【発明の詳細な説明】 本発明は互に絶縁されるべき二つの回路を含み、それぞ
れ外部回路と接続のための端子を有する混成集積回路の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a hybrid integrated circuit including two circuits to be isolated from each other, each having a terminal for connection to an external circuit.

（従来技術とその問題点） 混成集積回路の外部回路の接続のための端子をリードフ
レームのリードピンによって形成することは製造工程の
合理化と材料費の低減のために有効である。しかしリー
ドフレームのリードピンは等間隔に設けられるため、例
えばホトカブラにより結合される一次側，二次側の回路
の端子をりードピンにより形成する場合には隣接リード
ビンを利用したのでは十分な絶縁距離をとることができ
ないおそれがある。そこでやむを得ずリードフレームを
利用しないで必要な間隔を置いてそれぞれ端子を接続し
なければならなかった。そのため作業が複数となり、原
価の上昇ばかりでなく信頼性の低下をもたらす。(Prior art and its problems) Forming terminals for connecting external circuits of a hybrid integrated circuit using lead pins of a lead frame is effective for streamlining the manufacturing process and reducing material costs. However, since the lead pins of a lead frame are provided at equal intervals, for example, if the terminals of the primary and secondary circuits connected by a photocoupler are formed using lead pins, using adjacent lead bins will not provide sufficient insulation distance. There is a possibility that you will not be able to take it. Therefore, I had no choice but to connect the terminals at the necessary intervals without using a lead frame. This results in multiple tasks, which not only increases cost but also reduces reliability.

（発明の目的） 本発明はこれに対し互に絶縁されるべき回路の端子をリ
ードフレームで形成し、しかも端子間の必要な絶縁距離
が確保できるような混成集積回路の製造方法を提供する
ことを目的とする。(Object of the Invention) In contrast, the present invention provides a method for manufacturing a hybrid integrated circuit in which the terminals of a circuit that should be mutually insulated are formed using a lead frame, and the necessary insulation distance between the terminals can be secured. With the goal.

（発明の要点） 本発明による混成集積回路の製造工程は・基板に配線導
体を印刷する工程と、配線導体に回路部品を固定する工
程と、リードフレームのリードピンを基板縁部にはめ込
む工程と、配線導体とり−ドピンとを接続する工程と、
側フレーム部を切り落とす工程と、絶縁の必要な二つの
リードピンの間に存在し配線導体と接続されないリード
ピンを基板から取り外す工程とを含むことによって上記
の目的を達成する。(Summary of the Invention) The manufacturing process of the hybrid integrated circuit according to the present invention includes: a process of printing wiring conductors on a board, a process of fixing circuit components to the wiring conductors, and a process of fitting lead pins of a lead frame into the edges of the board, a step of connecting the wiring conductor to the doped pin;
The above object is achieved by including the steps of cutting off the side frame portion and removing from the board the lead pin that is present between two lead pins that require insulation and is not connected to the wiring conductor.

（発明の実施例） 第１図は本発明の一実施例により製造された混成集積回
路を示し、例えばセラミックからなる絶縁基板上に斜線
で示した配線導体２が印刷厚膜により形成されている。(Embodiment of the Invention) FIG. 1 shows a hybrid integrated circuit manufactured according to an embodiment of the present invention, in which a wiring conductor 2 shown by diagonal lines is formed by printing a thick film on an insulating substrate made of, for example, ceramic. .

この配線導体２に１ｉ７１路部品がろう付けされて回路
が構成される。ホトカプラ３は隣接する二つの回路を結
合させるもので、その−次側および二次側が配線導体２
１．２２を介して外部回路と接続のための端子として他
の回路部分と同様に基板１の縁部にはめ込まれたリード
フレーム４のリードピン５とそれぞれ接続される。1i71 path components are brazed to this wiring conductor 2 to form a circuit. The photocoupler 3 connects two adjacent circuits, and its negative side and secondary side are connected to the wiring conductor 2.
1.22, they are respectively connected to the lead pins 5 of the lead frame 4 fitted into the edge of the board 1 as well as other circuit parts as terminals for connection to an external circuit.

リードピン５は図に鎖線で示した位置に等間隔αを置い
て存在するが、ホトカプラの一次側と二次側に必要な距
離は隣接するリードピン５の間では得られないので図の
例では中間に２本のリードピンを挾んで接続されている
。しかし図゛の５１，５ｊ！の位置にあった中間のリー
ドピンの端部が基板ｌの縁部にはめ込まれたままでは必
要な絶縁のための沿面距離が得られないので、側フレー
ム部６を切断線Ａ−Ａによって切り落とした後取外され
ている。このあと基板上を保饅用の樹脂によって被覆す
ればホトカプラの一次側、二次側の間の絶縁が確保され
た混成集積回路が得られる。The lead pins 5 are located at equal intervals α at the positions indicated by the chain lines in the figure, but since the distance required for the primary and secondary sides of the photocoupler cannot be obtained between adjacent lead pins 5, It is connected with two lead pins in between. But 51,5j in figure ゛! If the end of the intermediate lead pin located at the position remained fitted into the edge of the board l, the necessary creepage distance for insulation could not be obtained, so the side frame part 6 was cut off along the cutting line A-A. It has since been removed. After that, by covering the substrate with a protective resin, a hybrid integrated circuit is obtained in which insulation between the primary and secondary sides of the photocoupler is ensured.

（発明の効果） 本発明は互に絶縁されるべき二つの回路に接続される端
子として、リードフレームの中間に接続されないリード
ピンを挾んだ二つのリードピンを利用し、接続されない
リードピンを除去するもので、除去されるリードピンの
数を絶縁に必要な沿面距離に応じて選ぶことができる。(Effects of the Invention) The present invention uses two lead pins sandwiching an unconnected lead pin in the middle of a lead frame as a terminal to be connected to two circuits that should be insulated from each other, and removes the unconnected lead pin. The number of lead pins to be removed can be selected depending on the creepage distance required for insulation.

このためシングルインライン形状またはデュアルインラ
イン形状の混成集積回路において、外部回路との接続の
場合に絶縁距離が必要な回路構成であっても、通常のリ
ードフレームを用いて極めて容易に所要の絶縁沿面距離
が確保でき、信頼性の高い混成集積回路の経済的な製造
を可能にする。For this reason, even in single-in-line or dual-in-line hybrid integrated circuits, even if the circuit configuration requires an insulation distance when connecting to an external circuit, it is extremely easy to obtain the required insulation creepage distance using an ordinary lead frame. This enables economical manufacturing of highly reliable hybrid integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例により製造される混成集積回
路の製造工程中における正面図である。 １：基板、２．２１．２２：配線導体、３：ホトカプラ
、４：リードフレーム、５：リードピン、６第１図FIG. 1 is a front view of a hybrid integrated circuit manufactured according to an embodiment of the present invention during the manufacturing process. 1: Board, 2.21.22: Wiring conductor, 3: Photocoupler, 4: Lead frame, 5: Lead pin, 6 Fig. 1

Claims (1)

【特許請求の範囲】[Claims] １）基板に配線導体を印刷する工程と、配線導体に回路
部品を固定する工程と、リードフレームのリードビンを
基板縁部にはめ込む工程と、配線導体とり−ドピンとを
接続する工程と、側フレーム部を切り落とす工程と、絶
縁の必要な二つのリードピンの開に存在し配Ｉｓ導体と
接続されないリードピンを基板から取り外す工程とを含
むことを特徴とする混成集積回路の製造方法。1) The process of printing the wiring conductor on the board, the process of fixing the circuit components to the wiring conductor, the process of fitting the lead bin of the lead frame into the edge of the board, the process of connecting the wiring conductor take-do pin, and the process of installing the side frame. 1. A method for manufacturing a hybrid integrated circuit, comprising the steps of: cutting off a portion of the lead pin; and removing a lead pin that is present between two lead pins that require insulation and is not connected to the Is conductor from the substrate.
JP58174573A 1983-09-21 1983-09-21 Manufacture of hybrid integrated circuit Pending JPS6066453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58174573A JPS6066453A (en) 1983-09-21 1983-09-21 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58174573A JPS6066453A (en) 1983-09-21 1983-09-21 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6066453A true JPS6066453A (en) 1985-04-16

Family

ID=15980918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58174573A Pending JPS6066453A (en) 1983-09-21 1983-09-21 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6066453A (en)

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