JPS6065562A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a software error due to alpha-ray by individually altering the depths of a well of a peripheral circuit and a memory cell, thereby reducing the number of implantation to an inverting layer of induced electrons due to the alpha-ray. CONSTITUTION:In a memory cell, a shallow P type well 2 is formed, and NMOS memory cells 4-6 are formed in the well 2. In a peripheral circuit, a deep P type well 2' is formed, an N type substrate 1 is formed with PMOS 5, 6, and P type well 2' is formed with NMOS 4, 6. Accordingly, the P type well 2 of the memory cell can be shallowed to the degree that a punch-through is not produced, and the depth of the P type well 2' of a peripheral circuit can be formed to the degree that a latchup does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device, and particularly to a dynamic RAM having an 0MO8 structure.

Background of the Technology In a normal 0MO8 structure, all P-type wells are formed on an N-type substrate, and PMO8'e is formed on an N-type substrate.

N-MOS is formed in the P-type well, but in addition to this, N-MOS is formed in the P-type well.
It is known that a large P-type well is formed on a shaped substrate, and an NMOS memory cell is formed within this P-type well.

This stiff NMOS memory cell becomes resistant to α-ray soft errors.

In FIG. 1, a P-type well 2 is formed on an N-type substrate 1.

An NMOS memory cell is formed in this P-type well 2. Here, 3 is a field oxide film, 4 is an N type impurity diffusion region as a source or drain, 5 is an inversion layer or square impurity diffusion region as a charge storage part, and 6 is a metal as a gate electrode or a counter electrode of a capacitor. layer, B is the bit line.

W is a word line. When α rays are incident on the device of FIG. 1 as shown by the dotted line, a large number of electron and hole pairs are induced around the trajectory of the α rays. As a result, induced electrons are injected into the inversion layer 5 or the N-type substrate l, which is a charge storage part, along the electric field 9
Due to the electrons injected into the inversion layer 5, information stored in the inversion layer 5 with a small number of electrons, such as 1'', may be inverted to information with a large number of electrons, ``0''. In this case, the electrons that are induced to be injected into the inversion layer 5 by the electric field crossed by the α rays exist only in the depletion layer that exists between the inversion layer 5 and the P-type well 2. The number of electrons injected into the layer 5 should be limited to only the electrons induced within the depletion layer, but in reality, due to the "Funneling" phenomenon, temporary pseudo The electric field expands. Therefore, the induced electrons in a fairly deep place are transferred to the inversion layer 5 VC
As a result, the number of injected electrons due to the "Funneling" phenomenon accounts for a considerable proportion of the total number of injected electrons. However, in P-type well 2 on N-type substrate l, NM
When an OS memory cell is formed.

As shown in FIG. 2, since the P-type well 2 forms a potential barrier, the depth to which the pseudo electric field spreads is limited, and the distance d
Only the induced electrons generated within the distance d are injected into the inversion layer 5, and the induced electrons generated outside the distance d are injected into the substrate 1.

Therefore, in order to reduce the number of electrons induced by α rays injected into the inversion layer 5, the thickness of the P-type well 2 may be reduced. However, if the total thickness of the P-type well 2 is reduced too much, the peripheral circuit constituted by the PMO8 formed in the N-type substrate 1 and the NM6S formed in the P-type well 2,
A latch-up phenomenon occurs in which the NPNP element, that is, the parasitic thyristor turns on.

Therefore, conventionally, the thickness of the P-type well 2 is set to such an extent that latch-up of the 9 peripheral circuits does not occur, so that the number of electrons induced by α rays injected into the inversion layer 5 is insufficiently reduced. There was also a problem in that prevention of soft errors caused by alpha rays was insufficient.

Purpose of the Invention The purpose of the present invention is to solve the following problems in view of the problems in the conventional type described above.
Based on the idea of changing the well depth of the peripheral circuit and the well depth of the memory cell section separately, the well of the memory cell section is made as shallow as possible, that is, to the extent that punch-through does not occur, to prevent electrons induced by α rays. The objective is to sufficiently prevent soft errors caused by α rays by reducing the number of injections into the inversion layer.

Composition of the invention According to the present invention to achieve the above objects.

A deep well and a shallow well of a second conductivity type opposite to the first conductivity type are formed in a semiconductor substrate of a first conductivity type, and a memory cell portion is formed in the shallow well.

A semiconductor memory device is provided in which a peripheral circuit is formed in the deep well and the semiconductor substrate.

Examples of the invention Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 3, the right side is the memory cell section, and the left side is the peripheral circuit. In the memory cell section, a shallow P-type well 2 is formed, and NMO is formed in this well 2.
S memory cells 4 to 6 are formed. On the other hand, in the first peripheral circuit section.

A deep P-type well 2' is formed, and PMOs 86 and 7 are completely formed on the N-type substrate 1, and NMO8 is formed on the P-type well 2'.
4 and 6 are formed. Therefore, memory section k (D P
The depth of the P-type well 2' of the peripheral circuit 1 can be made shallow enough to prevent bunch-through from occurring, and the depth of the P-type well 2' of the peripheral circuit 1 can be made to an extent that latch-up does not occur.

The wells having different depths shown in FIG. 3 can be formed by various manufacturing methods. The manufacturing method will be explained below.

First, FIGS. 4(A) to (C1) will be explained.
As shown in the figure, a resist pattern 4 is placed on an N-type substrate l.
1 is formed, a predetermined dose of B ions is implanted, and the resist pattern 41 is removed. Next.

As shown in FIG. 4(B), a new resist pattern 4 is created.
2 gold is formed, a predetermined amount of B ions are implanted, and the resist pattern 42 is removed. As a result, a high concentration region 2' and a low concentration region 2 are formed. Next.

When running (heat treatment in a non-oxidizing atmosphere),
As shown in FIG. 4(C), a deep P-type well 2' and a shallow P-type well 2 are formed.

The manufacturing method shown in FIGS. 4(5) to 4(O) can also be applied to the case of forming a deep N-type well and a shallow N-type well in a P-type substrate.In this case, instead of B ions, P ions or As ions are used.

Figure 5 (5) to (C> will be explained. Figure 5 (5)
As shown in FIG. 1, a resist pattern 51 is entirely formed on an N-type substrate 1, and a predetermined dose of B ions is implanted to form a high concentration region 2'. Then, the resist pattern 51 is removed. Next, as shown in FIG. 5), a new resist pattern 52 is formed and a predetermined dose of B ions is implanted to form the low concentration region 2. Then, the resist pattern 52t is removed. Next, when running is performed, a deep P-shaped well 2' and a shallow P-shaped well 2 are formed as shown in FIG.

The manufacturing method shown in FIGS. 5(4) to 5(0) can also be applied to the case where a deep N-type well and a shallow N-type well are formed on a P-type substrate.

The manufacturing method of Fig. 6) to (0) is one in which a running process is added between the step of Fig. 5 and the step of Fig. 5 (Bl), that is, a running process for forming a well. Jt is to be performed twice.

The above-mentioned Figure 4 prisoner ~ (C), Figure 5 prisoner ~ (0, Figure 6 ■ ~
Although the manufacturing method shown in Figure 0 uses only one type of ion implantation for forming wells,
), it can also be carried out using two types of ions.

The discussion in FIGS. 7(A) to 0 assumes that an N-type well is formed on the P-type substrate 11. In other words.

In FIG. 7, a resist pattern 71 is formed on the substrate 11.
region 1 by forming P ions with a large diffusion coefficient and implanting P ions with a large diffusion coefficient.
2"i is formed. Then, the resist pattern 71 is removed. In FIG. 7(B), a new resist pattern 72 is formed on the substrate 11, and As ions having a small diffusion coefficient are implanted to form the region 12. Then, the resist pattern 12 is removed.If running is performed in this state, a deep N-type well 12' and a shallow N-type well 12' will be formed due to the difference in diffusion coefficients, as shown in FIG. Then, as shown in FIG. 7(2), a deep N
A PMO 8 is formed in the shallow N-type well 12', and a PMOS memory cell is formed in the shallow N-type well 12.

13 is a field oxide film.

The manufacturing method shown in Figure 7 (■ to D) can also be applied to forming deep P-type wells and shallow P-type wells on an N-type substrate by selecting ions with different appropriate diffusion coefficients. can.

As described in detail, according to the present invention, the memory cell portion can be formed into a shallow well that does not cause bunch-through, and is therefore sufficiently useful for preventing soft errors caused by alpha rays.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a memory cell portion for explaining the present invention in detail, and FIG. 2 is a potential characteristic diagram of FIG. 1. FIG. 3 is a sectional view showing an embodiment of the semiconductor memory device according to the present invention, FIG. 4 (4) to (C1), FIG. A) to 0 are cross-sectional views for explaining the manufacturing method of the device shown in FIG. 3. 1.11: Semiconductor substrate. 2.12: Shallow well. 2', iz': Deep well. Patent applicant Fujitsu Patent Application Agent Co., Ltd. Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate 1) Yukio Patent Attorney Akira Yamaguchi

Claims (1)

[Claims] 1. Forming a deep well and a shallow well of a second conductivity type opposite to the first conductivity type in a semiconductor substrate of a first conductivity type, forming a memory cell portion in the shallow well, and forming a memory cell portion in the shallow well; A semiconductor memory device in which a peripheral circuit is entirely formed in a well and the semiconductor substrate.