JPS6063591A - Digital image apparatus by software - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Related Applications The following US patent applications are related to the present invention. G. J. Goss, T., filed June 13, 1983.
,O.

Holtey and J. O., U.S. Patent Application No. 504,092, "Modifiable Loadable Character Generator."

TECHNICAL FIELD The present invention relates to computer systems, and more particularly to an apparatus and method for generating various types of character sets, including character sets for many national languages.

A character generator is a device for converting a character code associated with a particular character to be displayed on a cathode ray tube into a dot pattern for that particular character.

To obtain reasonable speed, character generators typically use a table indexing scheme with tables stored in dedicated memory, usually ROM/RAM, by using the character code as part of the address to memory. - Constructed within the software. There are various ways to generate characters. Applicants have not conducted a search of the prior art. However, Cole's patent (U.S. Pat. No. 3,345,458,
In a recent case by the U.S. District Court of Prauea in Master File Case No. 78-198, the court's intent resulted in the following technical opinion.

(Technical Outlook) [Receives digitally encoded data and transfers it to a cathode ray tube (
There are several parameters to consider when designing a system for display in decoded form on a CRT. These include: (1) The format of the scanning pattern. The two forms of concern are those in which the scan covers one character space at a time (a miniature master scan pattern), and those in which the beam scans across the entire width of the CRT screen so that each line of the scan Includes a horizontal slice of each character in a row (television master scan pattern).

(2) The two main types of CRTs are the memo IJ-tube type, which can hold one image for several minutes, and the CRT type, which is fast enough to continue displaying the image, of which TV tubes are an example. There are non-memory types (containing fluorescent phosphors with high resistance) that require refreshing.

(3) Storage area. A certain amount of storage space or memory is required in systems using non-memory CRTs.
This is because the video signal must be applied many times per second. However, this memory may either store the character code prior to decoding or store the video bits produced by the conversion process.

When the former is used, the system is sometimes characterized as an "on-the-fly" system, as opposed to a system that stores video bits as each one is generated by the conversion mechanism. Indicates that video bits are added to.

Each type of rask scan pattern has its advantages and disadvantages.TVThe advantage of miniature rask scan over rask scan is that the character code is relatively slow for the same number of characters per row and column per screen. It is something that can be presented.

The two main advantages of using TV scanning are cost savings in the display portion of the system (CRT and deflection circuitry) and cost savings in the display of images or other video signals (e.g. maps, etc.).
It is the ability to overlay letters on top of. However, such advantages are generally only useful if they can be operated at speeds at least equal to "commercial" or "entertainment programming" TV scanning speeds. Therefore, we can purchase a mass-produced, off-the-shelf display system relatively cheaply, or simply send a message to a TV set already in use for other purposes, or we can install a commercial TV set. It is only possible to mix the character signal with other video signals operating at speed.

However, at least the first advantage would be lost if the cost of producing a text video signal at commercial TV speeds exceeds the cost savings in the display portion.

When the beam of a CRT scans, the 0N10FF conditions that control the information of this beam must be synchronized with the scanning of the beam. This is true whether the beam is a TV scan pattern or a miniature scan pattern. However, if the TV scan pattern operates at commercial TV speeds or faster, the synchronization requirements are
This meant that electronic components had to operate at speeds that were unfeasible in the 1950s and too high to be commercialized in the early 1960s.

The encoded form of the input data must be converted to video data in order to control the 0N10FF conditions of the CRT's beam as the CRT sweeps in mini-rask scan or TV rask scan.

Patent documents from the 1950's disclose conversion in the form of digital circuits to convert from 6-bit character codes to pulse trains that result in the display of a 5.times.7 character matrix on a CRT.

Among the analog conversions known in the 1950's were monoscope character generators. This monoscope generally does not produce a series of 35 equal length pulse positions, each of which may be ON or OFF;
Therefore, it is generally not related to character matrix type displays. Rather, it receives a 6-bit character code and generates a pulse train whose pulse length corresponds to the exact width of the character being displayed at various locations along the height of the character. Physically, a monoscope is.

It is a small CRT that is generally cylindrical in shape and has a target on which characters are printed or stenciled instead of a screen. The beam is deflected to a particular character on the target in response to the received 6-bit character code and then scans the character. In response to this scanning, the monoscope produces an output signal that is a train of pulses with a pulse length or period corresponding to the time the beam traverses the character.

This pulse closely follows the shape of the character, resulting in a character of much better quality than the bin holes from a 5x7 character matrix.

All of the character display CRT systems in question use signal storage so that the CRT screen can be repeatedly "refreshed."

In this way, the entire screen of signals representing characters (sometimes
(referred to as "pages") are stored and used repeatedly to "refresh" the screen.

This storage is in one of two forms.

The first type provides storage of the received 6-bit character code. This code is then read from storage and C
The RT beam is converted into a video signal during scanning. The second type of storage converts the received 6-bit character code into its corresponding video signal and then stores the video bits. At this time, C! While the beam of the RT is scanning, video bits are read from storage onto the CRT. Both of these storage approaches involve the storage of codes, which are generally binary in nature and represent characters, but these are respectively ``character code storage'' and ``video It can be conveniently referred to as "bit storage area".

A disadvantage of video bit storage is that character code storage requires only one screen or page of 6-bit character codes, which requires storing a 35-bit character matrix code. , which requires a larger storage area. But the advantage of video bit storage is.

The character code is converted only once, so the video bits are stored and read simultaneously with the beam scan, so that the character code does not have to be converted simultaneously with each scan of the scan line, so the conversion is done in the fast beam. There is no need to maintain the same scanning speed. Furthermore, video bit storage is particularly suited for variable positioning of characters on a screen. As stated above, the advantages of the rask scan technique of digital character generation are only effective if it can operate at speeds at least equal to TV speeds for commercial or entertainment programming. This requirement is due to the ROM/R
This is met in the prior art using AM. This approach has the limitation that it requires dedicated memory for character generation, so it can only generate one set of characters, and it has the limitation that Other character sets, including formats, require additional hardware in the form of other ROM/RAM. This requires manufacturers to stock a wide variety of such hardware in order to provide a complete service to customers around the world.

What is needed, therefore, is a character generator that uses ROM/FROM, which is loadable rather than fixed, so that multiple character sets can be provided in a single hardware form.

Accordingly, it is an object of the present invention to provide an improved character generator.

Another object of the present invention is to use a cathode ray tube (C) as a display.
The present invention provides an improved character generator for use with computer terminals using the RT).

Yet another object of the present invention is to provide an improved character generator that is a ROM/FROM that is loadable rather than fixed so that multiple character sets can be represented in a single hardware form.

Another object of the invention is to provide an improved character generator that uses minimal hardware to make the character generator loadable.

These and other objects of the invention will become apparent when the description is considered in conjunction with the drawings.

The software loadable character generator of the present invention is a RAM using 2×8 RAM storage;
The ROM/FROM is replaced by a Motorola 6845 CRT controller with 4k x 8 memory, 4 MUX chips and various registers.

Eighty characters horizontally and twelve scan lines vertically are used per character line. The character code is read from the display memo IJ- for each character position on each scanning line.

Each time a new character is read from display memory, the character code is used as part of the address used to address the RAM, which acts as a character generator. The remainder of the address for the character generator is derived from the scanline number. The address consists of 12 bits consisting of 8 upper bits containing a character code and 4 lower bits containing a scanning line number. The appropriate portion of the character will appear at each character time until 80 characters are displayed on the screen after each scan completes the 12 scan lines.

The manner in which the apparatus of the present invention is constructed, and its mode of operation, is best understood in light of the following detailed description in conjunction with the drawings.

To understand the invention, the television set C.
It is necessary to understand that forming images on RT. The image is formed by an electron beam that causes points on the fluorescent phosphor coating of the screen to emit light as the electron beam scans the area where the image is to be displayed.

Typically, the beam scans along one horizontal line at a time, starting at the top of the screen and moving gradually down the screen to the bottom.

This pattern of scanning, in which the beam travels across the entire width of the CRT's screen before scanning a second horizontal line, is called a television raster scanning pattern. By appropriately controlling the beam intensity using digital video control signals as the beam traverses the screen, the beam can be used to form a recognizable message or image. Because of its speed, the motion of the beam is invisible to the human eye.

Each component (font) of a character set is a dot,
can be represented by an array of dots in a rectangular matrix having a height of 9 dots). Character,
A CRT in one character space containing the dot matrix of characters and another margin space separating the characters on the screen (e.g. 9 dots wide x 12 scan lines high)
displayed on the screen. Two such adjacent character spaces are shown in prior art FIG. 1A.

As the beam traverses the screen in one scan line, the computer code for each character to be written in a line across the screen is sequentially provided from memory to a decoder or "character generator." As shown in Prior Art FIG. 2, a timing and control circuit produces a count signal representing the scan line of the raster and the dot position along the scan line. The character code information, scan line count signal and dot position count signal are sent to a digital/video signal generator 20 which is a character generator.
1, this generator converts the signal to a two-level serial digital output. The output signal is applied to television monitor circuit 202 as a video signal. One digital value level of the signal corresponds to one dot and turns on the electron beam to write one dot on the television screen. The other digital level corresponds to the absence of one dot, leaving the electron beam OFF so that no dot is written. As the electron beam moves along the scan line, the dots thus produced correspond to dots in the appropriate horizontal slice of each character to be displayed in a line of characters.

In this way, in FIG. 1A, dots 103 to 10
5 (for the letter "A") and dots 106 to 10
9 (for the letter "B") will be emitted sequentially as the electron beam moves along the top scan line. The timing and control circuit of FIG. 2 also provides horizontal and vertical drive pulses to the monitor 202.
The scanning motion of the beam is synchronized to the video signal generated as described above.

After completing one scan line, the electron beam returns to the starting point of the screen (but one position lower due to the vertical sweep) to begin the next scan line. Next, the character code,
The sequential addition of scan line and dot position counts is repeated, now producing a video signal for the next dot slice of each character in the row.

After the appropriate number of scan lines (8 or 12) have been "written" to the screen, a complete line of characters is complete. Complete lines are written to the screen one scan line at a time from top to bottom.

Similarly, another line of characters is written that constitutes the message to be displayed on the screen. This step "refreshes" the screen after the entire screen has been scanned.
The images are repeated at a rate of 60 times per second to form a display that is perceived by the human eye as a stable, flicker-free image.

In FIG. 1B, an example of the translation of a code for the character "1" to be displayed on the screen is shown.

Note that if the binary codes used to identify the various characters were applied directly to the CRT, the patterns on the screen would generally not be visible.

In this way, the 6-bit code 000111 has the value "7".
”, but it will appear as three dark dots followed by three bright dots, or vice versa. the result,
It is necessary to convert the 6-bit binary code into a video signal representing the normally occurring characters. To see how this is done, please refer to Figure 1B, which shows the code-to-pattern conversion for the number "1". Note that the video code for the first scan line is ooiooo, and the video signal representing this code will be a pulse at the location where the dot is to appear. Similarly, in the scan line, two video coaters 011
00, so that the video signal representing this video code is two pulses that cause two dots to appear on scan line 2. (When the last scan line is completed,
The value "1" appears on the screen. ] Next, in FIG. 3, one character is shown in one row in one column. There are 80 such character strings across the screen, and 25 lines, so that 2000 characters can be generated on this page or screen. FIG. 3 shows how the letter "A" is formed within boundaries 301-302 when a total of twelve raster lines making up one character line are completed. (Nine raster lines are used to generate characters, but
Three lines are added as spaces between character lines. ) This character (
(part of a message), it must first be stored in the memory or buffer 7 shown in FIG.

In order for this character to be written on the screen, it must be generated by character generator 14. This character generator stores different standard characters at different addresses that can be used to generate the characters of any message on the screen stored in buffer 7, as described above. The patterns stored in this character generator 14 are addressed using the codes of the characters in the message as part of the address. in this case,
The decimal code is 65, but the hexadecimal code for "A" is 041. Therefore, the address of the letter "A" would be 65x16 for the first raster line, (65x16)+1 for the second raster line, and so on. As each raster line progresses across the screen, complete 1
The patterns for different characters of the message are similarly addressed by the code of seven to create each part, until the character of the line is created by nine consecutive raster lines.

Turning now to FIG. 4, a high level logic block diagram of the present invention is shown. Two buses are connected to a commercially available Motorola 6809 microprocessor 20, a 16-bit address bus 1 and an 8-bit data bus. Under the control of microprocessor 20, a microsystem 6/10 type system (not shown) forms part of the invention and communicates with the terminals via address and data buses 1,2. Two commercially available 6116 type RAMs 7 and 8 are connected to an 8-pit data bus via commercially available 74LS245 type transceivers 9 and 10, respectively. The transceivers 9 and 10 can send data in either direction from the bus to the RAM or from the RAM to the bus.

This data is stored in RAM at an address controlled by microprocessor 20 via address bus 1.
Placed against 7 or 8. The selection of RAM 7t or 8 in which data or attributes are to be stored is made via the lower bits of address bus 1 via logic not shown. Therefore, when a message is written on a CRT screen (not shown), the data (i.e.
message) is sent to RAM via transceiver 10 at an address provided by microprocessor 20.
Written to 7. Similarly, attributes (ie, underlining, flashing, etc.) are written to RAM 8 via data transceiver 9. To write on a CRT screen (not shown), each character must be scanned in small increments as each scan line advances across the screen (not shown), as described above. After that, the CRT control device CRT
Under the control of C3, each character of the message is addressed and read into register 11. Similarly, each attribute corresponding to any character is read into register 12 at the same time. For any character of a message temporarily stored in register 11, eight upper bits (actually representing the character code) and four lower bits (representing the scan line, and 12 different scan lines 0-11 ) is given to the character generator 14. Character generator 14 includes two commercially available generators that store a set of character patterns in different formats that can be addressed by addresses formed by juxtaposing character codes to one scan line code, as described above. It consists of 6116 type RAM. When the individual scan lines of a CRT screen (not shown) progress in an 80-character time frame, a portion of each character is assigned to each character by a character temporarily stored in register 11 for the particular time frame. Each scan line as shown in the time frame is written in each time frame. The scan line addresses cycle from 0 to 11, and when 12 complete scan lines are formed on the screen, 80 characters are completed as a line on the screen. A shift register 15 connected to the character generator 14 is a means for converting parallel data into serial data.

The invention is to have the attributes for a particular character appear on the screen at exactly the same time that the character appears. This is accomplished by storing character data in the screen's data buffer and attribute data in the screen's attribute buffer. Each address is given to a screen data buffer and a screen attribute buffer so that the character being addressed is placed in register 11 and the attribute being addressed is placed in register 12. In this way, the character code and attribute code are written on the screen at the same time and are therefore available to the control logic. In this way, both the textual information and the attribute information are available at exactly the same time, resulting in very precise timing and a clear image on the screen.

It will now be shown that the present invention provides a means for loading the character generator RAM 14 of FIG. 4 which requires minimal hardware beyond that required for the character generation function. The core of the invention has alphanumeric characters and attributes from RAM 7 having the pattern of FIG.
The hardware described below is the load mode flip-flop 17 of the character generator of FIG. 7 and the associated control loading character of the single register 13 of FIG. When this flip-flop is set to the character generator load state, the character generator RAM is set to write mode, and the three-state output of register 13 described above remains in register 13 as long as this mode remains enabled. RA every clock cycle for each character whose content is
Enabled to be written to M14. At this time, the address where the data is written is exactly the RAM
14 is used for its normal character generation functions, as well as when C! These are the addresses of 12 reads consisting of 4 scan line reads originating from RTO3 and 8 reads originating from register 11. It is also noted that register 13, which holds the data to be written, is fed by the "attribute" screen buffer RAM 8, while register 11 is fed by the "data" screen buffer RAM 7. sea bream.

The combination of "loading" the screen data and attribute RAM and programming the 0RTC3, in conjunction with the load mode hardware described above, will cause the required tables to be loaded into the character generator 14. The attribute screen buffer 8 is loaded with the screen pattern and the data screen buffer 7 is loaded with the character codes normally used to induce the associated pattern. These patterns, which in this example are 12 scan lines high, are stored in character generator RAM1.
To simplify addressing of 4, these patterns are assigned to blocks of 16 sequential locations.

Therefore, a configuration in which the address is merely a concatenation of character codes based on scanning line numbers is possible. The screen buffer data and attribute RAM is 2048 (2
k) locations, so there is room for 2048/16=128 patterns in one "load" of the attribute RAM. This is half of the 256 different patterns that need to be loaded into the character generator, so the procedure must be split into two phases. Generally, this division will be through a character code set consisting of 128 codes handled in the first phase and the remaining 128 codes loaded in the second phase. The following description is limited to the effect of one of these phases, and the difference between the two phases &
Present only in the values of data loaded for mehita and attribute RAMs 7 and 8.

At the beginning of each phase, the screen attributes and data buffers are each loaded with 128 patterns and corresponding character codes, each of which is replaced 16 times.

The details of the order of this information within the screen buffer RAM are governed by the action of 0RTC3.

0RTO3 can now be loaded with several parameters that will control its behavior, including: That is: Number of characters per line Number of scanlines per line Number of characters per line One purpose of the starting address of the screen buffer 0RTO3 is to store the scanline number, which acts as part of the address of the character generator, as mentioned earlier. The problem is to generate a suitable sequence of addresses to address the screen buffers 7 and 8 in order to enable the display of the patterns associated with the code stored in the buffers while also occurring. Another purpose of this 0RTO is to facilitate scrolling by allowing the beginning of the screen to correspond to any location in the screen buffer and thus the starting address parameter.

The action of the 0RTO is to create a series of screen buffers.
It consists of issuing an address and a scan line number (as well as a synchronization pulse, which is not an issue here). In particular, the first sequence that occurs consists of a linear sequence of screen buffer addresses starting at the screen buffer starting address, but the length of this sequence is Equal to the number of characters per parameter. After a suitable synchronization interval, this same sequence of screen buffer addresses is repeated while maintaining the resulting scan line number at a value of one. This process is repeated a number of times as dictated by the number of scan lines per character line parameter. The entire process is then repeated for the next sequential set of screen buffer addresses, and this level of repetition is repeated until the number of iterations equals the character line parameter number.

Thus, for an 80 character per line display with 12 scanlines per character line and 25 character lines, the first sequence is such that the scanline number is held at zero and then the scanline number is This same sequence of first 80 addresses consists of the first 80 addresses (starting at the starting address of the screen buffer) followed by the scan line number being held equal to 1 until it equals 11. After this, the second 80 addresses are generated 12 times until finally the 25th set of 80 addresses is generated 12 times (with scanline numbers ranging from O to 11 for each repetition of the same set of addresses). etc.

Let us now assume the following example for the purpose of illustrating the loading of a single character generator. “Parameters” for the following assumptions
is loaded to 0RTO and controls its operation during the loading function. That is, the number of characters per line = 128, the number of character lines = 1, the number of scanning lines per character line = variable, and the starting address of the screen buffer; variable.

FIG. 8 shows the structure of data in screen buffer RAMs 7 and 8. The left half of each column represents the contents of the "data" buffer 7, while the right half represents the contents of the "attribute" buffer 8. The number at the top represents the number of character patterns to be loaded, while the number in the left margin indicates the address range used for each scan line. The case shown in FIG. 8 is for the first phase of pattern loading, that is, the character code θ˜127. Thus, as shown, the contents of the data buffer (the left hand side of each column) constitute a sequence of character codes for this range repeated 16 times. The notation r P a,b J (in this case raJ and "b" are numbers) shown for the contents of the right half column is the scan line of the pattern for the character whose code is l-a J. A binary representation for rbJ is shown. Thus, according to the example of FIG. 3, if the character code for rAJ is 65 (according to the AEIC!I echo code), then P65.
O=0, P65.1 becomes 16 (binary number 000100
00), P65.2=40 (binary number 00101000)
, etc.

The appropriate character pattern constructed as described above is loaded into the screen attribute buffer by an appropriate program resident in the 6809 microprocessor 20 at the beginning of each phase.

C! Due to constraints imposed by the normal functioning of the RTO, the algorithm for loading character patterns into the character generator must be divided into 16 passes. For each pass, the 0RTO is loaded with parameters as described below and then determined by monitoring by a vertical synchronization signal, not shown, issued by the 0RTO at the end of each complete sequence that occurs. ) Thus, to describe the loading pattern recognizing that the entire range of 16 scanlines is achieved by only loading the scanlines that were actually used because the improvement in loading time appears Become.

FIG. 9 shows the starting address of the screen buffer for every 16 passes and the value of the number of scanning lines for each character line parameter. In the first pass, the starting address is
Set to the address corresponding to the beginning of the last scan line in the figure, this is the area where 15 slices of the scan line of the character pattern are stored. ORT C will cycle through this address line 16 times while the scan lines step from 0 to 15. Next, two of the patterns of scan lines 15 are used because the data buffer 7 holds a series of numbers 0 to 127 and each of these numbers together with the scan line number forms an address to the character generator RAM 14.
The decimal representation (right half of each column of the last row of FIG. 8) will be written to character generator 14 16 times. The first 15 such iterations are unnecessary, but the 16th loads the pattern information for scan line 15 to the correct location. In the second pass, the starting address is set to 1'12 (the next after the last scan line in FIG. 8), but this time the number of scan lines is programmed to be 15. This means that on this bus, 0R
This means that the scan line numbers generated by TO are only in the range 0 to 14, and as a result, the pattern information of scan line 15 loaded on the first bus remains unchanged. Again, at the same time as this bus, the screen
Only the last of the repetitions (in this case 15 times) up to the address specified by 128 in the buffer is necessary. In this way, this process ends (16th time)
Each cycle through the first 128 locations progresses by one scanline in FIG. 8 while decreasing the number of scanline parameters by one until the bus. At this time, the appropriate half of the character generator for the current phase is fully loaded.

5, 6 and 7, detailed block diagrams of the invention of FIG. 4 are shown.

It will be appreciated that components in FIG. 5, 6 or 7 that correspond to similar components in FIG. 4 are identified by the same reference numerals. Thus, the character generator of FIG. 4 with reference number 14 is also identified by reference number 14 in FIG.

Next, in Figure 6, the screens and
Data buffer 7 and screen attribute buffer 8 constitute a 2kX16 screen buffer. Data from the 8-bit data bus shown in FIG.
Given for US 00 to DBUS 07. When data is being sent from the bus to the screen data buffer 7 to be written, the transceiver 1
Screen buffer data signal 5BDATO on 0
to 5BDAT7 are provided to terminals 5BDATQ to 5BDAT7 of screen data buffer 7. Conversely, data from screen data buffer 7 can be read out onto bus 2 via transceiver 10.

Similarly, data representing attributes is stored with respect to screen attribute buffer 8 and data bus terminals DBUSOO to DBUSO7 of transceiver 9 and screen buffer attribute terminals 5BATTO to 5BAT.
Writing or reading is possible on bus 2 via T7. When moving information into and out of screen buffer memories 7 and 8, the information is transferred to and from terminal 5BA.
DO9 to S BAD tufa attribute 8 or screen
Data buffer 7's write enable signal WESBAT or WEiSBDT must be true. This technique of using a unique write-enable signal to select one memory or the other allows screen data to be stored in one memory bank, but screen attributes to be stored in another memory bank. is stored in

When it is desired to generate a character, the information in screen data buffer 7t or 8 is read into registers 11 and 12 in synchronization with the scan line time interval. Therefore, terminals 5BDATQ to 5BDAT
It will be seen that the screen buffer data at 7 will be applied to terminals 5BDAT.0 through 5BDA 7 of register 11. Similarly, data from screen attribute buffer 8 is transferred to register 1.
Added to 2. For example, the information in register 11 is the required character code for this particular time interval. This character code is applied to terminals 0OODK O through CC0DE7 of the character generator 14. Furthermore, the terminal RAS of the CRT control device 3
Raster scan line address signals at TR1 through RASTR4 are applied to character generator 14 at terminals RASTR1 through RASTR4 of the raster scan address lines of character generator 14. Therefore, when the rask scan line θ~11 is addressed, and when each character is presented to the character generator in synchronization with the scan line time interval, the character generator 14 decodes a portion of the character and The video output signal is connected to the lines VIDD00 to VI in Figure 7.
The shift/control in the third sheet of FIG. 7 is performed via DDO7.
Terminals VIDD00 to VIDD of register 15
Give to O7. These signals are input in parallel,
They are sequentially shifted out at terminal VIDOUT.

Next, in FIG. 5, the CRT control device (ORTC 3
causes all timing for display. This is the screen buffer address sequence sent out at terminals 0RTAO9 to CRTA19,
It consists of a sequence of rask line numbers sent out at terminals RASTR1 to RASTR4, as well as horizontal and vertical synchronization signals H8YNO1 and vSYNC2 and a display enable signal DIEIPLY. 0RT
C3 applies signals UDATA O through UDATA 7 from data bus 2 to its terminals and the appropriate UBUSRD%PHAEI.

It can be loaded with control parameters by virtue of adding control signals such as E, ABUS and 0RTO061. Matrix (MUX) 6 is 0RT
It is for the purpose of selecting an address for the screen buffer RAM from either O3 or address bus 1. The former allows reading from the encoded display data and attributes selected at each display character time, while the latter allows the information to be displayed to be properly stored in the screen buffer. selected under the control of microprocessor 20 for that purpose. (For specifications for control devices such as CRT control devices, see MotorO1aSemic starting with 4-457.
Found in the onductor catalog,
Specifications for other components can be found at TexasInstr.
ument's r TTL Data Book for
rDesiv+IEngineθrsJ 2nd edition. ) Although the invention has been described in such a way that one of ordinary skill in the art can make and use it without undue experimentation, it is clear that one of ordinary skill in the art will be able to make and use the same without undue experimentation. It will be appreciated that many changes and modifications are possible and still fall within the scope and spirit of the appended claims. Therefore, some of the hardware and/or steps may be replaced by different hardware and/or steps that produce the same result and fall within the spirit of the invention.
Changes or substitutions are possible depending on the step. Therefore,
The invention is to be limited only as indicated by the scope of the claims appended hereto.

[Brief explanation of the drawing]

1A and 1B illustrate a prior art method of generating characters on a cathode ray tube (CRT) using video signals, and FIG. 2 illustrates a method of generating characters on a CRT using digital signals. FIG. 3 is a schematic diagram illustrating the addressing scheme of the present invention for generating characters on a CRT using a video signal; FIG. 4 is a high-level logic block diagram illustrating the present invention. Figure 5 shows the CRT of the present invention.
FIG. 6 is a detailed logical block diagram of a transceiver for the microprocessor, screen attribute buffer, and screen data buffer of the present invention; FIG. 7 is a detailed logic block diagram showing the character generator and various storage and shift registers; FIG.
Figure 9 shows a typical organization of data in the screen buffer RAM, and Figure 9 shows typical values used for the starting address and scan line number parameters for 16 passes through a row. It is a table. 1.2...Data bus, 3...CRT control device,
4.5...Line, 6...Multiplexer, 7,8...
・RAM, 9.10 ・Data transceiver, 1
1 to 13...Register, 14...Character generator,
15.16...Shift register, 17...Load mode flip-flop, 18...Control element, 2
0...Microprocessor. Patent Applicant: Honeywell Information Systems, Inc. (5 others) F/θ3 1814 Hθθ 1X'S Nanadai Ares F/θ 9 Continued from page 10 Inventor Tortus El Mare America--
Junior Mellon Ki United States of America New Hampshire 0304α Hollis, Tadrive 31 Procedural Amendment (Method) 1. Indication of the case Showa Sg Year Peep V Request No. 1]/2 Rifugan) 1-1 Software 1: Given data t L/- Thousands of images 3, Person making the amendment Relationship with the case Applicant Address , λ, Kito Haoiya = I no In 7th Meshikun ° Shi 8 Te' Sui Inko〃V-Dead 4, Agent

Claims (5)

[Claims] (1) has a mode for generating characters and attributes (i.e. one flash, underline, etc.), a mode for loading characters and attributes;
A system clock Y that is loaded with first and second digital signals in each clock cycle during a load mode representing different characters and attributes, a first digital signal for generating alphanumeric characters, and attributes; a second digital signal for generating a selected character; (b) a first device connected to the first device for providing a path for the first digital signal to be loaded to the first device; 2 device. a third device connected to said first and second devices for enabling said second device to write to said first and second devices; a fourth device connected to the device for storing the first digital signal in predetermined row and column addresses; Enough column CC to remember
-), each row further comprising a predetermined number of scanning lines (8), and further comprising a predetermined number of rows (r). (2) said column is divided into left and right columns, said left column being for storing a first digital signal representing a character, and said second column being for storing said second digital signal representing an attribute; 2. A software-based digital image device as claimed in claim 1, wherein the software digital image device is for storing digital signals. (3) The first digital signal also forms part of an address for loading the first digital signal into the first device. digital imaging device with software. 4. The second digital signal also forms part of an address for loading the second digital signal into the first device. Software-based digital imaging device. (5) said fourth device comprises one row of characters and attributes, the left-hand column representing a range of addresses, and the number in the top position of each column representing a stored character and part of the address of this character; A software-based digital signal processing apparatus according to claim 1, characterized in that the first and second digital signals are stored in the following typical pattern representing:
image device. That is, ``1'''P'l F-1+ ++ +-1+
-F-1 + t-t F-1 ('4''YamaruyamaYamayamayamaYoyamaYamaruyamayamap@p-1yenp@MaruyamayamayamaMaruyamayamayamayamayamamaruyama0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 b