JPS6061943A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To change instantaneously a high-speed reproduction mode to a low- speed reproduction mode or a standard reproduction mode, by switching the gain of a capstan control system by the detection signal of a frequency discriminating means when the rotational frequency of a capstan is smaller than a prescribed frequency. CONSTITUTION:A capstan motor has a switch to a low-speed drive mode from a high-speed drive mode, and the frequency of the output signal of an amplifier 4 is gradually lowered. A frequency discriminating circuit 26 generates a detection signal when the output of the amplifier 4 is lowered down to a prescribed frequency which is slightly higher than the frequency obtained in a low-speed reproduction mode. Both gates 28 and 15 are changed to an ON state from an OFF state by the above-mentioned detection signal. The gain to be corrected is reduced when the gate 15 conducts. This can decrease the time needed for a switch to a low-speed reproduction mode from a high-speed reproduction mode.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a magnetic recording/reproducing device.

The structure of a conventional example and its problems A conventional magnetic recording/reproducing device (hereinafter referred to as a VTR) will be explained with reference to the drawings.0 Figure 1 shows a conventional VTR.
FIG. 2 is a block diagram of main parts of the capstan servo circuit of FIG. In the figure, 11/i is a drive circuit, and the key 1-5 drives the Yapstan motor 2. 3 is a frequency generator (
(hereinafter referred to as FG). The output of Fe2 passes through an amplifier 4 and a frequency divider circuit 6. 6. 7 respectively. Frequency division ratio of frequency division circuit 5 is 1/4, frequency division ratio of frequency division circuit 6 is 1/m1
The relationship Q)m>n holds between the frequency division ratio 1/n of the frequency divider circuit 7.

Frequency dividing circuit 5. 6. The output ends of 7 are connected to gates 8°9.1o, respectively. 11 is a speed comparison circuit (game) 8. 9. Output of 10 and reference signal 11
Compare the speeds and output a voltage according to the speed error. The speed error voltage C output by the speed comparison circuit 11 is supplied to the inverting input terminal of the differential amplifier 19 via the resistor 13. A non-inverting input terminal of the differential amplifier 19 is grounded via a resistor 2o.

The output of the differential amplifier circuit 1e is applied to the drive circuit 1 and is fed back to the negative input terminal of the operational amplifier via the resistors 16, 17, 18 and the gate 14.16. resistance 1
ld I'h > R2 > R53.
] The following relationship holds true. The above circuits 1 to 2o form one loop of the cabstan system.

Reference numeral 21 denotes a gain switching circuit, which is configured by 13 to 2 degrees, and is used to correct changes in the loop gain of the capstan control system due to switching of the rotational speed of the capstan motor 2.

Reference numeral 22 is an input terminal for applying a command signal d for a high-speed reproduction mode that drives the capstan motor 2 at high speed.

Gate 8 is set to 0N-OF by high-speed playback mode command signal d.
The gate 8 is conductive only in the high-speed reproduction mode. 23 is an input terminal for applying a standard reproduction mode command signal e for driving the capstan motor 2 at a standard speed. In response to the standard playback mode command signal e, gates 9 and 14 are set to 0N-OFF, and gates 9 and 14 are turned off only in the standard playback mode.
becomes conductive. Reference numeral 24 is an input terminal for applying a command signal f for a low-speed regeneration mode that drives the capstan motor 2 at a low speed. Due to the low speed playback mode command signal f,
Game) 10 and gate 16 are 11 Kaisho GO-61943
(2) ON-OFF controlled, gate 1 only in low speed mode
0 and gate 15 become conductive. The above is the configuration of the conventional example. Next, the operation in each mode will be explained. In the high-speed reproduction mode, gate 8 becomes conductive, and gates 9,
Since drive circuit 1.1o and gates 14 and 15 are cut off, drive circuit 1. Capstan motor 2. Fe2. amplifier 49
Frequency divider circuit 5° gate 8. Speed comparison circuit 11. The gain switching circuit 21 forms a cab's tan system loop. At this time, the gain of the gain switching circuit 21 is determined only by the resistor 16. Gate 9 in standard playback mode
And the gate 14 becomes conductive, and the gates 8I 10 and 16 become cut off.

Drive circuit 1. Capstan motor 2t Fe2P amplifier 4 frequency divider circuit 6. Gate 9. The speed comparison circuit 11 and the gain switching circuit 21 form a capstan control system loop. At this time, the gain of the gain switching circuit 21 is determined by a parallel circuit of a resistor 16 and a resistor 17. In the low-speed reproduction mode, the gates 1o and 16 are conductive, and the gates 8, 9, 6, and 14 are cut off, so that the drive circuit 1, capstan motor 21, FG3s, amplifier 4, frequency divider circuit 7. Gate 10. Speed comparison circuit 11. Gain switching circuit 2
1 creates a cabstan system (goods) system loop. At this time, the gain of the gain switching circuit 21 is determined by the parallel circuit of the resistor 16 and the resistor 18. Gain switching circuit 2
1, the gain is switched to the optimum gain according to the capstan motor rotation speed in each mode. As mentioned above, the resistance values of resistors 16, 17, and 18 are n, , R2
, R3 has the relationship R+ > R2 > R3, and the gain is proportional to the resistance, so the nominal gain is 01 in the high-speed playback state.
%The relationship G1>G2>G3 holds between the gain G2 in the standard playback state and the gain G5 in the slow playback state. However, in the configuration of this conventional example, the gain switching circuit 21 also operates at the same time as the mode switching, so when switching from the high speed playback state to the standard playback state or the low speed playback state, the gain of the gain switching circuit 21 is switched from C1 to 02 or G3. Change. That is, capstan motor 2
Even though it is still rotating 6 pages in a state close to high-speed drive, the gain is small, so the coordination of the capstan motor is poor, and it takes a considerable amount of time to reach the specified rotation speed. .

OBJECTS OF THE INVENTION It is an object of the present invention to provide a magnetic recording and reproducing apparatus that enables an instantaneous transition from a high speed reproducing state to a low speed reproducing state or a standard reproducing state.

Structure of the Invention The magnetic recording and reproducing apparatus of the present invention includes a tape transport means for feeding a magnetic tape, a cabstan control means for switching the tape transport means from high-speed drive to low-speed drive or standard drive, and a signal corresponding to the rotational speed of the capstan. During the period when the output signal of the signal generating means is below a predetermined frequency, the gain of the capstan control system is determined by the frequency determining means that generates a detection signal and the detection signal. and gain switching means for switching.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of main parts of a capstan servo circuit using the present invention. 1 to 24 in the figure are the same as those in FIG. 1, so their explanation will be omitted.

Reference numeral 26 denotes a frequency discrimination circuit that generates a detection signal during a period when the output a of the amplifier 4 is below a predetermined frequency in the standard reproduction state. 26 is a frequency discrimination circuit that generates a detection signal during a period when the output a of the amplifier 4 is below a predetermined frequency in the low-speed reproduction state. 27 is a gate, and the output of the frequency discrimination circuit 51 enables the 0N-OFF control.
and becomes conductive only when a detection signal is output. 28 is a gate, and 0m is determined by the output of the frequency discrimination circuit 26.
1t-OFF is suppressed, and becomes conductive only when a detection signal is output. FIG. 3 is a timing chart of the capstan servo circuit using the present invention when switching from a high-speed reproduction state to a low-speed reproduction state. FIG. 3 will be explained based on FIG. 2. 3(A) is a high speed reproduction mode command signal d%. FIG. 3(A) is a low speed reproduction mode command signal e. The mode switching command at time a switches from the high-speed playback mode to the low-speed playback mode. Figure 3(C) shows amplifier 4
With the mode switching at time a, the capstan motor begins to shift from high-speed drive to low-speed drive, and the frequency of the output signal of the amplifier 4 gradually decreases accordingly. FIG. 3(D) shows the output signal of the frequency discrimination circuit 26. When the output signal of the amplifier 4 drops to a predetermined frequency that is slightly higher than the frequency in the low-speed reproduction state, the frequency discrimination circuit 26 generates a detection signal. This is the time. Figure 3 (g)) shows the operation of the gate 28,
Figure (F) shows the operation of the gate 15. The detection signal causes the gate 28 to change from the OFF state to the ON state, and at the same time, the gate 15 also changes from the OFF state to the ON state.Gate 1
15 becomes conductive, the gain corrected becomes smaller.

In the conventional example, the gain of the gain switching circuit 21 was also switched at the same time as the mode was switched at time a.
By using the present invention, a time difference is provided between mode switching (time a) and gain switching (time b). FIG. 4 is a graph showing the relationship between the 91' rotation speed of the capstan motor and time when switching from the high speed regeneration state to the low speed regeneration state. 29 in the figure is a graph when the present invention is used. a is a mode switching point at which the high-speed playback mode is switched to the low-speed playback mode.

The rotational speed of the capstan motor at this time is a predetermined rotational speed N1 in the high-speed regeneration state, and the rotational speed decreases after the mode switching point a. b is the point at which the capstan motor decreases to a predetermined rotation speed N2 and the frequency discrimination circuit 26 generates a detection signal. In this respect, the gain of the gain switching circuit 21 is made small. C1 is the point at which the capstan motor has decreased to a predetermined rotation speed N51 in the low speed regeneration state. When transitioning from a to b, the correction gain is large, so the correlation is good and the slope becomes steep. b to 01
When shifting to , the correction gain is small, so the slope becomes gentle. 3 is a graph of a conventional example. At the mode switching point a, the gain of the gain switching circuit 21 also decreases, so the coordination of the capstan motor deteriorates, and the rotational speed gradually decreases. C2 is the point at which the capstan motor has decreased to a predetermined rotational speed in the low speed regeneration state and has reached a 10/- speed. Therefore, in the case of the conventional example, it takes time (tzto) from point a, at which the high-speed reproduction mode is switched to the low-speed reproduction mode, to point 02, at which the predetermined rotational speed N3 is reached in the low-speed reproduction state. Therefore, by using the present invention, it is possible to shorten the time required for transition from a high-speed reproduction state to a low-speed reproduction state.

Further, the main parts of this embodiment will be specifically explained using FIG. 6. FIG. 6 shows a concrete configuration of the frequency discrimination circuit 26 shown in FIG. 2. In FIG. In the figure, 31 is an AND circuit, 32 is an H
AND circuit %33 is a resistor, and 34[5V terminal %35 is a capacitor. Reference numeral 36 is a mono multi that, when a trigger pulse is applied again before the output pulse ends, outputs a new output determined by the OR time constant from that point on (hereinafter referred to as a retriggerable mono multi).Retriggerable mono multi 36
Explain the operation. When the terminal M is grounded and the input signal a is input to the terminal B, the resistance 33
．． An output g determined by the time constant of the capacitor 36 is output. (An inverted signal 1 11'-: h is output from the terminal. When the input j of the CD terminal is set to L level, the output g of the Q terminal becomes L level regardless of the input to the A terminal and B terminal, and the output of the Q terminal It becomes H level.

Next, the retriggerable mono multi 36 that operates as described above
26 shows the operation of the frequency discrimination circuit shown in FIG. from the input terminal 37 connected to the B terminal
The output of the amplifier in FIG. 50 is input. 39 is an input terminal for a low speed reproduction mode command signal, and 38 is an output terminal for a gate control signal shown in FIG. 254.

FIG. 6 is a timing chart of each signal shown in FIG. The timing chart shown in FIG. 6 will be explained based on the circuit configuration shown in FIG. Figure 6 (A) u Figure 2 The output of the amplifier in Figure 4 (hereinafter referred to as input a), Figure 6 (B) is the output g of terminal Q, Figure 6 (C) is the output of the terminals, Figure (D) shows the low-speed playback mode command signal f, and Figure 6 (G)) shows the NAND
The output j1100 of the circuit 32 is the output i of the AND circuit 31. At time a, the high speed playback mode is switched to the low speed playback mode.

In the high-speed playback mode before mode switching, the low-speed playback mode is at L level, so the output j of the NAND circuit 32 becomes H level. Therefore, the CD terminal becomes H level, and the lid coupler monomulti 36 operates normally. The time constant of the output of the retriggerable monomulti 36 is determined by the resistor 33 and the capacitor 35. This time constant is set slightly smaller than the cycle of input signal a when the capstan is rotating at a predetermined rotation speed in the low-speed playback state, so the time constant is set to be slightly smaller than the cycle of input signal a in the high-speed playback state. is larger, and the output g of the Q terminal is always at H level. Since the Q terminal output hldL level, AND circuit 3
The output i of 1 becomes L level. In the low-speed playback mode after switching the mode at time a, the low-speed playback mode command signal f[ becomes H level, but since the Q terminal output hldL level state is maintained, the output j of the NA) iD circuit 32 becomes H level. maintain the condition. That is, the CD terminal [is at H level, and the retriggerable monomulti 36 operates in the same manner as before the mode switching. After switching the mode at time a, the rotational speed of the capstan gradually decreases (131), and the period of the input signal f increases. The time is the time when the period T of the input signal a becomes larger than the time constant τ of the retriggerable monomulti 36. At this time, the output g of the terminal Q changes from H level to L level, and the output h of the terminals changes from H level to L level.
Since the idL level is switched to the H level, the output j of the NAND circuit 32 becomes the L level. In other words, the CD terminal is L
level, and the retriggerable monomulti 36 is reset.

The output g of the Q terminal is fixed at L level, and the output of the terminal capable terminal is fixed at H level. Therefore, the output of the AND circuit 31 becomes H level, and the gate 28 in FIG. 2 is turned on from the OFF state.
Switch to state. In the above embodiment, the configuration of the frequency discrimination circuit shown in FIG. 2 when switching from high-speed playback mode to low-speed playback mode was explained using a specific example using the retriggerable mono multi 36, but this system is not applicable to high-speed playback mode. The frequency discrimination circuit shown in FIG. 26 when switching from to standard playback mode can also be used in the same way.

Effects of the Invention As is clear from the above explanation, the present invention has a magnetic tape 141"
- A capstan for transporting the jeep, a capstan control means for switching the capstan from high speed drive to low speed drive or standard drive when switching from high speed playback state to low speed playback state or standard playback state, and a signal corresponding to the rotation speed of the capstan. a signal generating means for generating a signal, a frequency determining means for generating a detection signal during a period when the output signal of the signal generating means is below a predetermined frequency and wave number, and a gain switching means for switching the gain of the capstan control system according to the detection signal. When switching from high-speed playback mode to low-speed playback mode or standard playback mode, the time required for the capstan motor to reach a predetermined rotation speed is shortened. It has the excellent effect of being able to realize tape feeding that is exactly the same as the movement of the search dial (the movement of the hand that turns the dial).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of a conventional VTR capstan servo circuit, and FIG. 2 is a VTR according to an embodiment of the present invention.
A block diagram of the main part 161-2 of the capstan servo circuit, and FIG. 3 is a timing chart of input and output signals of the circuit. FIG. 4 is a characteristic diagram showing the relationship between the rotation speed and time of the capstan motor of the same VTR, FIG. 5 is a circuit diagram of the main part of the same circuit, and FIG. 6 is a timing chart of output signals of the same circuit. 1...Drive circuit, 2...Capstan motor, 3...FC, 4...Amplifier,
5... Frequency divider circuit, 6... Frequency divider circuit, 7
...Frequency divider circuit, 8...Gate, 9...
...Gate, 10...Gate, 11...
...Speed comparison circuit% 12...Reference signal, 1
3...Resistance, 14...Gate, 16.
...Gate, 16...Resistance, 17...
...Resistance, 18...Resistance, 19...
Differential amplifier, 2o...Resistance, 21...
Gain switching circuit %22...Input terminal for high-speed playback mode command signal, 23...Input terminal for standard playback mode command signal, 24...Input for low-speed playback mode command signal Terminal, 26... Frequency discrimination circuit, 2
7... Frequency discrimination circuit, 27... Gate, 28... Gate %29... Graph using the present invention, 30... Conventional example graph, 3
1...AND circuit, 32...NAND
AND circuit...Resistor, 34...5V terminal, 36...Capacitor, 36...Retriggerable mono multi, 37...Input terminal, 3
8... Output terminal, 39... Input terminal for low speed playback mode command signal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure tIOtIt2 time

Claims (1)

[Claims] tape transport means for transporting the magnetic tape; control means for switching the tape transport means from high-speed drive to low-speed drive or standard drive; and signal generation means for generating a signal according to the rotational speed of the tape transport means; A magnetic recording and reproducing device comprising: a frequency determining means for generating a detection signal during a period when the output signal of the signal generating means is below a predetermined frequency; and a gain switching means for switching the gain of the side means according to the detection signal. .