JPS6060712A - Infrared ray heating method - Google Patents

Infrared ray heating method

Info

Publication number
JPS6060712A
JPS6060712A JP16998683A JP16998683A JPS6060712A JP S6060712 A JPS6060712 A JP S6060712A JP 16998683 A JP16998683 A JP 16998683A JP 16998683 A JP16998683 A JP 16998683A JP S6060712 A JPS6060712 A JP S6060712A
Authority
JP
Japan
Prior art keywords
power
annealing
heated
sides
infrared
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16998683A
Other languages
Japanese (ja)
Inventor
Hiroshi Nishimura
博 西村
Shigezo Makino
牧野 繁蔵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Machinery Inc
Original Assignee
Nichiden Machinery Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichiden Machinery Ltd filed Critical Nichiden Machinery Ltd
Priority to JP16998683A priority Critical patent/JPS6060712A/en
Publication of JPS6060712A publication Critical patent/JPS6060712A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Abstract

PURPOSE:To enable to perform an annealing process on both sides of the material to be heated simultaneously by heating both sides of the material to be heated at different temperatures by a method wherein a device for adjustment of supplied electric energy is provided independently on the infrared ray heating lamps which are opposingly arranged on the front and back sides of the material to be heated. CONSTITUTION:The programed power sent from a common power source 9 is supplied to power controllers 13a and 13b through power ratio setting devices 14a and 14b, and each lamp 6 of infrared ray lamp groups 8a and 8b is lighted up using the power set for each lamp group by the setting devices 14a and 14b. The setting devices 14a and 14b output the power W1 of W0Xx% (x=0-100) and the power W2 of W0Xy% (y=0-100) by independently and selectively setting the inputted common power W0 within the range of 0-100%. The power ratio set values (x) and (y) are determined by manual operation performed from outside. As a result, workability is improved due to reduction in annealing manhours, and the improvement in quality can also be contrived by performing an annealing simultaneously on the front and back sides of the material to be heated.

Description

【発明の詳細な説明】 イ、産業上の利用分野 この発明は特に半導体素子製造におけるウェーハのアニ
ール(焼鈍)処理工程等で賞用される赤外線加熱方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to an infrared heating method which is particularly useful in wafer annealing processes in semiconductor device manufacturing.

口、従来技術 半導体ウェーへの加熱処理工程における目的にはイオン
注入後やポリシリコン層形成後のアニールの他に、ポリ
シリコン層の低抵抗化、再結晶化や半導体ウェー八表裏
両面へのアルミニウムやニッケルやクロムなどのメタル
のシンタリングやアロイ化などがあり、これらの場合に
は、加熱手段には一般に電気炉が使用されている。しか
し、最近の半導体技術における素子のVLS I化によ
る高密度・高精度化に伴い電気炉アニールでは半導体ウ
ェーハ内の高濃度不純物領域での不純物の電気的活性化
などに限界が見え始め、時代の進展に応じた新しいアニ
ール技術の開発が待たれている。
In addition to annealing after ion implantation and polysilicon layer formation, the purposes of the conventional heat treatment process for semiconductor wafers include lowering the resistance of the polysilicon layer, recrystallization, and applying aluminum to both the front and back surfaces of the semiconductor wafer. There are also sintering and alloying of metals such as nickel and chromium, and in these cases, an electric furnace is generally used as a heating means. However, with the recent trend toward higher density and higher precision due to VLSI devices in semiconductor technology, electric furnace annealing has begun to reach its limits in terms of electrical activation of impurities in high concentration impurity regions within semiconductor wafers. The development of new annealing technology in line with progress is awaited.

新しいアニール技術としてはレーザアニール法や電子ビ
ームアニール法、赤外線アニール法などが文献等で報告
され、その中で半導体ウェーへのように平板状で広面積
のものを同時に均一加熱するに有効で実用段階に入って
いるものに赤外線ランプを使った赤外線アニール法があ
る。この赤外線アニール法による半導体ウェーへのアニ
ール装置例を第F図乃至第3図を参照しながら説明する
New annealing techniques such as laser annealing, electron beam annealing, and infrared annealing have been reported in the literature, and among them, they are effective and practical for uniformly heating flat, wide-area objects such as semiconductor wafers. An infrared annealing method using an infrared lamp is currently in the process. An example of an apparatus for annealing semiconductor wafers using this infrared annealing method will be described with reference to FIGS. F to 3.

第1図及び第2図において、(1)は被加熱物の半導体
ウェーハ、(2)はアニール用加熱炉、(3)(3)は
半導体ウェーハ(1)を支持して加熱炉(2)の内外に
搬入・搬出する石英製支持アニール、(4a) (4b
)は加熱炉(2)内の上下2箇所に対向配置した赤外線
加熱装置で、この両者の中間に半導体ウェーハ(1)が
位置決め搬入されて表裏両面のアニール処理が行われる
。上部赤外線加熱装置(4a)は1つの横断面放物線形
の樋状反射鏡(5)と、この反射鏡(5)の焦点位置に
設置された1灯の直線状赤外線ランプ(6)からなる−
組の加熱要素(7)を複数組、例えば4組並列に固定配
置したものを各赤外線ランプ(6)(6)−を下に向け
て加熱炉(2)向上部に固定した構造である。下部赤外
線加熱装置(4b)は上記と同一構造の加熱要素(7)
を例えば5組並列に固定配置したものをその赤外線ラン
プ(6)(6)・−を上にして加熱炉(2)内の下部に
固定したもので、この下部の赤外線ランプ群(8b)と
上部の赤外線ランプ群(8a)は半導体ウェーハ(1)
をより均一加熱するため互いに位置をずらせて設置され
る。
In Figures 1 and 2, (1) is a semiconductor wafer to be heated, (2) is an annealing heating furnace, and (3) (3) is a heating furnace (2) supporting the semiconductor wafer (1). (4a) (4b)
) is an infrared heating device disposed oppositely at two locations, upper and lower, in a heating furnace (2), and a semiconductor wafer (1) is positioned and carried between the two, and annealing processing is performed on both the front and back surfaces. The upper infrared heating device (4a) consists of one gutter-shaped reflector (5) with a parabolic cross section and one linear infrared lamp (6) installed at the focal point of this reflector (5).
It has a structure in which a plurality of sets, for example four sets, of heating elements (7) are fixedly arranged in parallel and fixed to the upper part of the heating furnace (2) with each infrared lamp (6) (6) facing downward. The lower infrared heating device (4b) is a heating element (7) with the same structure as above.
For example, five sets of infrared lamps (6), (6), and - arranged in parallel are fixed at the bottom of the heating furnace (2) with the infrared lamps (6), (6), and - facing upward, and the lower infrared lamp group (8b) and The upper infrared lamp group (8a) is a semiconductor wafer (1)
They are placed at different positions from each other in order to heat them more evenly.

半導体ウェーハ(1)のアニールはその表面m及び裏面
nの両面が対象となり、この両面のアニール温度(熱反
応温度)は同一の場合もあるが通常は両面状態が異なる
等して異なる温度で行われる。また加熱炉(2)に搬入
された半導体ウェーハ(1)のアニールは表裏両面を赤
外線輻射で表層部を10数秒程度の短時間で高温加熱し
て行われ、この加熱に供される上下の赤外線ランプ群(
8a) (8b)の各赤外線ランプ(6)(6)・−の
点灯は第3図に示す回路でもって行われている。即ち、
第3図において、(9)は共通電源、(10)は共通電
源(9)から各赤外線ランプ群(8a) (8b)に供
給される電力量を決めるプログラマ−1(11)はプロ
グラマ−(10)のプログラム設定器で、ここで設定さ
れた電力が各赤外線ランプ群(8a) (8b)の各赤
外線ランプ(6)(6)−に共通に供給されて各赤外線
ランプ(6)(6)−が同一パワーで同時点灯して半導
体ウェーハ(1)の表裏両面を同時加熱する。尚、(1
2a ) (12b )は各赤外線ランプ群(8a) 
(8b)の入力ゲートであるサイリスタ、(13a )
 (13b )は各赤外線ランプ群(8a) (8b)
に供給される電力を、ランプ回路からフィードバックさ
れる電流Iと電圧■をパラメータとして制御し一定に保
持する電力コントローラである。
Annealing of the semiconductor wafer (1) targets both its front surface m and back surface n, and although the annealing temperature (thermal reaction temperature) for both surfaces may be the same, it is usually performed at different temperatures because the conditions of both surfaces are different. be exposed. The semiconductor wafer (1) carried into the heating furnace (2) is annealed by heating the surface layer to a high temperature in a short period of about 10 seconds using infrared radiation on both the front and back surfaces. Lamp group (
The lighting of each of the infrared lamps (6) (6), (8b), and (8a) and (8b) is performed by the circuit shown in FIG. That is,
In Fig. 3, (9) is a common power source, (10) is a common power source (9), and programmer 1 (11) is a programmer (11) that determines the amount of power supplied from the common power source (9) to each infrared lamp group (8a) (8b). 10), the power set here is commonly supplied to each infrared lamp (6) (6) of each infrared lamp group (8a) (8b). )- are turned on at the same time with the same power to simultaneously heat both the front and back sides of the semiconductor wafer (1). Furthermore, (1
2a) (12b) is each infrared lamp group (8a)
Thyristor (13a) which is the input gate of (8b)
(13b) is each infrared lamp group (8a) (8b)
This is a power controller that controls and holds the power supplied to the lamp constant using the current I and voltage (2) fed back from the lamp circuit as parameters.

ハ6発明が解決しようとする問題点 ところで、第3図回路によるアニール処理は半導体ウェ
ーハ(1)の表裏両面を同一温度に加熱して行う場合は
問題無いが半導体ウェーハ(1)の表面mと裏面nとの
材質や表皮状態等の差によりアニール処理温度に差があ
る場合は、この両面m、nを同時にアニールするわけに
はいかない。そこで両面m、nのアニール処理温度に差
がある場合は先ず高いアニール温度で加熱して片面のア
ニール処理を行い、次に低くいアニール温度で加熱して
残り片面のアニール処理を行う等して交互に行っている
。そのため1枚の半導体ウェーハ(1)の表裏両面のア
ニールに2工程を必要として作業性が悪く、また表裏両
面が2回加熱されるので処理内容的に信頼性が低くて赤
外線アニール法の実用面への応用を難しくしていた。
Problems to be Solved by the Invention Incidentally, there is no problem when the annealing process using the circuit shown in FIG. 3 is performed by heating both the front and back sides of the semiconductor wafer (1) to the same temperature. If there is a difference in annealing temperature due to differences in material, skin condition, etc. from the back side n, it is not possible to anneal both sides m and n at the same time. Therefore, if there is a difference in the annealing temperature for both sides m and n, first heat at a higher annealing temperature to anneal one side, then heat at a lower annealing temperature and anneal the remaining side. They are taking turns. Therefore, two steps are required to anneal both the front and back sides of one semiconductor wafer (1), resulting in poor workability.Also, since both the front and back sides are heated twice, the reliability of the process is low, making the infrared annealing method difficult to implement. This made it difficult to apply.

二0問題点を解決するための手段 本発明は上記問題点に鑑み、これを解決するための手段
として半導体ウェーハ等の被加熱物の表裏両面に対向配
置された加熱用赤外線ランプに夫々独立的に0〜100
%の範囲で供給電力量調整を行う手段を設定したことを
特徴とする。従って、上記手段により被加熱物の両面を
夫々異なる温度で同時加熱して両面同時アニールするこ
とが可能になり、また片面のみのアニールも可能となる
20 Means for Solving the Problems In view of the above-mentioned problems, the present invention provides a means for solving the problems by independently providing heating infrared lamps arranged oppositely on both the front and back sides of an object to be heated such as a semiconductor wafer. 0-100
The present invention is characterized in that a means for adjusting the amount of supplied power is set within a range of %. Therefore, by the above means, it is possible to simultaneously heat both sides of the object to be heated at different temperatures to anneal both sides simultaneously, and it is also possible to anneal only one side.

ホ、実施例 本発明を第1図乃至第3図のアニール装置に適用した場
合、上下の各赤外線ランプ群(8a)(8b)の点灯を
第4図に示す如き回路で行う。
E. Embodiment When the present invention is applied to the annealing apparatus shown in FIGS. 1 to 3, the upper and lower infrared lamp groups (8a) and (8b) are lit by a circuit as shown in FIG. 4.

この第4図における第3図と同一符号は同一内容のもの
を示し詳細は省略する。相違点は共通電源(9)からの
プログラム設定された電力を2つの電力比設定器(14
a ) (14b )を通して電力コントローラ(13
a ) (13b )へ送り、各赤外線ランプ群(8a
) (8b)の各赤外線ランプ(6)(6)・−を群毎
に電力比設定器(14a )(14b )で設定された
電力にて点灯させることである。
The same reference numerals in FIG. 4 as in FIG. 3 indicate the same contents, and the details will be omitted. The difference is that programmed power from a common power source (9) is transferred to two power ratio setters (14).
a) through (14b) the power controller (13
a) (13b) and each infrared lamp group (8a
) The infrared lamps (6), (6), and (8b) are turned on with the power set by the power ratio setting device (14a) (14b) for each group.

各電力比設定器(14a ) (14b )は入力され
る共通電力WOを0〜100%の範囲で、各々独立的に
選択設定してWOXx%(X−0〜100 )の電力W
l、WOXY%(y=0〜100)の電力W2を出力す
る。この電力比設定値X、7は手動により外部操作され
て決められる。例えば半導体ウェーハ(1)の表面mと
裏面nのアニール温度が同一ならばx=yにして表裏両
面m、nを対応する各赤外線ランプ群(8a) (8b
)の同一パワーの同時点灯で加熱して同時アニールが行
われ、表面mと裏面nのアニール温度に差があればその
差に応じてX% y(x≠y。
Each power ratio setter (14a) (14b) independently selects and sets the input common power WO in the range of 0 to 100%, and outputs a power W of WOXx% (X-0 to 100).
output power W2 of 1, WOXY% (y=0 to 100). This power ratio setting value X, 7 is determined by manual external operation. For example, if the annealing temperature of the front surface m and the back surface n of the semiconductor wafer (1) is the same, then x=y and each infrared lamp group (8a) (8b
) are simultaneously turned on with the same power to perform simultaneous annealing, and if there is a difference in the annealing temperature between the front surface m and the back surface n, the temperature is increased by X% y (x≠y).

X≠0、y≠0)を設定して表裏両面m、nを夫々のア
ニール温度に同時加熱して同時アニールが行われる。こ
のように表裏両面m、nの同時アニールが可能なのは、
赤外線輻射による表裏両面m、nの短時間加熱が表層部
において集中的に行われるのがほぼ全てであるからであ
る。また表裏両面m、nの一方のみのアニールを行う場
合は未7二−ル側のX又はyを0%にして行うか、又は
未アニール側のX又はyを片面を予熱的に加熱する程度
に設定して行う。
Simultaneous annealing is performed by setting (X≠0, y≠0) and simultaneously heating the front and back surfaces m and n to their respective annealing temperatures. In this way, simultaneous annealing of both the front and back surfaces m and n is possible because
This is because almost all of the short-term heating of the front and back surfaces m and n by infrared radiation is concentrated in the surface layer portion. In addition, when annealing only one of the front and back surfaces m and n, it is done by setting X or y on the unannealed side to 0%, or preheating X or y on one side on the unannealed side. Set it to .

尚、本発明の実施例は上記例に限らず、特に被加熱物に
応じて赤外線ランプの配置形態を適正に設計変更するな
どしてやればよい。
Note that the embodiments of the present invention are not limited to the above-mentioned examples, and the layout of the infrared lamps may be appropriately modified depending on the object to be heated.

へ2発明の効果 本発明によれば平板状被加熱物の表裏両面を夫々の適正
アニール温度で同時加熱してアニールすることが容易に
達成できるので、アニール工数の低減化による作業性改
善、表裏両面の同時処理による品質改善が図れ、赤外線
アニール法の実用面での応用を効果的ならしめる。また
被加熱物の表裏両面の同時アニールの他、片面のみのア
ニールも他の片面を予熱的に加熱する等して実行するこ
とが容易にでき、汎用性の大なる赤外線アニールが可能
となる。
2. Effects of the Invention According to the present invention, it is possible to easily anneal both the front and back surfaces of a flat plate-shaped object to be heated at the appropriate annealing temperature at the same time. Simultaneous processing on both sides improves quality, making the practical application of infrared annealing effective. Further, in addition to simultaneous annealing of both the front and back sides of the object to be heated, annealing of only one side can be easily performed by preheating the other side, making it possible to perform infrared annealing with great versatility.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は本発明の前提技術を説明するための
もので、第1図は赤外線アニール装置の概略断面図、第
2図は第1図のA−A線に沿う断面図、第3図は第1図
の加熱回路のブロック図、第4図は本発明の具体的実施
装置例を示す赤外線アニール装置の加熱回路のブロック
図である。 (1)・・被加熱物、(6)・・赤外線ランプ、(9)
−−共通電源、(14a ) (14b ) ・・供給
電力量調整手段。
1 to 3 are for explaining the basic technology of the present invention, FIG. 1 is a schematic sectional view of an infrared annealing device, FIG. 2 is a sectional view taken along line A-A in FIG. 1, FIG. 3 is a block diagram of the heating circuit of FIG. 1, and FIG. 4 is a block diagram of the heating circuit of an infrared annealing apparatus showing a specific example of the apparatus of the present invention. (1)...Object to be heated, (6)...Infrared lamp, (9)
--Common power supply, (14a) (14b) . . . supply power amount adjustment means.

Claims (1)

【特許請求の範囲】[Claims] (1) 平板状被加熱物の両面近傍に各々対向配置した
上下又は左右一対の加熱用赤外線ランプに夫々独立的に
供給電力量調整手段を設けて、被加熱物の両面を同時加
熱又は片面選択加熱を行うようにしたことを特徴とする
赤外線加熱方法。
(1) A pair of upper and lower or left and right heating infrared lamps placed opposite each other in the vicinity of both sides of a flat plate-shaped object to be heated is provided with power supply adjustment means independently, so that both sides of the object to be heated can be heated simultaneously or one side can be selected. An infrared heating method characterized by heating.
JP16998683A 1983-09-13 1983-09-13 Infrared ray heating method Pending JPS6060712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16998683A JPS6060712A (en) 1983-09-13 1983-09-13 Infrared ray heating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16998683A JPS6060712A (en) 1983-09-13 1983-09-13 Infrared ray heating method

Publications (1)

Publication Number Publication Date
JPS6060712A true JPS6060712A (en) 1985-04-08

Family

ID=15896474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16998683A Pending JPS6060712A (en) 1983-09-13 1983-09-13 Infrared ray heating method

Country Status (1)

Country Link
JP (1) JPS6060712A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5118378A (en) * 1989-10-10 1992-06-02 Hitachi, Ltd. Apparatus for detecting an end point of etching
JP2020537863A (en) * 2017-10-17 2020-12-24 フェイスブック,インク. Systems and methods for monitoring power line conductors with relevant fiber optic cables

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846623A (en) * 1981-09-16 1983-03-18 ウシオ電機株式会社 Epitaxial growth method of amorphous silicon or polycrystalline silicon on wafer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846623A (en) * 1981-09-16 1983-03-18 ウシオ電機株式会社 Epitaxial growth method of amorphous silicon or polycrystalline silicon on wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5118378A (en) * 1989-10-10 1992-06-02 Hitachi, Ltd. Apparatus for detecting an end point of etching
JP2020537863A (en) * 2017-10-17 2020-12-24 フェイスブック,インク. Systems and methods for monitoring power line conductors with relevant fiber optic cables

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