JPS6059762B2 - muting amplifier - Google Patents

Description

[Detailed Description of the Invention] The present invention has an amplification ability and can reduce the degree of amplification to zero using a control signal, and at the same time does not produce a DC fluctuation, so-called click sound, in the output. , power supply O
The present invention relates to a muting amplifier that can prevent the generation of click sounds even during the N/OFF state, and particularly relates to a muting amplifier suitable for IC implementation.

For audio equipment, such as radios, stereos, recorders, etc., you must operate various switches, turn the power on and off, etc.
It is desired that no clicking sound be produced when FF is performed.

For this reason, various types of ink systems have been proposed and put into practical use, but many of them generate a slight clicking sound or are large, like relays. As integrated circuits (ICs) have become more popular in recent years, the need for muting circuits that can be integrated into ICs has increased.

With this background in mind, the present invention has been developed to
To provide a muting amplifier which does not emit a click sound at times and can completely prevent the click sound even during operation.

FIG. 1 shows one embodiment of the present invention.

1 is a first current mirror, and transistors Ql, Q2
, resistors Rl and R2.

Transistors Q3 and Q4 constitute a differential amplification stage, and the collector current of transistor Q2 is used as an emitter bias current. 2 is a second current mirror and transistors Q5 and Q
6, resistors R3 and R4, and inputs the collector current of transistor Q3.

3 is a third current mirror, which includes transistors Q7, Q8,
It consists of resistors R5 and R6, and receives the collector current of transistor Q6 as input.

4 is the fourth current mirror and transistors Q9 and QlO
, resistors R7 and R8, and uses the collector current of the transistor Q4 as an input current.

Qll, Ql2, Ql3, Ql4, Ql5, R9, Rl
O, Rll, and Rl2 are class B push-pull output stages. Of these, transistors Qll, Ql2, and R9 constitute a bias voltage circuit. The transistor Ql3 is a positive side output transistor, and Ql4 and Ql5 are negative side output transistors connected in a Darlington manner. RlO and Rll are small resistances for protecting the output transistor. A feedback resistor Rl is connected between the output terminal 7 and the base of the transistor Q3.
6, and a resistor Rl5 is connected between the base of the transistor Q3 and ground. The base of transistor Q4 is connected to input terminal 6 and grounded via Rl4. Output terminal 7 and . Rl3 is connected between ground. This embodiment is assumed to operate with voltages of +Vcc and -Vcc (volts). A resistor Rl7 is connected to the transistor Q1 of the current mirror 1, and the other end is connected to the control terminal 5. ■Cc or VO is connected to the control terminal 5 as shown in FIG. Either of the lower voltages ON is applied. In the above configuration, the voltage V.

When N is applied, 21A flows into transistor Q1,
A current equal to this becomes the emitter bias of the differential input stage. Input voltage■. When N is O■, IA flows through each of transistors Q3 and Q4. current mirror 2,
When the mirror coefficients of 3 and 4 are 1, the input current and output current of the current mirror are equal, so transistors Q5 and Q6
, Q7, Q8, Q9, and QlO become equal, IA flows through transistors Qll and Ql2 of the bias voltage circuit, a bias voltage is generated, and the output transistor becomes active. On the other hand, when input voltages V and N are applied to input terminal 6, the collector currents of transistors Q3 and Q4 become unbalanced, and eventually transistors Q8 and Ql
The collector current of O becomes unbalanced.

Unbalanced current is caused by output transistor Ql3 or Ql
Since it becomes the base current of 4 and drives the output stage,
Open loop gain will be very high. The closed loop gain is (Rl5+Rl6)/R due to the feedback of resistor Rl6.
It becomes l5. Here, when the control voltage of the control terminal 5 becomes Vcc, the transistors Ql and Q2 become 0FF, and the bias current of the differential input stage becomes zero.

Therefore, all of the transistors Q3 to Ql5 have their base currents zero, and therefore become 0FF.
In this state, the amplification function is lost, the input voltages V and N are not transmitted to the output terminal 7, and the output terminal 7 is
It is in a state where it is grounded via l6 and Rl5. At this time, there are many 0FF transistors between the input terminal 6 and the output terminal 7, so the input voltage ■! Leakage (feedthrough) of N to the output terminal 7 is extremely small. Whether the control voltage is Vcc or VON, the input voltage is V.

In the state where N=0, the output voltage VOUT is 0V.
The control voltage is V. The change in the output voltage VOUT in the process of gradually changing from N to Vcc is very small and can be reduced to substantially 0 volts. For this purpose, transistors Q8 and QlO
It is preferable that the corctor currents of the transistors are always balanced and that the characteristics of the transistors Qll and Ql3 and Ql2 and Ql4 are well balanced. The balance of the above characteristics can be easily achieved in integrated circuits. The mirror coefficients of the current mirrors 2, 3, and 4 are preferably stable over a wide range of operating currents.

GM the mirror coefficients of current mirrors 2, 3, and 4
2, GM3, and GM4, the output currents of current mirrors 3 and 4 are balanced if always satisfied. For this purpose, it is preferable that the HFE of the transistor is high, but in reality it takes a finite value, so it deviates from equation (1). In order to prevent this shift, an improved current mirror as shown in FIGS. 2 to 4 may be used.
FIG. 2 shows a current mirror in which the mirror coefficient approaches 1 by causing the base currents of transistors QlOO and QlOl to flow through QlO2. FIG. 3 shows a known Wilson type current mirror. FIG. 4 shows a current mirror in which the adverse effect of the Early effect of the transistor is removed by making the transistor QlO4 of FIG. 3 Darlington. Furthermore, the resistor Rl2 in the output stage of FIG. 1 is inserted to bring the operating currents of the transistors Ql2 and Ql4 close to each other.

Instead, as shown in FIG. 5, if the collector current of transistor Ql4 is supplied from transistor Q2OO, since the collector currents of transistors QlO and Q2OO are equal, the emitter currents of transistors Ql2 and Ql4 will be It is balanced over a wide range and contributes to reducing click noise. When it is necessary to increase the output current of the output stage, transistors Ql3 and Q
It is better to connect l4, Ql5, etc. in parallel or to increase the area of the transistor. If it is desired to increase the current of the bias voltage circuit, the mirror coefficients GM3 and GM4 of the current mirrors 3 and 4 may be made larger than 1. Transistors Q8 and QlO are provided in parallel or multi-emitters are provided to provide multiple outputs of current mirrors 3 and 4, and an output stage such as the class B push-pull output shown in FIG. 1 is connected to each of them. From this output terminal, transistor Q3
By providing negative feedback to the output, it is possible to create a single-power amplifier with multiple outputs. In this way, common muting can be applied by controlling the current mirror 1. Moreover, the configuration becomes simple. In addition,
In the muting amplifier shown in Figure 1, if there is a large amount of feedback, there is a risk of oscillation, but this can be prevented by connecting a small capacitor at an appropriate location, for example between the collector and base of QlO and JQ8. Ru.

As explained above, the present invention moves the output current of the input differential stage to the driving point of the output stage using a current mirror,
Since a muting state is created by changing the bias current of the input differential stage, when power is applied, the balance of the transistors can be effectively utilized to prevent clicks from occurring.

Also, if the control current of the control terminal is set to zero, the power supply +■
No matter how 00 and -Vcc rise and fall, the output voltage 0UT can remain at 0 volts. Further, since negative feedback is applied during amplification operation, distortion such as crossover distortion can be reduced even with low current consumption, and these characteristics can be maximized in an integrated circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of one embodiment of the present invention, Figures 2 to 4 are circuit diagrams of a current mirror that can be used in the present invention, and Figure 5 is a circuit diagram of another embodiment of a portion of the output stage. There is. 1 to 4...First to fourth current mirrors, 5.
...Control terminal, 6...Input terminal, 7...
...Output terminal, Q3, Q4...Differential input stage, Qll to Ql5...Class B push-pull output stage, Rl6
...Return resistance.

Claims (1)

[Scope of Claims] 1. Comprising first, second, third, and fourth current mirrors, a differential input stage, and an output stage, the output of the first current mirror is transmitted to the differential input stage. A common bias current is used, the first and second outputs of the differential input stage are input to the second and fourth current mirrors, respectively, and the output of the second current mirror is input to the third current mirror. and adding the output currents of the third current mirror and the fourth current mirror to the output stage as bias currents for the output stage,
The output signal of the output stage is negatively fed back to the differential input stage to form an amplifier having a desired voltage gain, and the input current of the first current mirror is changed from a predetermined value to zero. . A muting amplifier characterized in that it is possible to prevent transmission of an input signal applied to the differential input stage to the output stage. 2. The muting amplifier according to claim 1, wherein the output stage is a class B output stage. 3 In claim 2, the second, third, and fourth
A muting amplifier characterized in that the current mirror is a current mirror having a predetermined mirror coefficient so as to output a bias current for driving an output stage. 4. In claim 2, the class B output stage comprises a bias circuit and a group of output transistors, and the operating current of the bias circuit and the operating current of the output transistor group are within the entire range of the bias current. A muting amplifier characterized in that the generation of an output offset voltage is prevented by accommodating the muting amplifier. 5. The muting amplifier according to claim 2, wherein the class B output stage is a complementary class B output stage. 6 In claim 5, the PNP side of the complementary class B output stage is connected to a PNP transistor and an NP transistor.
1. A muting amplifier characterized in that the N transistors are Darlington-connected, and the collector current of the PNP transistor is varied in accordance with the input current of the first current mirror. 7. The muting amplifier according to claim 6, wherein the collector current of the PNP transistor is varied in accordance with the output current of the fourth current mirror.