JPS6058594B2 - Planar photothyristor - Google Patents

Planar photothyristor

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Publication number
JPS6058594B2
JPS6058594B2 JP50017853A JP1785375A JPS6058594B2 JP S6058594 B2 JPS6058594 B2 JP S6058594B2 JP 50017853 A JP50017853 A JP 50017853A JP 1785375 A JP1785375 A JP 1785375A JP S6058594 B2 JPS6058594 B2 JP S6058594B2
Authority
JP
Japan
Prior art keywords
region
main surface
base layer
layer
impurity concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50017853A
Other languages
Japanese (ja)
Other versions
JPS5193679A (en
Inventor
信武 小西
隆洋 長野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50017853A priority Critical patent/JPS6058594B2/en
Publication of JPS5193679A publication Critical patent/JPS5193679A/ja
Publication of JPS6058594B2 publication Critical patent/JPS6058594B2/en
Expired legal-status Critical Current

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  • Light Receiving Elements (AREA)
  • Thyristors (AREA)

Description

【発明の詳細な説明】 本発明はホトサイリスタに係り、特に光感度の高いプレ
ーナ形ホトサイリスタに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photothyristor, and particularly to a planar type photothyristor with high photosensitivity.

発光素子と受光素子とを組み合わせたいわゆるホトカプ
ラは入出力間の絶縁分離、インピーダンス変換、広帯域
増幅あるいは高速スイッチング等の優れた機能をもつた
ユニークなデバイスである。
A so-called photocoupler, which combines a light-emitting element and a light-receiving element, is a unique device that has excellent functions such as insulation separation between input and output, impedance conversion, broadband amplification, and high-speed switching.

ホトカプラの受光素子としてホトサイリスタが用いられ
る場合、発光素子としては通常波長特性の点からGaA
s発光ダイオード(GaAs・LED)を用いる。Ga
As−LEDは一定の大きさを持つており通常の構造で
は面状に光を発光させているが、指向性はさほど鋭くな
いため発光素子と受光素子を組合せた場合ホトサイリス
タの受光面の光の照度が下がり、光の利用率が悪く電気
ゲート方式のサイリスタに比べて点弧感度が悪い。受光
面での照度を上げるため、発光素子の光を集光レンズ等
を介して受光素子へ導くことも考えられるが、ホトカプ
ラが小さい場合は組み立てが困難であり、コストも高く
つく。したがつて、ホトカプラ用のホトサイリスタとし
ては受光面積を大きくとる必要がある。しカル発光素子
の大きさやサイリスタ自体の電流容量との兼ね合いから
その面積には制限がある。一方、点弧感度を上げるため
に光電変換効率そのものを上げる工夫が必要である。光
電変換効率を高くするためには吸収係数α、少数キャリ
アの拡散距離Lp、空乏層の幅dを増大することが考え
られる。このうち吸収係数α、少数キャリアの拡散距離
Lpは材料によつて定まるが、空乏層の幅dは素子の製
造条件や使用条件で制御することができる。nベース領
域の不純物密度をNdとし、pベース領域の不純物密度
はきわめて多いとすれば順方向阻止状態での印加電圧■
に対して、空乏層の幅dは近似的に次式で示される。こ
こでEはシリコンの誘電率、eは電子の電荷であり定数
である。
When a photothyristor is used as a light-receiving element of a photocoupler, the light-emitting element is usually made of GaA from the viewpoint of wavelength characteristics.
s Light emitting diode (GaAs LED) is used. Ga
As-LEDs have a certain size and emit light in a planar shape in a normal structure, but the directivity is not very sharp, so when a light emitting element and a light receiving element are combined, the light on the light receiving surface of the photothyristor is The illumination intensity is reduced, the light utilization rate is poor, and the ignition sensitivity is lower than that of electric gate type thyristors. In order to increase the illuminance on the light-receiving surface, it is possible to guide the light from the light-emitting element to the light-receiving element through a condenser lens or the like, but if the photocoupler is small, assembly is difficult and the cost is high. Therefore, a photothyristor for a photocoupler needs to have a large light-receiving area. There is a limit to the area due to the size of the thyristor and the current capacity of the thyristor itself. On the other hand, in order to increase the ignition sensitivity, it is necessary to devise ways to increase the photoelectric conversion efficiency itself. In order to increase the photoelectric conversion efficiency, it is possible to increase the absorption coefficient α, the diffusion distance Lp of minority carriers, and the width d of the depletion layer. Of these, the absorption coefficient α and minority carrier diffusion length Lp are determined by the material, but the width d of the depletion layer can be controlled by the manufacturing conditions and usage conditions of the element. If the impurity density in the n base region is Nd and the impurity density in the p base region is extremely high, the applied voltage in the forward blocking state is
On the other hand, the width d of the depletion layer is approximately expressed by the following equation. Here, E is the dielectric constant of silicon, and e is the charge of electrons, which is a constant.

サイリスタの場合、印加電圧Vは数ボルト程度であり、
通常の構造ではnベース領域の不純物濃度Ndは一定で
あるから、(1)式より空乏層の幅dも一定となり、光
電変換効率は定まつてしまう。ホトサイリスタの光点弧
感度は光電変換効率たけでなく各層の接合寸法、不純物
濃度、なかでも特にnエミッタ領域直下のpベース領域
の抵抗によつて大きく左右されるから、これらを適当に
選ぶことにより点弧感度を向上させることができるが、
他の特性、例えばDV/Dt耐量、阻止耐圧等との兼ね
合いから制限されるのが普通である。したがつて、他の
電気的諸特性を損なうことなく光点弧感度を上げるには
、nベース領域の不純物濃度を低めることが必要である
。本発明の目的は、他の電気的諸特性を損なうことなく
光点弧感度の高い新規なプレーナ形ホトサイリスタを提
供することにある。かかる目的を達成する本発明プレー
ナ形ホトサイリスタの特徴とするところは、光感度の良
いnベース層の受光面側の表面付近にこのnベース層よ
り高比抵抗(低不純物濃度)のn形層(νベース層と呼
ぶ)を設ける点にある。
In the case of a thyristor, the applied voltage V is about several volts,
In a normal structure, since the impurity concentration Nd of the n-base region is constant, the width d of the depletion layer is also constant from equation (1), and the photoelectric conversion efficiency is fixed. The optical ignition sensitivity of a photothyristor is greatly influenced not only by the photoelectric conversion efficiency but also by the junction dimensions of each layer, impurity concentration, and especially the resistance of the p base region directly below the n emitter region, so these should be selected appropriately. The ignition sensitivity can be improved by
Usually, it is limited due to the balance with other characteristics, such as DV/Dt withstand capacity and blocking withstand voltage. Therefore, in order to increase the optical ignition sensitivity without impairing other electrical properties, it is necessary to lower the impurity concentration in the n-base region. SUMMARY OF THE INVENTION An object of the present invention is to provide a novel planar photothyristor with high light ignition sensitivity without impairing other electrical characteristics. The planar photothyristor of the present invention that achieves the above object is characterized by an n-type layer having a higher resistivity (lower impurity concentration) than the n-base layer near the light-receiving surface side of the n-base layer with good photosensitivity. (referred to as the ν base layer).

νベース層はpベース層と隣接するようにし、かつ受光
面と反対側の面においてnベース層と隣接するように配
置される。これによつて光感度の高い表面付近の空乏層
が高比抵抗v層て広がり、光電変換効率を上げることが
でき、光点弧感度を上げることができる。以下本発明プ
レーナ形ホトサイリスタを実施例として示した図面によ
つて具体的に説明する。第1図は本発明プレーナ形ホト
サイリスタの第1の実施例である。nベース層2(NB
)の光照射面付近はνベース層3(VB)から成つてい
る。これを実現するためには、半導体基体1として高濃
度のn層(nベース層)の上に低濃度のν層(νベース
層)を形成したシリコンウェハを用いればよい。このウ
ェハに長時間のp形不純物拡散(例えばボロン拡散)で
p+領域4を作り、ついでpエミッタ層5(PE)とp
ベース層6″(PB)を同じp形不純物拡散により形成
する。つぎにn形不純物拡散(りん拡散)でnエミッタ
層7(NE)を形成したのち、アノード電極8、カソー
ド電極9をを設けてサイリスタが完成する。Jl,J2
,J3はPE,.nB層、PBliの各層間に形成され
たPn接合である。上述の工程で作られた本実施例のサ
イリスタの各部寸法および不純物濃度は次の通りである
。サイリスタペレットは主表面が一辺が1.5mの正方
形、厚さは180pTrt,である。nエミッタ層は厚
さが20μm1表面での不純物濃度が約5〜10!Da
tOmslc!1,.pベース層はnエミッタ層直下で
の厚さが20μm1不純物濃度が約1×1017at0
ms′D..nベース層はpベース層直下での厚さが1
00μm1不純物濃度が2.5×1014at0msI
d..pエミッタ層は厚さが40μm1不純物濃度が約
1×1017at0msIc!lである。なお、nエミ
ッタ層の半導体基体表面露出部の形状は350μm×8
00μmの長方形である。また、νベース層の厚さは約
30μm1不純物濃度は5×1013at0msIc!
lである。光感度がもつとも良いところはJ2接合近辺
の空乏層10が広がつているところである。即ちpベー
ス層はライフタイム短いため光照射で発生した少数キャ
リアの電子は長い距離を拡散できず有効な光トリガ電流
にならないが、nベース層中に発生した正孔はライフタ
イムが長いから有効な光トリガ電流として使われる。こ
のことからできるだけnベース層側に空乏層を広げてや
ればよい。したがつてnベース層表面をさらに高比抵抗
であるvベース層にすることで、空乏層をn側に広げる
ことができ光感度が向上するものである。しかしnベー
ス層をすべてνベース層に置き換えると、主電流通路(
nエミッタ層を積層方向に投影した部分のνベース層)
のνベース層ではオン抵抗が高くなりオン電圧が高くな
るという欠点がある。しかもこのνベース層0りL接合
までは光が到達しないから(光の大部分はnエミッタ層
に吸収されてしまうため)そこでの空乏層を広げても光
感度は良くならない。したがつて第1図に示した実施例
のようにνベース層の厚さはb接合の深さよりも小さく
することが得策である。例えばnベース層の不純物濃度
を2.5×1014at0msIcI1の場合(1)式
よりV=10Vとすると、空乏層は約7μ広がるがnベ
ース層の上に5×1013at0ms1c!l程度のν
ベース層を設けると約16μまで広がる。本実施例の効
果を数値を用いて具体的に説明する。
The ν base layer is arranged adjacent to the p base layer and adjacent to the n base layer on the surface opposite to the light receiving surface. As a result, the depletion layer near the surface, which has high photosensitivity, expands into a high resistivity v layer, thereby increasing the photoelectric conversion efficiency and increasing the light ignition sensitivity. DESCRIPTION OF THE PREFERRED EMBODIMENTS The planar photothyristor of the present invention will be specifically explained below with reference to drawings showing embodiments thereof. FIG. 1 shows a first embodiment of the planar photothyristor of the present invention. n base layer 2 (NB
) consists of a ν base layer 3 (VB) near the light irradiation surface. In order to realize this, a silicon wafer in which a low concentration ν layer (ν base layer) is formed on a high concentration n layer (n base layer) may be used as the semiconductor substrate 1. A p+ region 4 is formed on this wafer by long-term p-type impurity diffusion (for example, boron diffusion), and then a p emitter layer 5 (PE) and a p
A base layer 6'' (PB) is formed by the same p-type impurity diffusion.Next, an n-emitter layer 7 (NE) is formed by n-type impurity diffusion (phosphorous diffusion), and then an anode electrode 8 and a cathode electrode 9 are provided. The thyristor is completed.Jl, J2
, J3 is PE, . This is a Pn junction formed between the nB layer and the PBli layers. The dimensions and impurity concentration of each part of the thyristor of this example manufactured by the above-mentioned process are as follows. The thyristor pellet has a square main surface with a side of 1.5 m and a thickness of 180 pTrt. The n emitter layer has a thickness of 20 μm and an impurity concentration of about 5 to 10 per surface! Da
tOmslc! 1,. The p base layer has a thickness of 20 μm just below the n emitter layer.1 The impurity concentration is approximately 1×1017at0.
ms'D. .. The thickness of the n-base layer directly below the p-base layer is 1
00μm1 impurity concentration is 2.5×1014at0msI
d. .. The p emitter layer has a thickness of 40 μm1 and an impurity concentration of approximately 1×1017at0msIc! It is l. Note that the shape of the exposed portion of the semiconductor substrate surface of the n emitter layer is 350 μm x 8
It is a rectangle of 00 μm. Also, the thickness of the ν base layer is approximately 30 μm1, and the impurity concentration is 5×1013at0msIc!
It is l. The advantage of photosensitivity is that the depletion layer 10 near the J2 junction is widened. In other words, since the lifetime of the p-base layer is short, the minority carrier electrons generated by light irradiation cannot diffuse long distances and do not become an effective photo-trigger current, but the holes generated in the n-base layer have a long lifetime and are therefore effective. It is used as a photo-triggered current. From this, the depletion layer should be expanded as far as possible to the n-base layer side. Therefore, by forming the surface of the n-base layer into a v-base layer having a higher specific resistance, the depletion layer can be expanded to the n-side, and the photosensitivity can be improved. However, if all n base layers are replaced with ν base layers, the main current path (
ν base layer of the part projected in the stacking direction of the n emitter layer)
The disadvantage of the ν base layer is that the on-resistance and on-voltage become high. Moreover, since light does not reach this ν base layer 0-L junction (most of the light is absorbed by the n emitter layer), even if the depletion layer there is widened, the photosensitivity will not improve. Therefore, as in the embodiment shown in FIG. 1, it is advisable to make the thickness of the ν base layer smaller than the depth of the b junction. For example, if the impurity concentration of the n-base layer is 2.5×1014at0msIcI1 and V=10V from equation (1), the depletion layer will expand by about 7μ, but it will be 5×1013at0ms1c! above the n-base layer. ν of about l
When the base layer is provided, it expands to about 16μ. The effects of this embodiment will be specifically explained using numerical values.

本実施例のサイリスタの受光部に通常のGaAs上ED
の発光面を対向させ、第1図に矢印で示すように光を入
射させた。その結果、本実施例のサイリスタはGaAs
上EDに3771,Aの入力電流を流したときに点弧し
た。これに対し、本実施例のサイリスタのνベース層の
不純物濃度をnベース層をそれと同じにし、その他は本
実施例のサイリスタと同じ構成を有するサイリスタ(従
来例)を用意し、上述と同じGaAs上EDを用い上述
と同じ方法で点弧させた。その結果、従来例のサイリス
タはGaAs・1EDに5TrLAの入力電流を流した
ときに点弧した。以上の比較実験から明らかなように、
本実施例のサイリスタは従来例のサイリスタと比べて点
弧感度が約1.7倍に向上した。
In the light receiving part of the thyristor of this example, an ordinary GaAs-based ED is used.
The light-emitting surfaces of the two were opposed to each other, and light was incident as shown by the arrow in FIG. As a result, the thyristor of this example is made of GaAs.
It ignited when an input current of 3771,A was applied to the upper ED. In contrast, a thyristor (conventional example) was prepared in which the impurity concentration of the ν base layer of the thyristor of this example was made the same as that of the n base layer, and the other configuration was the same as that of the thyristor of this example. The upper ED was ignited in the same manner as described above. As a result, the conventional thyristor fired when an input current of 5 TrLA was applied to the GaAs 1ED. As is clear from the above comparative experiments,
The ignition sensitivity of the thyristor of this example was improved by about 1.7 times compared to the thyristor of the conventional example.

第2図は本発明の第2の実施例で第1の実施例に比較し
て耐圧の高い装置を提供するものである。
FIG. 2 shows a second embodiment of the present invention, which provides a device with higher voltage resistance than the first embodiment.

νベース層は不純物濃度が低いからp形に反転しやすい
。表面安定化膜としてのSiO2層11直下のνベース
層がp形に反転するとpベース層とp+領域がつながり
漏洩電流が増え、耐圧が低下する恐れがある。そこで第
1図に示したようにνベース層をL接合近辺にだけ選択
エピタキシャル成長させ、J1接合とは接触しないよう
にする。あるいはJ1接合に接する部分は後で選択的に
n+拡散をしてもその効果は変らない。第3,4図は本
発明の第3の実施例であり、第1の実施例の比較して光
感度をさらに向上させる構造をもつた装置である。
Since the ν base layer has a low impurity concentration, it is easily inverted to p-type. If the ν base layer directly under the SiO2 layer 11 serving as a surface stabilizing film is inverted to p-type, the p base layer and the p+ region will be connected, increasing leakage current and possibly lowering the withstand voltage. Therefore, as shown in FIG. 1, the ν base layer is selectively epitaxially grown only in the vicinity of the L junction, so as not to contact the J1 junction. Alternatively, even if the portion in contact with the J1 junction is selectively n+ diffused later, the effect remains the same. 3 and 4 show a third embodiment of the present invention, which is an apparatus having a structure that further improves photosensitivity compared to the first embodiment.

b接合をpベース層中の一部を突き抜けて表面に出る構
造をしている。この場合も表面近くのnベース層の一部
はνベース層にしておく。このようにすると図示したよ
うに光照射領域一面に空乏層が広がり光感度が良くなる
It has a structure in which the b-junction penetrates through a part of the p-base layer and emerges from the surface. Also in this case, a part of the n base layer near the surface is made into a ν base layer. In this way, as shown in the figure, the depletion layer spreads over the entire light irradiation area and the photosensitivity improves.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明プレーナ形ホトサイリスタの第1の実施
例を示す断面図、第2図は本発明の第2の実施例を示す
断面図、第3図は本発明の第3の実施例を示す平面図、
第4図は第3図のI−1線に沿う断面図である。 符号の説明、1・・・・・・半導体基体、2・・・・・
・nベース層、3・・・・・・νベース層、5・・・・
・・pエミッタ層、6・・・・・・pベース層、7・・
・・・・nエミッタ層、8・・・アノード電極、9・・
・・・・カソード電極。
FIG. 1 is a sectional view showing a first embodiment of the planar photothyristor of the invention, FIG. 2 is a sectional view showing a second embodiment of the invention, and FIG. 3 is a sectional view of a third embodiment of the invention. A plan view showing
FIG. 4 is a sectional view taken along line I-1 in FIG. 3. Explanation of symbols, 1...Semiconductor substrate, 2...
・n base layer, 3...v base layer, 5...
...p emitter layer, 6...p base layer, 7...
...n emitter layer, 8... anode electrode, 9...
...Cathode electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 互いに反対側に位置する一対の主表面と、大部分が
一方の主表面に隣接し一部が他方の主表面側に延びて他
方の主表面に隣接する一方導電極の第1の領域と、他方
の主表面から第1の領域内に延びて形成され、第1の領
域との間に他方の主表面に終端する第1のpn接合を形
成する第1の領域より低不純物濃度を有する他方導電型
の第2の領域と、他方の主表面から第2の領域内に延び
て形成され、第2の領域との間に他方の主表面に終端す
る第2のpn接合を形成する第2の領域より高不純物濃
度を有する一方導電型の第3の領域と、他方の主表面か
ら第2の領域内に延び一部が第3の領域に隣接して形成
された第2の領域より低不純物濃度を有する他方導電型
の第4の領域と、他方の主表面から第3の領域内に延び
て形成され、第3の領域との間に他方の主表面に終端す
る第3のpn接合を形成する第3の領域より高不純物濃
度を有する他方導電型の第5の領域と、から成る半導体
基体、半導体基体の一方の主表面において第1の領域に
接触する第1の主電極、半導体基体の他方の主表面にお
いて第5の領域に接触する第2の主電極、するようにし
たことを特徴とするプレーナ形ホトサイリスタ。
1 A pair of main surfaces located on opposite sides of each other, and a first region of one conductive electrode that is mostly adjacent to one main surface and partially extends to the other main surface side and is adjacent to the other main surface. , extending from the other main surface into the first region and having a lower impurity concentration than the first region forming a first pn junction between the first region and the first region terminating at the other main surface. a second region of the other conductivity type; and a second pn junction formed extending from the other main surface into the second region and terminating at the other main surface between the second region and the second region. a third region of one conductivity type having a higher impurity concentration than the second region; and a second region extending from the other main surface into the second region and partially adjacent to the third region. a fourth region of the other conductivity type having a low impurity concentration; and a third pn formed extending from the other main surface into the third region and terminating at the other main surface between the third region and the third region. a fifth region of the other conductivity type having a higher impurity concentration than the third region forming the junction; a first main electrode in contact with the first region on one main surface of the semiconductor substrate; A planar photothyristor characterized in that the second main electrode contacts the fifth region on the other main surface of the semiconductor substrate.
JP50017853A 1975-02-14 1975-02-14 Planar photothyristor Expired JPS6058594B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50017853A JPS6058594B2 (en) 1975-02-14 1975-02-14 Planar photothyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50017853A JPS6058594B2 (en) 1975-02-14 1975-02-14 Planar photothyristor

Publications (2)

Publication Number Publication Date
JPS5193679A JPS5193679A (en) 1976-08-17
JPS6058594B2 true JPS6058594B2 (en) 1985-12-20

Family

ID=11955209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50017853A Expired JPS6058594B2 (en) 1975-02-14 1975-02-14 Planar photothyristor

Country Status (1)

Country Link
JP (1) JPS6058594B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5347287A (en) * 1976-10-13 1978-04-27 Oki Electric Ind Co Ltd Independent gate structure photo switch
JPH0666462B2 (en) * 1987-12-21 1994-08-24 日本電気株式会社 Semiconductor protection element

Also Published As

Publication number Publication date
JPS5193679A (en) 1976-08-17

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