JPS6057779B2 - output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an output in a digital control circuit that is configured with MISEETs (insulated gate field effect transistors) and shares a terminal for an input signal and an output signal that do not compete in time. Regarding buffer circuits.

In order to reduce the number of terminals in a digital control circuit, one idea is to share terminals for transmitting and receiving input signals and output signals that do not conflict in time.

In this case, as shown in FIG. 2, the output buffer circuit 1 is a push-pull output circuit Q that is in a high output impedance state at non-output timing.

,Q, may be used. Transistor Q. ,
Q, is connected between the first power supply voltage terminal Vcc and the second power supply voltage terminal (reference potential point of the circuit). Note that in the circuit shown in the figure, the MISFET is of an n-channel type, and the logic is positive logic. This output buffer circuit 1 is provided with NOR gate circuits NR3 and NR4 on the input side, and when the output timing pulse φc is at the ``1'' level is the non-output timing, and at this time, the push-pull MISFET
The input buffer circuit 2 is operated by turning off Q, , Q unconditionally, making the input/output terminal P high impedance, and setting this terminal to a level defined only by the output level of the output circuit 4 of the other digital circuit. It is something. Note that the output circuit 4 is constituted by a drive transistor Q, 2 to which an input signal is applied to its base and whose emitter is coupled to a reference potential of the circuit, and a load transistor R3.

As a result, an inverted signal of the input signal is supplied to the terminal P. However, at the timing of the output of the output buffer circuit 1, the drive transistors Q and 2 are put into the OR state so as not to compete with the output signal thereof. In this output buffer circuit 1, ′Π゛L(TransistorTr
In the case of driving the input buffer circuit of another digital control circuit configured with ansistorLogic, the following procedure is performed.

That is, when the emitters of the input transistors Q and O of the circuit 3 are brought to a low level, the base and emitter regions of the input transistors Q and O of the circuit 3 are biased in the forward direction. Therefore, the input transistor Ql. The base and emitter of the power supply voltage■. A current flows from the resistor R3 through the resistor R3. In this case, since no current is supplied to the base side of the output transistor Qll,
Transistor Qll is turned off. Next is the input transistor Ql. When the emitter of QlO is brought to a high level, the base-collector of the input transistor QlO is forward biased. Therefore, a current is supplied to the base of the output transistor Qll, and the output transistor Qll is turned on. As is clear from the above operation, in order for the output buffer circuit 1 to supply a low level signal to the terminal P1, MISFET Q5 must be turned on, and in addition to the TTL input current (for example, 1.6 mA or less), the external digital circuit Since it is necessary to flow current from the load resistor R3 of No. 4 to ensure a low level, it is necessary to increase the size of MISFET Q5 to allow a large current to flow. Therefore,
As shown in FIG. 3, the output timing pulse φC turns on the MISFET Q4 on the power supply side even at the non-output timing of the 66r1 level, so that it can also be used as a load for the external digital circuit 4. Conceivable.

As a result, the current flowing through MISFETQ5 when the output buffer circuit 1 outputs the ``0'' level can be reduced to only the TTL side input current (1.6mA).However, this MISFETQ is Since it is used as a load at the time of input, it is not possible to flow more than the current (for example, 167TLA) at this time.In other words, the output transistor Ql on the external TI'L side
The collector current of No. 2 is defined by its base input current, and if more current flows, it will not be possible to secure the ゜゜0゛ level of the input buffer circuit 2 on the MIS logic circuit side. . Therefore, even when the output buffer circuit 1 outputs a high level, the MISF
Since a current exceeding the collector current rating of Ql2 cannot flow through ETQ4, the delay time when outputting the ゜゜1゛ level increases.

This invention provides an output buffer circuit configured with MISFETs that exchanges signals with a logic circuit whose input/output current is regulated, such as a TTL logic circuit, and also shares input/output terminals. The size of the output MISFET can be determined without being constrained by
This invention was made in order to provide an output buffer circuit that can increase the speed of output signals.

In one embodiment of the present invention, a push-pull output circuit that has high impedance at non-output timing;
An output buffer circuit is constituted by the MISFET which supplies the output current of the other party and supplies the current when the power supply side level is output at the output timing.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, 1 is an output buffer circuit.

This circuit consists of a push-pull output circuit composed of MISFETQl and Q2, a NOR gate circuit NRl and NR2 controlled by an output timing signal φc, and a MISFETQ provided between a power supply voltage terminal P2 and an output terminal P1.
The signal D to be output is applied to the gate of the ground side MISFETQ2 of the push-pull output circuit via the NOR gate circuit NRl, and the output of this NOR circuit NRl is applied to the gate of the ground side MISFETQ2 of the push-pull output circuit. Power supply side MI of the push-pull output circuit via circuit NR2
Applied to the gate of SFETQl, inverter circuit FsJ
The voltage is applied to the gate of the SFET Q3 through 1. The NOR gate circuits NRl and NR2 output the output timing signal φCf)6 at the non-output timing.
Due to the 6r゛ level, the above ■SFETQl,Q
2 is off. Furthermore, regarding the output timing, the output timing signal φc is set to the ゜“0゛ level, and RvISFETQl and Q2 are controlled in a complementary manner according to the information D to be output.In other words, the information D to be output is “゛0゛” When this happens, MISFET Q2 turns on and outputs a 660° level, and when the signal D to be output is at a 1° level, the MISFET Q2 turns on and outputs a 660° level.
FETQ2 turns on and outputs 66r3 level. Also, the output of the NOR gate circuit NRl is connected to the inverter circuit 1.
The MISFET 9, which is applied to its gate via N1, turns on at the non-output timing when the output timing signal φc is at the "°1" level, and supplies the output current of the output circuit of the other party.

Then, at the output timing when the output timing signal φc is at the 660'5 level, the output of the NOR gate circuit NRl changes according to the information D to be output, so the MIS
Like FETQl, it is turned on when outputting the 66r3 level, which is the power supply side level, to help supply the '6r5 level output current.

In this embodiment, 2 is an input buffer circuit on the S logic circuit side, which is composed of an inverter circuit IN2 and the like.

Further, 3 is an input buffer circuit of the other party, which is a TTL 8 circuit composed of bipolar transistors QlO, Qll and resistors Rl, R2.

4 is the output buffer circuit of this other party,
It is composed of an open collector transistor Ql2.
In this example circuit, at non-output timing,
As mentioned above, in the output buffer circuit 1, the MISFET
Only Q3 is on.

Therefore, this MISFET Q3 is designed to satisfy the collector current standard (for example, maximum 167T1, A) of the output transistor QS2 of the other party. Also, at the time of output timing, when the C6O'' level is output, only the MISFET Q2 of the output buffer circuit 1 is turned on, so the size of the other input transistor Ql can be changed without increasing the size compared to the case of FIG.
It is set so that an input current of 0 (for example, 1.6Tr1.A or more) flows. On the other hand, when the C'R5 level is output, both SFETQl and Q3 of the output buffer circuit 1 are turned on, so MISFETQl is
Considering the output current of FETQ3, high level (゜゜1
It is set to flow the current necessary for increasing the speed of output in (2). The output buffer circuit 1 shown in this embodiment has the minimum SFET size without being constrained by the MISFET size and output delay time according to the rating in a circuit such as a TrL circuit where the input/output current is regulated. It is possible to achieve faster speeds.

The present invention is not limited to the above embodiments, and the gate circuit is
In addition to NOR gate circuits, other logic circuits such as NAND circuits can also be used.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams each showing an example of a possible output buffer circuit. 1... Output buffer circuit, 2... Input buffer circuit, 3... Opposite input buffer circuit, 4... Opposite output buffer circuit.

Claims (1)

[Claims] 1 a push-pull output circuit coupled between a first power supply voltage terminal and a second power supply voltage terminal; a gate circuit controlled by an output timing signal and outputting an input signal of the push-pull output circuit; A MISF provided between the first power supply voltage terminal and the output terminal of the push-pull output circuit and rendered conductive at least when the push-pull output circuit is in a high output impedance state.
ET, a terminal to which the output signal of the push-pull output circuit and an input signal that does not compete with these in time are commonly applied, and whether or not the current supplied from the MISFET is sent to the second power supply voltage side. and a terminal to which a circuit for forming the input signal is connected.