JPS6278915A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To select a mode of an input/output circuit freely according to the purpose of use by providing a control circuit which controls the gate of a pull-up or pull-down TR and controlling a voltage impressed from the control circuit to the gate. CONSTITUTION:When the value of a pull-up selection register 8 is 'H' in an N channel open drain input/output circuit which allows pull-up selection, a pull-up TR 7 which is a P-MOSTR is off, so this circuit is equivalent to a circuit to which the pull-up TR 7 is not added. When the value of the pull-up selection register 8 is 'L', the pull-up TR 7 is on and the drain 9 of an output TR 1 is pulled up to VCC. Thus, whether the N channel open drain output is pulled up or not is selected freely according to the value of the pull-up selection register 8. The operation of a P channel open drain input/output circuit which allows pull-down selection is basically the same.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor Tokio circuit device vtK having a pull-up transistor or a pull-down transistor.

[Conventional technology]

The configuration of a semiconductor integrated circuit device having a conventional pull-up transistor or pull-up/transistor is shown in FIG.
), (b).

Figure 3(a) is a block diagram of an N-channel open-drain input/output circuit with a pull-up transistor.
2 is an input/output terminal; 3 is an output transistor composed of a performance-type N-channel MOS transistor;
is a pull seven-tube transistor composed of depletion type N-channel MOS transistors.

, it! Figure 3(b) is a configuration diagram of a P-channel oven drain input/output circuit with a pull-down transistor.

Reference numeral 4 designates an output transistor constituted by an enhancement type P-channel MO8 transistor, 5 an input/output cursor, and 6 a pull-down transistor constituted by a depression type N-thousand MOS transistor.

As described above, the pull-up transistor 3 and the pull-down transistor 6 are generally configured by debrenosion type N-channel MO8 transistors.

The pull-up transistor 3 and the pull-down transistor 6, which are depletion type transistors, are formed by forcibly forming a channel between the source and drain of the transistor by ion implantation during the manufacturing process of the semi-integrated circuit device. The resulting source-drain resistance is used as a pull-up and pull-down resistance.

[Problem that the invention seeks to solve]

The pull-up and pull-down transistors in the conventional semi-dedicated circuit device as described above are composed of depletion type transistors, so whether or not to use a pull-up or pull-down can only be selected during the manufacturing process. There were problems such as the need for two masks for the depression process during the process.

This invention was made in order to solve this problem, and the depression mask during the manufacturing process can be of the LW type, and the presence or absence of pull-up and pull-down can be freely selected depending on the intended use. The purpose is to obtain a semiconductor integrated circuit device.

[Means for solving problems]

The half-body integrated circuit device according to the present invention includes at least one of a pull-up transistor and a pull-down transistor constituted by an enhancement type MOS transistor whose drain is connected to a terminal to which at least one of input or output is connected. and a control circuit for controlling the gates of one or both of the pull-up and pull-down transistors.

[Effect]

In this invention, pull-up or pull-down is selected by controlling the voltage applied to the gate of the pull-up transistor or pull-down transistor by the control circuit.

[Actual example]

FIG. 1(a) is a configuration diagram of an N-channel oven-drain input/output circuit that allows selection of pull-up transistors, which is an embodiment of the semiconductor integrated circuit device of the present invention, and is the same as FIG. 3(a). Symbols indicate the same parts, 7 is a pull-up transistor formed by an enhancement type P-channel MOS transistor, 7a is the gate of the previous pull-up transistor 1, 8 is a pull-up selection register which is a control circuit, 9 is the drain of the output transistor 1.

Figure m1 (b) is an actual example of the semi-quadruple circuit device of this invention, and the selection of the pull-down transistor is the main point in J1 city P.
This is the configuration diagram of the channel open drain input/output circuit.
The same reference numerals as in FIG.
11 is a pull-town selection register, and 12 is a drain of a transistor 40 for output.

I will explain about the next Km work.

First, in Figure 1(a), which is an N-channel oven-drain input/output circuit with a pull-up selection port S, the pull-up transistor 1 is controlled by the voltage node 7a of the pull-up selection register 8. . That is, if the value of the pull-up selection register 8 is 1H1, the pull-up transistor 7, which is a P-channel MO8 transistor, is turned off, and the circuit becomes equivalent to a circuit to which the pull-up transistor 1 is not added. The value of pull-up selection register 8 is @L
'', the pull 7 tube transistor 7 is turned on and the drain 9 of the output transistor 1 is pulled up to VCC.In this way, depending on the value of the pull 7 pump selection register 8, the N channel open drain Output can be freely selected with or without pull-up.

Since the pull-down selection I-IJ transistor transistor 10 shown in FIG.
0 is on! Therefore, the input 12 of the output transistor 4 is pulled down to VSS. Also, when the pull-down selection register 11 is "L", the pull-down transistor 10 is turned off, and the output transistor 4 becomes an open drain without pull-down. In this way, regardless of pull-up or pull-down, pull-up or The input/output format can be freely selected by selecting one of the pull-down selection registers 8 and 11.

FIG. 2 shows another embodiment of the semiconductor integrated circuit device of the present invention, in which input pull-up and pull-down can be freely selected.
% 13 in j7-configuration diagram of CMO8 input/output circuit
．． 14 is an enhancement type P-channel MOS transistor and an N-channel MOS transistor for configuring CMO8 output transistors, 15 is a pull-up transistor constituted by an enhancement type P-channel MOS transistor, and 16 is an enhancement type N-channel MO8 transistor. A pull-down transistor composed of, 1T is an input/output terminal,
18.19 is NAND gate, 20.2+ is N Oit
Gate, 22 is direction register, 23 is pull-up/pull-down selection register, 24 is output register, 30 is play
V times f6.

Next, the operation will be explained.

First, if the value of the direction register 22 is H'', this input/output circuit is set to output mode.In this case, the output register 2
1st shift of 4 is NAND gate 19. NOB gate 21 connects P-channel MO8 transistor 13. N channel MO
When one of the S transistors 14 is turned on, an output is output to the input/output terminal 17, and the pull-up transistor 15. Pull-down transistor 16 is NAN
D gate 19. Both are cleared by the NO gate 21 and no pull-up or pull-down operation is performed.

On the other hand, when the 1st shift of the direction register 22 is "L", the input/output circuit becomes the input mode, and the P channel MO No. 8 valve tiger /;/meta 13
．． N channel A40S) Since both of the runnostars 14 are turned off, the 1st shift of the output register 24 is not output. However, if the value of the pull amplifier/pull-down selection register 23 is F', the NAND gate 19
If the pull-up transistor 15 is turned on and the pull-up mode is set, and the value of the pull-up/pull-down selection register 23 is L'', the pull-down transistor 16 is turned on by the No gate 21 and the pull-down mode is set. Therefore, when the input mode is set by the direction register 22, the pull-up or pull-town of input AJ can be freely selected directly by the pull-up/pull-town selection register 2301.

〔Effect of the invention〕

As explained above, the present invention includes at least one of a pull-up transistor or a pull-down transistor constituted by an enhancement type MOS transistor having a drain connected to a terminal to which at least one of input or output is connected; Since a 15-11 # enclosure is provided to control the gate of one or both of the knob transistor or pull-down transistor,
By controlling the voltage applied to the gate from the surface control circuit, the selection of pull-up and pull-down is possible, and pull-up, pull-down, am
This eliminates the inconvenience of having to select the output circuit, and allows one person to freely select the mode of the output circuit according to the intended use.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram of an N-channel open-drain input/output circuit in which the selection of pull-up transistors is selective, which is an embodiment of the semiconductor integrated circuit device of the present invention, and FIG.
) is an actual IM example of the semiconductor integrated circuit device of the present invention, and is a block diagram of the P-channel oven drain output circuit 6 in which the selection of the pull-down transistor is OJ HF. CM that is the real nine series of
The configuration diagram of the O8 output circuit, Figure 3 (a) is the conventional Bull 7
FIG. 3(b) is a block diagram of a conventional P-channel open-drain input/output circuit with a pull-down transistor. In the figure, 1.4 is an output transistor, 2.5 is an input/output terminal, 7 is a pull-amp transistor, 8 is a pull-up selection register, 10 is a pull-down transistor, 1
1 is a pull-down selection register. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Ruo Oiwa (2 others) Diagram 1] O Puno Night Down Transistor

Claims (1)

[Claims] Consisting of the required number of output transistors, each consisting of an enhancement-type MOS transistor whose drain is connected to a terminal to which at least one of the input or output is connected, and an enhancement-type MOS transistor whose drain is connected to the terminal. 1. A semiconductor integrated circuit device comprising at least one of a pull-up transistor and a pull-down transistor, and a control circuit that controls a gate of at least one of the pull-up transistor and the pull-down transistor.