JPS6057720A - Snubber circuit device of electrostatic induction thyristor - Google Patents

Snubber circuit device of electrostatic induction thyristor

Info

Publication number
JPS6057720A
JPS6057720A JP16464783A JP16464783A JPS6057720A JP S6057720 A JPS6057720 A JP S6057720A JP 16464783 A JP16464783 A JP 16464783A JP 16464783 A JP16464783 A JP 16464783A JP S6057720 A JPS6057720 A JP S6057720A
Authority
JP
Japan
Prior art keywords
snubber
thyristor
capacitor
electrostatic induction
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16464783A
Other languages
Japanese (ja)
Other versions
JPH035691B2 (en
Inventor
Yutaka Kawamura
豊 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Denki Seizo KK
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Denki Seizo KK
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Denki Seizo KK, Toyo Electric Manufacturing Ltd filed Critical Toyo Denki Seizo KK
Priority to JP16464783A priority Critical patent/JPS6057720A/en
Publication of JPS6057720A publication Critical patent/JPS6057720A/en
Publication of JPH035691B2 publication Critical patent/JPH035691B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08144Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in thyristor switches

Landscapes

  • Thyristor Switches And Gates (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To decrease the power loss of a snubber resistor by connecting one end of an impedance element to a connecting point of a series connection between a diode and a capacitor and connecting the other end of the impedance element to a DC power supply. CONSTITUTION:The series connection comprising the snubber diode 5' and the snubber capacitor 6' is connected in parallel with an electrostatic thyristor 8. One end of the snubber resistor 7' being the impedance element is connected to the connecting point between the snubber diode 5' and the snubber capacitor 6' and the other end of the snubber resistor 7' is connected to the DC power supply E. Through the constitution above, even if the capacitor capacitance is selected largely in order to lower the overcharge voltage of the snubber capacitor 6' when the electrostatic thyristor 8 is turned off, no hindrance is given to the power loss at turn-off.

Description

【発明の詳細な説明】 本発明は靜1!誘導サイリスタを用いてなる直流スイッ
チ回路に係り、特に静電誘導サイリスタに適合して効用
できる格別なスナバ回路装置の改良に関する◇ 静電誘導サイリスタ(以下8Iサイリスクと称する)は
ゲートターンオフサイリスタ(GTOサイリスタ)と同
じ自己消弧機能を有する自己消弧形サイリスタの一糎で
あるが、GTOサイリスタと比べて種々の利点を備える
ものとして注目されているところである◎すなわち、 (1) スイッチングの速度が速い。
[Detailed Description of the Invention] The present invention is silent! This article relates to a DC switch circuit using an induction thyristor, and in particular to the improvement of a special snubber circuit device that is suitable and effective for electrostatic induction thyristors. ) is one type of self-extinguishing thyristor that has the same self-extinguishing function as the GTO thyristor, but it is attracting attention as having various advantages compared to the GTO thyristor ◎ Namely, (1) Fast switching speed .

(2) ターンオフ時に熱破壊し難い。(2) Hard to cause thermal damage during turn-off.

(3) ターンオフ直後の順電圧上昇率(dV/dt 
)の耐量が大きい。
(3) Forward voltage rise rate immediately after turn-off (dV/dt
) has a large tolerance.

一方1代表的なスナバ回路装置として第1図ζこ示すも
のが知られている。
On the other hand, one typical snubber circuit device shown in FIG. 1 is known.

第1図は公知のスナバ回路装置を具備してなるGTOサ
イリスタ採用の直流スイッチ回路例の要部構成を示すも
ので、lは直流電源、2はGTOサイリスタ、3は負荷
、4は主回路浮遊インダクタンスである。また、図にお
いて5はスナバダイオード、6はスナバコンデンサ、7
はスナバ抵抗である。
Figure 1 shows the main part configuration of an example of a DC switch circuit using a GTO thyristor and equipped with a known snubber circuit device, where l is a DC power supply, 2 is a GTO thyristor, 3 is a load, and 4 is a main circuit floating It is inductance. In addition, in the figure, 5 is a snubber diode, 6 is a snubber capacitor, and 7 is a snubber diode.
is the snubber resistance.

さらに、第2図と第3図は第1図に示した直流スイッチ
回路でオフ動作する場合とオン動作する場合の各部波形
を示す説明図である0 すなわち、GTOサイリスタ2を使用してスイッチ動作
をさせる際のスナバ回路動作はつぎの如くである。
Furthermore, FIGS. 2 and 3 are explanatory diagrams showing the waveforms of each part when the DC switch circuit shown in FIG. 1 is turned off and turned on. The snubber circuit operates as follows.

まず、 GTOサイリスタ2により負葡電流ILをしゃ
断するときのアノード電流IT(!ニアノード電圧VA
Kの時間的推移を表す第2図においては、いま時点TO
FでGTOサイリスタ2にオフゲートパルスを与えたも
のとするに、蓄積時間Ts経過後下降時間T。
First, the anode current IT (!near-node voltage VA
In Figure 2, which shows the time course of K, the current time TO
Assuming that an off-gate pulse is given to the GTO thyristor 2 at F, the fall time T after the accumulation time Ts has elapsed.

の間にアノード電流I、の大半は減衰して残りの電流が
テイル期間TT後に消滅する0さらには、この期間のG
TOサイリスタ2のアノード電圧TAXの変化は例示の
如くになる◇ そして、かかる動作化おけるスナバコンデンサ6の機能
はつぎの三点にある・その第一点はテイル期間TTにお
ける電力損失を、ターンオフ直後のアノード電圧YAK
を抑制して低減させることであり、第二点はアノード電
圧VXXの上昇率を制限してターンオフ直後のGTOサ
イリスタ2の誤点弧を防ぐことであり、第三点は主回路
のインダクタンス成分に蓄えられたエネルギーを吸収す
ることにより1アノード電圧vAKに生じるスパイク電
圧ΔvOを抑制することである。
During this period, most of the anode current I attenuates and the remaining current disappears after the tail period TT.
Changes in the anode voltage TAX of the TO thyristor 2 are as shown in the example. ◇ The functions of the snubber capacitor 6 in such an operation are as follows. The first point is to reduce the power loss during the tail period TT immediately after turn-off. Anode voltage YAK
The second point is to limit the rate of increase in the anode voltage VXX to prevent false firing of the GTO thyristor 2 immediately after turn-off, and the third point is to suppress and reduce the inductance component of the main circuit. The purpose is to suppress the spike voltage ΔvO occurring in one anode voltage vAK by absorbing the stored energy.

つぎに、 GTOサイリスタ2のターンオン時のアノー
ド電流ITおよびスナバコンデンサ6の電圧vOの変化
は第3図に示した如くになる。
Next, changes in the anode current IT and the voltage vO of the snubber capacitor 6 when the GTO thyristor 2 is turned on are as shown in FIG.

ここにs ITPはアノード電流ITのピーク値を示し
ている。すなわち、時点TOt!でオンゲートする際ス
ナバコンデンサ6に蓄えられた電荷がスナバ抵抗7を通
して放電されるものとなり、そのエネルギーは熱となっ
て消費されるOこのとき、スナバ抵抗7Iこ印加される
電力wRは、スナバコンデンサ6の容量をaS V動作
周波数をFとする署こ、WR= (1/2)・C5(E
s)ζF ・−=−=・−・(1)なる関係式で表わせ
る0よって、スナバ抵抗7の発熱は回路電圧と動作周波
数が上昇するにつれて著しく増大するものとなる0 さて、かような直流スイッチ回路において、いまGTO
サイリスタに代えて8Iサイリスクを採用するものとす
れば、前述した如くターンオフ時化熱破壊し−くくかつ
(dV/d t )耐量が大きいことから、スナバコン
デンサ6の容量を小さくしてスナバ抵抗7の低減できる
筈である。しかしながら、第1図に示した回路構成に$
けるGTOサイリスタ2を単に8Iサイリスタに置換す
ることでは、サイリスタしゃ断時に主回路浮遊インダク
タンス4に蓄えられたエネルギーにより生じるスナバコ
ンデンサの過充電電圧が大きく左右するものとなってし
まうO これは、スパイク電圧ΔVOは主回路浮遊インダクタン
ス4の値をL3とするに、 1vo−工T−τ=局■ ・・・・−・・・・・・(2
)なる関係を示す。ただし、アノード電流ITはしゃ断
時の値である。このため、スナバコンデンサ6の容iC
8を小さくするとスパイク電圧ΔvOが極めて太き(な
り、したがって3Nサイリスタの許容順電圧を超えるも
のとなる不具合を生じるO本発明は上述したような点に
着目しなされたもので、SIサイリスタを採用した直流
スイッチ回路にあって8IサイリスクIこ適合し作用効
果を奏する簡便な構成のスナバ回路装置を提供するもの
である0以下、本発明を図面に基づいて説明するOgJ
4図は本発明の一実施例の要部構成を示すもので、5′
はスナバダイオード、6′はスナバコンデンサ、7′は
インピーダンス素子例のスナバ抵抗、8は8Iサイリス
タである0図中、第1図と同符号のものは同じ構成部分
を示すOかようなものは、8Iサイリスタのスナバ回路
構成部Cζついて第1図と対比すれば、スナバ抵抗7′
がスナバダイオード51、スナバコンデンサ6′からな
る直列接続体の2個間の接続点と直流電源1の正電極と
の間に配されてなる相違点をもつものである。かかる構
成についてその各部の波形の時間推移を第2図および9
J3図に類して表した第5図および第6図を参照してつ
ぎこと詳細説明する。
Here, s ITP indicates the peak value of the anode current IT. That is, time TOt! When turning on the snubber capacitor 6, the charge stored in the snubber capacitor 6 is discharged through the snubber resistor 7, and the energy is consumed as heat.At this time, the power wR applied to the snubber resistor 7I is If the capacity of 6 is aSV and the operating frequency is F, then WR = (1/2)・C5(E
s) ζF ・−=−=・−・0 This can be expressed by the relational expression (1), so the heat generation of the snubber resistor 7 increases significantly as the circuit voltage and operating frequency increase. In the DC switch circuit, now GTO
If an 8I thyristor is used instead of a thyristor, it is difficult to thermally break down during turn-off as described above and has a large (dV/dt) withstand capacity. It should be possible to reduce this. However, the circuit configuration shown in Figure 1 requires $
Simply replacing the GTO thyristor 2 with an 8I thyristor will greatly affect the overcharge voltage of the snubber capacitor caused by the energy stored in the main circuit stray inductance 4 when the thyristor is cut off. ΔVO is 1vo-T-τ=station■, assuming that the value of main circuit stray inductance 4 is L3.
). However, the anode current IT is the value at the time of shutoff. Therefore, the capacitance iC of the snubber capacitor 6
If 8 is made small, the spike voltage ΔvO becomes extremely large (and therefore exceeds the allowable forward voltage of the 3N thyristor, which causes a problem). The present invention will be explained below with reference to the drawings.
Figure 4 shows the main structure of an embodiment of the present invention, and Figure 5'
is a snubber diode, 6' is a snubber capacitor, 7' is a snubber resistor as an example of an impedance element, and 8 is an 8I thyristor. , 8I thyristor snubber circuit component Cζ is compared with FIG. 1, the snubber resistor 7'
is disposed between the positive electrode of the DC power source 1 and the connection point between the two series-connected bodies consisting of the snubber diode 51 and the snubber capacitor 6'. The time course of the waveforms of each part of this configuration is shown in Figures 2 and 9.
The details will be explained below with reference to FIGS. 5 and 6, which are similar to FIG. J3.

ここに、tJ5図は第4図回路におけるオフ動作時のア
ノード電流1丁′およびアノード電圧VAK′の波形を
示し、さらには第6図はオン動作時のアノード電流IT
′およびスナバコンデンサ6′の電圧vO′を示してい
る◇ すなわち、時点TOFで8Iサイリスタ8にオフゲート
パルスを与えると、蓄積時間Ts経過後下降時間TFの
間ζこアノード電流工T′の大半は減衰して残りの電流
がテイル期間TT後に消滅する。したがって、この変化
は第2図に示したアノード電流ITと同様であるが、ア
ノード電圧VAK e VAK’特性の両者は著しく異
なるものとなる。これは、図示の如くスナバコンデンサ
6′が直流電源1に接続されてなるスナバ抵抗7′によ
り、スナバコンデンサ6′は8Iサイリスタ8の導通期
間中に常に直流電源1電圧E。
Here, Figure tJ5 shows the waveforms of the anode current 1' and anode voltage VAK' during the OFF operation in the circuit of Figure 4, and furthermore, Figure 6 shows the waveforms of the anode current IT during the ON operation.
' and the voltage vO' of the snubber capacitor 6' ◇ That is, when an off-gate pulse is applied to the 8I thyristor 8 at time TOF, most of the anode current T' is is attenuated and the remaining current disappears after the tail period TT. Therefore, although this change is similar to the anode current IT shown in FIG. 2, the anode voltage VAK e VAK' characteristics are significantly different. This is due to the snubber resistor 7' in which the snubber capacitor 6' is connected to the DC power supply 1 as shown in the figure, so that the snubber capacitor 6' always maintains the DC power supply 1 voltage E during the conduction period of the 8I thyristor 8.

に充電され、よって、アノード電圧VAK’はフォール
期間終了後直ちに電源電圧値以上を示すことになる。な
お、このときのスパイク電圧Δvo′は前述の主回路の
インダクタンス成分に生じて式(2)で与えられる。さ
らに、SIサイリスタ8が時点TONでターンオンする
と、アノード電流IT′は図示の如くに増加するものと
なって、スナバコンデンサ6′に蓄えられた電荷を放電
する接続を有せずスナバ抵抗7′による電力損失が生じ
ない。
Therefore, the anode voltage VAK' becomes equal to or higher than the power supply voltage value immediately after the fall period ends. Incidentally, the spike voltage Δvo' at this time is generated in the inductance component of the above-mentioned main circuit and is given by equation (2). Furthermore, when the SI thyristor 8 is turned on at time TON, the anode current IT' increases as shown, and the snubber resistor 7' has no connection to discharge the charge stored in the snubber capacitor 6'. No power loss occurs.

かくの如く、本実施例はSIサイリスタ8をその性能を
十分に発揮せしめスナバ回路のインピーダンス素子部分
において電力損失を発生せず、回路電圧、動作周波数と
もに高く選定可能になるものであり、8Iサイリスタ採
用の直流スイッチ回路に最適なスナバ回路装置を実現し
たものである。さらに、この点をよりへ体的に示すと、
SIサイリスタは熱破壊し”4 < < (dV/dt
)耐量が大きいためターンオフ直後のアノード電圧の急
上昇に耐えられ、8Iサイリスタのターンオフ時スナバ
コンデンサの過充電電圧を低くするためにそのコンデン
サ容量を大きく選んでも、ターンオン時の電力損失に何
ら支障をきたさないものとすることができる。
As described above, this embodiment allows the SI thyristor 8 to fully demonstrate its performance, does not generate power loss in the impedance element part of the snubber circuit, and allows selection of a high circuit voltage and operating frequency. This is a snubber circuit device that is ideal for the DC switch circuit used. Furthermore, to illustrate this point more physically,
The SI thyristor is thermally destroyed and "4 << (dV/dt
) Because of its large withstand capacity, it can withstand a sudden increase in anode voltage immediately after turn-off, and even if the capacitance of the snubber capacitor is chosen to be large in order to lower the overcharge voltage of the snubber capacitor when the 8I thyristor turns off, there will be no problem with power loss at turn-on. It can be assumed that there is no such thing.

第7図は本発明の他の実施例の要部構成を示すもので、
5“はスナバダイオード、6“はスナバコンデンサ、7
′はスナバ抵抗、8′は8Iサイリスタである。すなわ
ち、第7図に示したものは、第4図に示した直流スイッ
チ回路例、したがって8Iサイリスタ8を直流電源1の
正極側より負荷3等を介し、接続して直流電源1に通ず
る系統1こ対し、SIサイリスタ8′を負荷3の正電位
側に配した例である。
FIG. 7 shows the main structure of another embodiment of the present invention.
5" is a snubber diode, 6" is a snubber capacitor, 7
' is a snubber resistor, and 8' is an 8I thyristor. That is, what is shown in FIG. 7 is the example of the DC switch circuit shown in FIG. On the other hand, this is an example in which the SI thyristor 8' is placed on the positive potential side of the load 3.

なお、スナバダイオード5′、スナバコンデンサ6′お
よびスナバ抵抗7′よりなるスナバ回路構成も第4図に
示したものと同様であるこを明白である@よって、第7
図に示した装置は第4図装置と同じ畿能を有するもので
ある〇 第8図は第4図装置の一変形例を示すもので、図中第1
図および第4図と同符号のものは同じ構成部分を示して
いる。すなわち、第8図に示したであるoしたがって、
かかる−例もまた第4図装置と同様の効果が得られるこ
とは明らbである。
It is clear that the snubber circuit configuration consisting of the snubber diode 5', the snubber capacitor 6' and the snubber resistor 7' is also the same as that shown in FIG.
The device shown in the figure has the same performance as the device shown in FIG. 4. Figure 8 shows a modified example of the device shown in FIG.
The same reference numerals as those in the figures and FIG. 4 indicate the same components. That is, as shown in FIG. 8, therefore,
It is clear that this example also provides the same effect as the device shown in FIG. 4.

以上説明したように本発明によれば、S■サイリスタ採
用の直流スイッチ回路に有用かつ格別な装εを提供でき
る◇
As explained above, according to the present invention, a useful and special equipment ε can be provided for a DC switch circuit employing an S thyristor◇

【図面の簡単な説明】[Brief explanation of the drawing]

第1図き第21および第3図は公知のスナバ回路装置を
備えたGTOサイリスタ採用の直流スイッチ回路例を示
す回路図とその各部波形の時間推移をそれぞれ表す説明
図%第4図と第5図および第6図は本発明の一実施例を
示す回路図とその各部波形の時間推移をそれぞれ表す説
明図、第7図は本発明の他の実施例を示す回路図、第8
図は第4図装置の一変形例を示す回路図である。 3・・・・−・負荷、4・・−・主回路浮遊インダクタ
ンス、スナ1< 5.5’、5“・・・・b71オード、6,6’、6“
・・・・スナバコンデンサ、?、7’、7’・・・・・
・スナバ抵抗、81B1.8N・・・・・・静電誘導サ
イリスタ(SIサイリスク)0特許出願人 東洋電機製造株式会社 代表者 土 井 厚
Figure 1, Figures 21 and 3 are circuit diagrams showing an example of a DC switch circuit employing a GTO thyristor equipped with a known snubber circuit device, and explanatory diagrams showing time transitions of the waveforms of each part, respectively. FIG. 6 is a circuit diagram showing one embodiment of the present invention and an explanatory diagram showing the time transition of waveforms of each part thereof, FIG. 7 is a circuit diagram showing another embodiment of the present invention, and FIG.
This figure is a circuit diagram showing a modified example of the apparatus shown in FIG. 3...Load, 4...Main circuit floating inductance, Snap 1 <5.5',5"...B71 ode, 6, 6', 6"
...Snubber capacitor? , 7', 7'...
・Snubber resistor, 81B1.8N...Static induction thyristor (SI Thyrisk) 0 Patent applicant Atsushi Doi, Representative of Toyo Denki Manufacturing Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 直流電源と負荷と静電誘導サイリスタを少なくとも備え
てなる直流スイッチ回路において、ダイオードに直列に
コンデンサを接続した直列接続体を前記静電誘導す・イ
リスタに並列接続し、該ダイオードとコンデンサの接続
点にインピーダンス素子の一端を接続するとともに、該
インピーダンス素子の他端を、静電誘導サイリスクの導
通期間中前記コンデンサを充電する如く前記直流電源に
接続したことを特徴とする静電誘導サイリスタのスナバ
回路装置。
In a DC switch circuit comprising at least a DC power supply, a load, and an electrostatic induction thyristor, a series connection body in which a capacitor is connected in series with a diode is connected in parallel to the electrostatic induction thyristor, and a connection point between the diode and the capacitor is connected in parallel to the electrostatic induction thyristor. A snubber circuit for an electrostatic induction thyristor, characterized in that one end of an impedance element is connected to the capacitor, and the other end of the impedance element is connected to the DC power supply so as to charge the capacitor during the conduction period of the electrostatic induction thyristor. Device.
JP16464783A 1983-09-07 1983-09-07 Snubber circuit device of electrostatic induction thyristor Granted JPS6057720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16464783A JPS6057720A (en) 1983-09-07 1983-09-07 Snubber circuit device of electrostatic induction thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16464783A JPS6057720A (en) 1983-09-07 1983-09-07 Snubber circuit device of electrostatic induction thyristor

Publications (2)

Publication Number Publication Date
JPS6057720A true JPS6057720A (en) 1985-04-03
JPH035691B2 JPH035691B2 (en) 1991-01-28

Family

ID=15797150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16464783A Granted JPS6057720A (en) 1983-09-07 1983-09-07 Snubber circuit device of electrostatic induction thyristor

Country Status (1)

Country Link
JP (1) JPS6057720A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4678932A (en) * 1985-04-30 1987-07-07 Mitsubishi Denki Kabushiki Kaisha Snubber circuit for GTO thyristor
EP0785627A3 (en) * 1996-01-17 1999-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor switching apparatus and method of controlling a semiconductor switching element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4678932A (en) * 1985-04-30 1987-07-07 Mitsubishi Denki Kabushiki Kaisha Snubber circuit for GTO thyristor
EP0785627A3 (en) * 1996-01-17 1999-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor switching apparatus and method of controlling a semiconductor switching element

Also Published As

Publication number Publication date
JPH035691B2 (en) 1991-01-28

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