JPS6057158B2 - non-volatile random access memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Industrial Application Field This invention relates to a random access memory device,
In particular, it relates to normally volatile random, access memory cells with non-volatile storage capabilities.

(2) Prior Art Currently, MNOS (Metal-Nitride-Oxide-Semiconductor) technology is being used successfully for monolithic integrated circuits with static or dynamic memories.

Static memory cells can be made into non-volatile structures,
Non-volatile static random access memory (RAM)
Examples of cells are assigned to the same person as the assignee of this invention, and 1
97:00 on November 2nd, George C. Lockwood (
GeorgeC. No. 3,651,492 issued to LDckwood. However, prior art dynamic RAM cells are volatile and typically consist of address transistors and volatile storage capacitors.

Memories based on this type of cell usually have an emergency power supply, which maintains the storage of data in the event of a loss of mains power. Volatile dynamic RAM must be refreshed at a rapid rate (on the order of every 2 milliseconds) and therefore requires relatively large amounts of energy during an extended power outage. Under such circumstances, non-volatile operation is desirable instead of volatile operation. Therefore, a dynamic RA that can operate in non-volatile mode
It is clear that the emergence of M memory cells is highly desired.

After that, a memory device having both volatile and non-volatile memory functions as disclosed in Japanese Patent Application Laid-Open No. 51-80731 1 Memory System and Japanese Patent Application Laid-Open No. 51-6553 1 Transistor Memory Element devices have been developed.

The former uses a variable threshold storage capacitor and an MO as one storage element.
The latter is also an MNO element.
It is composed of a mixture of an S capacitor and a MOS transistor. In either case, information is stored in a volatile manner in a variable threshold capacitor or capacitor, and in the event of a power failure, information is stored in a non-volatile manner in the same capacitor or capacitor. (3) Problems to be Solved by the Invention However, the above volatile/nonvolatile elements had the following problems.

In other words, the amount of charge that is transferred and stored in a non-volatile manner depends on the amount of charge that was previously stored in a volatile manner, but recently, as chip density has increased, capacitors have gradually become smaller and their storage capacity has decreased. I'm getting used to it. Moreover, the amount of charge gradually decreases due to loss of accumulated charge due to the long non-volatile retention period without refresh. The return of charge to a volatile memory depends on the amount of charge to be returned, but the above-mentioned prior art directly depends on the amount of charge, which poses a problem in the reliability of the result of the return operation. Therefore, it is an object of the present invention to provide a non-volatile dynamic RA capable of storing volatile information in a non-volatile manner, which allows emergency power to be used in the event of a power failure in a memory system.
M memory cells.

Furthermore, it is an object of the present invention to provide a reliable non-volatile memory that is not significantly influenced by the amount of stored charge or the amount of lost charge by a simple means of separating a volatile memory device and a non-volatile memory device. It is to provide cells. (4
) Means for Solving the Problem The present invention provides a capacitor for volatile storage and a separate threshold-rewritable (e.g., MNOS) transistor for non-volatile storage, and further provides a The above problem has been solved by using a transfer transistor that is used to transfer charge or return charge to a capacitor.

In other words, the charge accumulated in the nonvolatile transistor is not directly returned to the capacitor during the recovery operation, but is used only to determine the threshold value that controls the on/off of the nonvolatile transistor. The charge returned to the capacitor is supplied from another power source via a transfer transistor according to the on or off state of the nonvolatile transistor. As a result, it has become possible to restore the normal value of charge to the capacitor even if the charge held in the nonvolatile transistor changes considerably. (5) Summary of the invention The present invention is an improvement to RAM cells using charge storage structures such as MNOS or SNOS structures consisting of synthetic memory devices.

The RAM cell according to this improvement includes a memory device that stores signal information in a volatile manner, an address device that controls the input of information to the volatile memory device, and a RAM cell based on the volatile information stored in the volatile memory device. a threshold rewritable nonvolatile storage device that can be selectively activated to a predetermined threshold state;
and a transfer device for restoring signal information to the volatile storage device described above based on the threshold state of the nonvolatile storage device. (6) Embodiment Referring to FIG. 1, there is shown a schematic diagram of an R,AM cell 10 using the principles of the present invention, which includes a diffusion region 14,
It has 16.

In this embodiment, the spread regions or lines 14, 16 are each connected to a bit line 36 labeled RBJ, while a word line 28 labeled RwJ is connected to a dynamic RAM. Metallized gate 18 of the required representative volatile address transistor 18
．． 1 directly connected. Adjacent to the address transistor 18 is a volatile data storage capacitor 20 having an electrode 20.1 connected to a line 30 labeled RcJ. The other electrode of the capacitor 20 is connected to the channel region 1 of the semiconductor substrate on which the cell 10 is constructed.
It is represented by 2. Address ●Transistor 1
8 and capacitor 20 constitute a typical prior art dynamic RAM cell. A rewritable nonvolatile field effect transistor 24 is provided adjacent to the capacitor 20 .

Transistor 24 can be an MNOSFET with a uniform thickness memory oxide or an MNOSFET with a tri-gate or double-gate structure as described in US Pat. No. 3,719,866. The aforementioned U.S. Pat. No. 3,719,866 was filed on March 6, 197 by Charles T. Naller.
and GeOrgeC.Lockwood (GeOrgeC.
1OckwOOd) and assigned to the same person as the assignee of this invention. Line 32 labeled RMO is connected to gate metal 24.1 to control transistor 24. The schematic representation of gate 24.1 is shown with an arrow at one end to indicate its non-volatile nature. This nonvolatile property, i.e., the ability to retain its memory state in the absence of any bias gate voltage, is reflected in the aforementioned U.S. Pat.
Since it is described in detail in No. 19866, the explanation here will be made by quoting it. Nonvolatile transistor 24
A transfer transistor 26 having a gate 26.1 connected to a line 34 labeled RTJ adjacent to
is provided.

FIG. 2 represents another embodiment of a dynamic RAM cell according to the invention.

The RAM cell according to the embodiment is bit line 3.
In addition to 6, it has a return line 38 designated by JRJ.
In this embodiment, the function of bit line 36 of cell 10 of FIG. 1 is divided into bit line 36 and return line 38 in FIG. The first fruit of cell u-dan
In the exemplary P-channel MNOS cell 60 (FIG. 4), the structure of the cell 60 is similar to that of the cell 10 except that the ends of the P+ diffusion lines are connected to different P+ diffusion lines of adjacent cells 60. It has exactly the same structure. In the memory array 60-60 of cell 60, adjacent cells share a diffusion line, such that diffusion line 14 connects both the bit line of cell 60 in FIG. 4 and the return line of the cell adjacent to cell 60. Line 16 serves both as a return line for cell 60 and as a bit line for a cell adjacent to cell 60.

Thus, separate lines 14 and 16 provide bit line and return functions for the characteristic cell, but the waveform diagrams of FIGS.
4 and 16 will also be explained separately to facilitate understanding of the bit line function and the return function.
That is, at each given time, each of lines 14, 16 provides the same bit line and return effects for each of the different cells 60. Both lines 14 and 16 are placed at the same potential during store and restore operations to share bit line and restore functions for cell 60. Of course, it is within the skill of those skilled in the art to develop embodiments in which the bit lines and return lines are actually physically separated. Cell U and its embodiment 60 are more capable than Cell 10 as applied to design and construction for increasing density and are therefore the more preferred embodiment. To aid in understanding the operation of cell 50, in the following description lines 14, 36, 16, 38 are referred to not only by numerical designation, but also by their function or (and)
Represented by function and numbers.

For example, instead of specifying lines 14 and 16, specify 1 bit line or 1 bit line 14 and 0 return line or 1 return line 16. Also, an address transistor 18, a volatile storage capacitor 20,
Lines 28, 30, 32, and 34 for supplying voltage to the respective gates of non-volatile or memory transistor 24 and transfer transistor 26 are each designated with their function or terms suggestive of their function. For example, 1
Word line 28J or Rw line 28J. ．． r capacitor line 30J or Rc line 30, memory line 32J or RM line 32J, transfer line C or RT line CL, etc. Figure 4, Figure 5,
Referring specifically to FIG. 4, it represents the P-channel embodiment of cell Q of FIG.

The device is formed on an N-type substrate 11 and has permanent P+ channel diffusion regions 46-46 for connecting channel portions 12 formed through various device operations.
Also, the bit and return lines 14 and 16 are of P type. A thick protective coating 47 of field oxide formed over the substrate 11 provides electrical isolation between the substrate and the device. Devices 18, 20, 26 can all be constructed with gate isolation structures suitable for volatile fixed threshold transistor operation;
That is, the oxide layer 48,49 is typically about 450 mm thick.
, 51 and a silicon nitride layer 52 typically about 400 Å thick.
It consists of The channel region under the oxide mononitride gate insulator is then electrically connected using lines 28, 30, 34 and substrate electrode 50 to electrodes or gates 1 & 1, 20.1 and 26.1 and the substrate, respectively. A potential difference is provided between them. Electrode or gate 18.1, 20.1, 2
6.1 is typically made of a highly conductive material such as aluminum. As previously discussed, P+ channel diffusion regions 46-46 connect the portions of conductive channel 12 that are formed throughout the operation of each device.

For example, there are channel portions 61 and 62 associated with capacitor 20 and memory transistor 24, respectively. Diffusion regions 46-46 are not provided for use as sources and drains for respective devices. Rather, diffusion regions 46-46 are connected to gates 26.
1 and 24.1 or between gate 24.1 and electrode 20
．． 1, or between a gate and an electrode, which is required to form a channel 12 therebetween. Therefore, the diffusion region 46-46
can be omitted by using overlapping gates or electrodes separated by an insulator. The SNOS (silicon-nitride-monoxide-semiconductor) system is particularly advantageous for this method. As is apparent from FIG. 4, capacitor 20 has a structure similar to transistors 18, 24, and 26 and may also be referred to as a transistor or a data storage transistor.

However, capacitor 20 and transistors 18,2
4 and 26 are conventional 3 terminals (source, drain, gate)
FET (with field effect transistor or MNOSFET)
Rather than using source or drain here. As will be apparent from the modes of operation described below, the operation of devices 18, 20, 24, 26 utilizes both CCD (charge coupled device) and transistor principles.
However, to simplify terminology, we will refer to them as capacitors and transistors, respectively. The memory transistor 24 is approximately 15-60A thick in the thin memory oxide portion 53, and is typically approximately 450A thick in the medium-thickness oxide portion 54-54.
rigate) structure.

The memory oxide layer 53, which is very thin and has a low concentration of charge trapping centers, allows charge tunneling into the substrate. On the other hand, the silicon nitride layer has a high concentration of charge trapping centers.

By applying a suitable bias voltage to the gate 24.1 (e.g. aluminum) of the memory transistor 24 via the M-line 32, the memory oxide layer 53 and the silicon nitride layer 52 store charge tunneled from the substrate. and/or to tunnel to the substrate and release charge to set the value of the threshold voltage RvTJ of the memory transistor. In addition, the thick oxide portion 54-5
4 prevents the Zener breakdown of the transistor and prevents the consumption operation. The threshold voltage remains at the set value indefinitely after the bias voltage is removed.

This characteristic is the basis of the term 0 non-volatility. By appropriately choosing the bias voltage, the transistors can be set to different threshold voltages giving different binary states, thereby providing memory storage.RAM cell 60 uses the characteristics described below: Data in the volatile RAM portion of the cell is stored in a non-volatile manner.OPERATIONAL MODES To provide an accurate description of the operation of the exemplary non-volatile dynamic RAM cell 60, the following definitions are made.

When a line or element is driven to zero, the line or element shall be at a potential, i.e., 0V. When a line or element is driven high, the line or element shall be maintained at a negative high potential, i.e. -12V, unless otherwise specified. Volatile Operation No. 6 In the figure, through normal volatile operation of cell 60, capacitor 20 is accessed to 0V (if desired, transistor 18 is programmed).
The gate 18.1 of the bit line 14 is driven to 1 by the word line 28, and the bit line 14 is driven to 1 by the word line 28.
The electrode 20.1 of the capacitor 20 is driven forward by the line 30.

The gate 24.1 of the memory transistor 24 and the gate 26.1 of the transfer transistor 26 are driven or maintained at one lock. Since the gate 18.1 of the access transistor 18 is driven forward, the transistor 18 is conductive and the channel region 6 of the capacitor 20 is
1 potential φ. becomes 0V, which is the same potential as the bit line 14. The capacitor 20 is then charged or polarized. The charging or polarizing state is arbitrarily chosen as the ROJ binary state. It is clear that address transistor 18 and capacitor 20 are both used as a volatile dynamic RAM cell. If it is desired to write to the JlJ binary state (here chosen to be -12V) to the capacitor 20, the word line 28 and the capacitor line 30 are again connected, and the bit line 20 is driven to the JlJ binary state (here chosen to be -12V). In 36, it will be driven.

As in the previous case, the gates of the memory transistor 24 and the transfer transistor 26 are both driven or maintained at 1 rotation. As with the ROJ write, word line 2
8, the potential φc of the channel region 61 of the capacitor 20 is set to the same potential as the bit line 14. In this case, bit line 14 is at -12V and capacitor 2
0 is unpolarized and written to -12V, ie, RlJ state. The -12V potential on the bit line actually writes a potential less than -12V to capacitor 20.

This (ignoring other effects) φ. is close to the difference between the bit line potential and the threshold voltage of transistor 24, . That is, the bit line is -12
V. ．． When VT is -3V, φ. is -9V. The surface potential thereon should take into account the effects of VT, but for simplicity and ease of understanding it is assumed to be approximately similar in value to the potential supplied by, for example, a bit line. FIG. 6 shows RO to capacitor 20. j. or RlJ
Indicates the waveform when writing the status.

To reverse the volatile operation of cell 60, capacitor electrode 20.1 and gates 1 & 1 of access transistor 18 are driven at -12■ and line 36 is used to drive bit line 14 to O. The RO state is written by driving or maintaining it. Additionally, capacitor 20 drives electrode 20.1 and gates 1&1 to -12V, and the RlJ state is written by driving bit line 14 to -12V using line 36. Actually, 0
Binary information in the form of a V1 or -12V signal is a bit
It is transferred from line 14 to capacitor 20 and stored as a defined binary state. There may be instances where the non-volatile storage main power supply is shut down or otherwise interrupted.

Under such circumstances, it is understood that the volatile information stored on capacitor 20 should be shifted and stored to eliminate the need for the use of emergency power to refresh the stored data. , is a very big request. This cell 60 can accomplish the foregoing desire by storing its data in non-volatile memory transistor 24. Its memory operation is memory
The gate 24.1 of the transistor 24 is driven with a large negative voltage, for example -25 cm, and then, after a short period of time, the electrode 20.1 of the capacitor 20 is driven to 1, and the address gate of the transistor 18 is This is achieved by keeping 1 & 1 at 1 ro. As those skilled in the art will appreciate, typical volatile RAM cells can retain data for only a few milliseconds after a power outage, so the readout circuitry will not survive an unexpected or unwanted power failure. Sometimes a prompt memory operation is requested and executed immediately. Figure 7 shows a rewritable non-volatile memory that transfers data from the capacitor 20 to the transistor 24.
or represents a waveform used for storage.

The diagram is divided into time progressions TSO-TS3. 7th
The time increments of the diagram and the time increments of other waveform diagrams need not be equally spaced. First, assume that ROJ is transferred from capacitor 20 to memory transistor 24. Also, when the power is stopped, that is, line t! At the time of JO, (1) the memory transistor 24 has been pre-erased to a threshold voltage of, for example, VT=-3V, and (2) the potential φ of the channel region of the capacitor. is -12■ C1-12■ W. ．． OVf
) B (FIG. 6), and (3) after a write or refresh operation, the W line 28 is driven to 1, and the C line 30 is (continuously)). Also, since access transistor 18 is inactive and has terminated the connection between the capacitor channel and the bit line, it does not matter whether bit line 14 is at 1 low or 1 high. It's irrelevant. Immediately after the power is turned off, the capacitor 20 is charged to the maximum level in order to effectively transfer data.

It refreshes all capacitors in memory. At time TSL, approximately 2 milliseconds after refresh, W line 32 drives gate 24.1 of memory transistor 24 to -25V. First, the surface potential φ9 of the channel region 62 of the memory transistor 24 is driven toward the source 25 by the supplied voltage. Capacitor●Channel 61 potential φ. is 0 as mentioned above
It is V. The capacitor channel therefore contains a large concentration of holes (minority charge carriers). Approximately 125 of this memory transistor channel 62
The electrical potential attracts and shares these holes. Next TS2
At the moment , the C line 30 is driven to 1, driving the capacitor electrode 20.1 to 0V. The capacitor no longer attracts holes towards its capacitor channel, and in fact, the 0V capacitor channel
The gate voltage repels the holes from the capacitor, and moreover, the negative memory transistor voltage attracts the holes towards the memory transistor. This process quickly transfers enough holes toward the channel of the memory transistor 24 so that the potential φ. sufficiently raise it to near 0V. It creates a tunnel effect between the oxide 53 and nitride 52 interface between the substrate and the gate insulator to write to the memory transistor. The 25V potential difference resulting from the gate voltage of approximately -25V and the channel surface potential of approximately 0V results in a threshold voltage of approximately -10V.
This will write the transistor. If the capacitor 20 was in the RlJ state during a power failure, the holes would not be attracted toward the capacitor channel, and the memory voltage would remain intact even when the memory voltage received the write voltage and the capacitor was driven to one position. There are no holes to be transferred towards the transistor.

Memory transistor surface potential φ. is the gate 24.
The voltage is maintained at approximately -25V, which is approximately the same voltage as that of voltage 1. It is an insufficient potential to create a tunneling effect between the oxide-monitride interface. Therefore, memory transistor 24 is maintained in the erased state with VT=-3. In summary, throughout the memory operation, ROJ (0V) or RlJ
Volatile capacitor data (-12V) is converted to non-volatile to write the state of the memory transistor to ■7=-10V or erase Vτ=-3V, respectively. From capacitor 20 to memory ●transistor 2
The write and erase states caused by the transfer of ROJ and RlJ data to 4 control the data returned to the capacitor through the return operation described below. It should be noted that when storing RlJ state data in memory transistor 24, the surface potential φ9 that prevents tunneling lasts only approximately a few milliseconds.

Under typical environmental conditions, holes (which are minority carriers in N-type substrate 11) are continuously emitted by thermal generation and/or absorption of ionizing radiation.
Minority charge carriers are memory transistors 24
, and is attracted, raising the surface potential φM toward 0 V in a short period of about 10 to 20 milliseconds. The resulting potential difference across the gate insulator is the memory transistor 2
4 causes writing to occur. This unwanted write completes the storage transfer operation within a few milliseconds and is eliminated by removing the voltage from the memory transistor gate 24.1, as represented at time T,3. be able to. As an alternative to the above, it is of course also possible that the ambient temperature and light can be controlled to eliminate this writing. Non-volatile memory for information Transistor 2
4 means that the transistor 24 does not need to be refreshed periodically.
The stored information is stored in the dynamic R of cell 60 in order to utilize it.
It can remain in that state for months or years until it is desired to be transferred back to the AM cell section.

Restoration Operation Memory - Data can be restored from the transistor 24 to the capacitor 20 in either an inverting or non-inverting manner.

To return information to capacitor 20 in an inverted manner, word line 28 and bit line 3 must first be connected to each other.
6 and the capacitor ● line 30) must be charged to the y state. Next, word line 28 and bit line 36 are driven to 1, and capacitor ●
Line 30 is maintained at the end. Memory line 32 is then driven to -6■ and transfer line 3
4 will be driven to cause the inverted charge to be transferred from memory transistor 24 to capacitor 20. To explain the inversion return in detail, refer to the voltage waveform of FIG. 8.

The elapsed time in Figure 8 is t! RO~t! It is divided into R6. Initially, during TIRO, all lines and gates (W, B, C, M, T and R) are powered down to 0.
It's in V. At the time of TIRl, first the capacitor 20
is initialized in preparation for returning to the RlJ state. This supplies -12V to line 36 and makes bit line 14 -12V, also -12S! to word line 28 and connect the bit line to capacitor channel 61.
This can be accomplished by turning on transistor 18. Thereby, the surface potential φ of the capacitor 20. is set to -12S1 and the capacitor is written to the unpolarized RlJ state. t! after initializing the capacitor! R
At 2 o'clock, the operating signal to address transistor 18 is cut off to disconnect capacitor 20 from bit line 14. T! At R3, the bit line is driven to 0V. At TlR4, transfer transistor 26 is supplied via T line 34 - 1
Return line 3 is driven by a 2V gate signal and is at 0V across channel region 62 of memory transistor 24.
Connect to 8. Therefore, at this point, the bit
line and return line are 0V1, gate 26.1 of transfer transistor 26 is -12■, memory transistor 2
4 gate 24.1 is 0V1 capacitor 20 gate 2
0.1 is -12V. At TIR 5, a read voltage of -6V, which is approximately an intermediate value between the respective threshold voltages of the memory transistors 24 -3V and -10V, is applied to the M line 32.
to the memory gate 24.1.

If the threshold voltage VT of the memory transistor is -3V
If , this -6V signal causes the memory transistor to conduct. Therefore, memory transistor 2
4 and transfer transistor 26 supply 0V on return line 16 to -12■ capacitor channel 61, so that the capacitor channel is discharged to 0V. Therefore, the original RlJ state is transferred to the erased memory transistor, and the capacitor is inverted back to the RRO state. If Vτ is -10V,
When a -6V read voltage is applied, the memory transistor does not conduct and the channel region of capacitor C remains at -12V. If the original ROJ capacitor state had been transferred to the memory transistor, RlJ inverts back to the capacitor state. One advantage of the inverting return operation is that it is relatively insensitive to threshold voltage drops if the read voltage is chosen appropriately. For example, if the initial If the threshold voltage is either -3V1 or -10■, the threshold voltage changes from -3V to -5V and -10
Even in the event of a decay from V to -7V, a typical -6V interrogation voltage can be used to ensure proper recovery. Moreover, since the memory transistor 24 is used relatively infrequently, i.e., only for non-volatile storage operations and recovery operations, functional deterioration due to wearout occurs in both inverting and non-inverting modes of operation. But very few.
As mentioned above, since the capacitor 20 returns in an inversion manner, the original or -12-1 surface potential of the channel region 61 of the capacitor when the power is turned off is -12■, respectively.
Or return to 0V.

This requires the RAM circuit to recognize the inversion, or to perform a double restoration operation to invert the inverted data again to create non-inverted original data. Either case is easy to implement. If it is desired to return information to capacitor 20 without inversion, drive word line 28 and capacitor line 30 to
One bit line 36 is driven or maintained at 1 to precharge the capacitor.

Memory line 32 and transfer line 34 are also driven or maintained in one rotation. capacitor line 30
On the other hand, drive the word line 28 to 1. Memory line 32 to -10V,
The transfer line 34 is driven to a high voltage, and φc is driven to -10V by the subsequent power supply operation (the voltage of the transistor 24 is
, attenuated by ). Here, cell 60 again functions and operates in a normal dynamic RAM mode requiring periodic refresh and having the ability to store information as desired. Reference is made to FIG. 9 for a detailed discussion of the non-inverting mode of operation.

It represents a useful waveform for explaining the non-inverting mode of operation.
The passage of time is expressed as TNRO-TNR6. TNR
O time represents a power-off state, and all elements are placed in their positions. During TNRl, word line 28 and capacitor line 30 are set to -12V to activate address transistor 18 and capacitor 20, and bit line 14 is set or maintained to 0V to activate capacitor channel region 61. potential φ. is driven to O■. This will initialize the capacitor by writing the charged ROJ state to it. Next, in TNR2, set the word line 28 to 0.
Address transistor 18 by driving to V
is deactivated.

At the same time, the return line 38 and the transfer transistor 26
The gate 26.1 of is set to -12V to invert the potential across the channel of the memory transistor. At TNR3, assuming 0V on the gate 24.1 of the memory transistor, the left and right sides of the memory transistor channel 62 are at 0V and -12V, respectively. The return operation is completed by supplying -10V to the gate 24.1 of the memory transistor (at TNR3, if desired).

If Vτ is -10V, the memory transistor will not conduct at all and the channel region of capacitor 20 will remain at 0V, returning the capacitor to its original ROl state. However, if the threshold of memory transistor 24 is -13V in the erase state, the memory transistor providing -10V to gate 24.1 will be turned on and its source will be -7V. The channel region of capacitor 20 is then charged to -7V, bringing the capacitor to a negative potential. In summary, the channel area of capacitor 20 will be either 0V or -7V depending on whether -3V or -10V is written to the memory transistor.

In terms of the magnitude of the restored charge, the non-inverting -7V return is not as complete as the -12V provided in the inverting mode of operation. However, non-inverting return is caused by capacitor 20
has the advantage that the polarity is restored to the same polarity that existed when the power was turned off. Moreover, there is no problem since the -7V recovery charge is completely restored to 12V by the subsequent refresh operation. After the return operation is complete, preparation can be made for the subsequent operation by turning off all elements, as shown at TNR in FIG.

The capacitor electrode 20.1 continues to bias the capacitor to maintain data. Due to the standard volatile memory portion of cell 60, the refresh operation must begin within approximately 2 milliseconds after the return operation is completed, and capacitor 2
The refresh operation must be repeated every 2 milliseconds to maintain the zero state.

Transfer gate 26.1 and memory gate 24.1 are 0
When V, accessed by word line 28
Transistor 18 is turned on and capacitor 20
The charge stored in is read out via bit line 36 to a reading device. In the case of non-inverted RlJ return, −
Use the circuitry necessary to refresh the 7V charge to -12V. Ru.

Cell 60 then returns to its normal volatile mode of operation. FIG. 3 depicts a memory cell array using cells 10.

Cell 50 or cell 60 are used in a similar manner. Each bit line of the common column is J common line 36.1, 36.
2, 36.3, and 36.4, and each word line of the common row is connected to common lines 28.1, 2, respectively.
&2, and 28.3. Thus, a particular memory cell is designated and its location within the array is accessed. For example, if it is desired to access the cell in the bottom left hand corner of the array, it will be accessed by word lines 2 & 3 and bit line 36.1. The gates of all capacitors 20-20 of cell 10 are connected to line 300 and the gate of memory transistor 24 is connected to line 320. Similarly, the gates of all transfer transistors 26 are connected to line 340. With such an arrangement, the device can be stored and erased in groups or matrices, which is very convenient. To clarify the organization of the memory array, there is also a read amplifier 42 for reading output data and an input driver 40 for writing data to the memory.
are shown schematically.

A read amplifier 42 is provided for each column of the memory array, but only one read amplifier is shown to simplify the drawing. Additionally, those skilled in the art will appreciate that a variety of other read amplifiers and driver devices can be used to read and write to cells 10-10, and that cell 10 can be utilized in many memory organizations. That's obvious. One example of such a memory organization is the 16 kbit dynamic RAM memory described in ElectrOnlcs, April 28, 1977, pages 115-119.

Although in the embodiments of the invention described above the cells have been described as operating in P-channel mode, it will be appreciated that N-channel cells may be used with appropriate opposite polarity.

Although the memory array according to this embodiment has been described as a 3×4 matrix, the invention is not limited thereto, but only to the dimensions of the chips on which the array of cells is constructed. (7) Effects of the Invention As is clear from the above explanation, according to the present invention, by separating the volatile memory capacitor and the nonvolatile memory transistor and using a transfer transistor in addition, Regardless of the amount of charge to be stored, or even if there is a considerable change in the amount of charge to be stored in a non-volatile manner, the non-volatile storage state can be correctly restored to the volatile storage device, i.e., the storage capacity decreases. We were able to provide a nonvolatile RAM memory cell that has a very wide tolerance range and doubles the reliability of nonvolatile memory.

Moreover, unlike the prior art, the memory cell according to the present invention does not require any special external equipment or its operation, and can easily perform inversion recovery and non-inversion recovery by simply changing the recovery operation sequence. I can do it.

In addition, since the non-volatile transistor according to the present invention is used only occasionally during non-volatile operation, there is little functional deterioration and the lifetime is long, resulting in further increased reliability. Furthermore, the memory cell according to the invention stores the information restored to the volatile memory during erasure or initialization in preparation for the next non-volatile memory in an external temporary memory, as in the prior art. This has the advantage that volatile operations can be continued immediately after recovery.

[Brief explanation of the drawing]

Figure 1 shows one of the new RAM cells using the principle of this invention.
FIG. 2 is a diagram illustrating another embodiment of a novel RAM cell using the principles of the invention; FIG. 3 is a diagram illustrating a representative RAM of the invention arranged in a matrix of rows and columns. A schematic diagram showing the memory array of the cell; FIG. 4 is a partially omitted cross-sectional view showing an embodiment of the P channel of the RAM cell shown in FIG. 2; FIG. 6 is a diagram of voltage waveforms used during a normal volatile write operation of the P-channel RAM cell of FIG. 4; FIG. 7 is a non-volatile diagram of the P-channel RAM cell of FIG. 4. Waveform diagram of voltage used during sexual memory operation;
8 is a waveform diagram of the voltage used during the inversion return operation of the P-channel RAM cell of FIG. 4; FIG. 9 is a waveform diagram of the voltage used during the non-inversion return operation of the P-channel RAM cell of FIG. 4. Represents a waveform diagram. 10...RAM cell, 14, 16...diffusion region, 18...address transistor, 20...
・Capacitor, 24...Nonvolatile transistor, 26...Transfer transistor, 28...
・Word●line, 36...Bit line,
40...Write driver, 42...Read amplifier, 46...P channel diffusion region, 47
...Field oxide protective coating, 48, 49, 51
... Thick oxide layer, 50 ... RAM cell, 52 ... Nitride layer, 53 ... Thin memory oxide layer, 54 ...・Intermediate oxide layer,
60...Cell, 61...Capacitor
Channel, 62...Memory transistor channel.

Claims (1)

[Claims] 1 A memory cell formed on a semiconductor substrate of a predetermined conductivity type and configured to store binary information determined by the potential of a substrate region of an opposite conductivity type, the memory cell having one electrode formed on the substrate. , a capacitor 20 for volatile storage of binary digit information determined by the potential of the opposite conductivity type substrate region; and a capacitor 20 for selectively charging the capacitor 20 during volatile operation of the cell to store binary digit information in the capacitor. a first supplying a substrate region potential to a substrate electrode of the capacitor during volatile storage of information and when selectively charging and initializing the capacitor prior to restoring binary digit information to the capacitor; transistor means 18 and a channel formed in the substrate adjacent to the substrate electrode of said capacitor for selectively changing the threshold by charging said capacitor 20 to non-volatilely store binary digit information on said capacitor; a second transistor means 24 whose threshold value can be rewritten; and a channel formed in a substrate adjacent to a channel of the second transistor means whose threshold value can be rewritten; a second transistor means capable of supplying a predetermined potential of the substrate region of the opposite conductivity type different from the initialized potential to the substrate electrode of the capacitor under control of the threshold voltage of the second transistor means; 3 transistor means 26;