JPS6056355B2 - signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing circuit that can be applied to signal processing such as matrix and switching of television audio multiplexed signals.

This signal processing circuit is equipped with a level adjuster.
By adjusting this adjuster, for example, the degree of separation during stereo broadcast reception can be adjusted.

By the way, if the DC level of the output circuit changes due to this adjustment, each time the operation mode of the signal processing circuit changes,
This is recognized as the so-called hop sound. For example, even if the signal processing circuit is configured with a well-balanced differential pair, the input signal to the signal processing circuit M depends on the operation mode of the sub-channel signal by the inverter N, as shown in FIG. For devices that use or do not use an inverted signal, and for devices where the volume P for adjusting the degree of separation also changes the DC level of the system, it is necessary to switch the operating mode, that is, to make a difference. When the inverter, which is different from the dynamic pair, is attached or detached, the DC level of the output circuit fluctuates, resulting in a hopping sound. The present invention aims to provide a signal processing circuit which has a function of adjusting the degree of separation and is devised so as not to generate this hopping sound when switching operation modes, regardless of the adjustment position. Next, the present invention will be explained based on an embodiment applied to a television audio multiplex receiver.

As shown in Figure 2, the television audio multiplex signal is made by frequency multiplexing the main channel signal A, the sub channel signal B, and the control channel signal C. is the main audio signal and also consists of a sum signal in the case of stereo broadcasting, and the sub-channel signal consists of the subcarrier center frequency (2fH: FH is the horizontal frequency) as the sub-audio signal (in the case of dual audio broadcasting) or the difference signal. signal(
In the case of stereo broadcasting), the control signal is frequency-modulated with the control signal subcarrier (3.5fH) to distinguish between these two types of broadcasting.
1 = 922.5Hz: in the case of double audio broadcasting) or the second frequency (F2 = 982.5Hz: in the case of stereo broadcasting)
It consists of amplitude modulated data. This television audio multiplex signal is obtained by FM modulating the audio carrier wave of the television broadcast signal. Therefore, this television audio multiplexed signal can be derived to the output terminal of the front end including the tuner, IF circuit, FM discrimination circuit, etc. FIG. 3 shows a block diagram of the main part of the receiver for this signal.

The television audio multiplexed signal derived from the output terminal 2 of the front end 1 is applied to a low-pass filter 3 and a band-pass filter 4 via a preamplifier 5, and from the low-pass filter 3, the main channel signal A is Further, the sub-channel signal B and the control channel signal C are separated from the band-pass filter 4. The sub-channel signal B is a limiter amplifier 7 built in the integrated circuit 1C6,
The signal is supplied to a demodulation circuit 10 including a pulse counter type discrimination circuit 8 and an amplifier 9, and a sub-audio signal or a difference signal is derived as its output. The output of this demodulation circuit is processed by a low-pass filter 11 for removing subcarriers and a stereo separation degree adjuster 1.
2 to the signal processing circuit 13 in the IC 6 together with the main audio signal or sum signal constituting the main channel signal A. The control channel signal C separated from the bandpass filter 4 is sent to the amplifier 14 in the IC 6 and the AM detection circuit 1.
5 and derives as its output a control signal of the first or second frequency.

16 is a tuning circuit tuned to the control signal subcarrier (3.5 fH).

This control signal connects the second ICl7 (elements of this IC to the first
It goes without saying that it may be included in an IC to form a single chip). Valid signals are derived from the PLL l8, and from the second PLJ, l9 when the control signal has the second frequency. These first and second PI-J. l
Each output signal from 8 and 19 is applied to a comparator 20 in the 11C6, and the output signal from the comparator 20 is applied to the first and second control circuits 21 and 21 in the signal processing circuit 13.
22 and the indicator drive circuit 23.

The indicator drive circuit 23 has light emitting diodes Ll, Ll, Ll and Ll connected in parallel in opposite directions between its output terminal 24 and a point 27 where the power source is divided by resistors 25 and 26.
The light emitting diode L2 is selectively turned on when receiving a dual audio broadcast, and the light emitting diode L2 is selectively turned on when receiving a stereo broadcast. Note that this comparator 20 has first and second control circuits 21,
22, a high level control signal is applied when receiving a stereo broadcast, and a low level control signal is applied when receiving a dual audio broadcast. Next, an embodiment of the signal processing circuit 13 will be described based on the actual circuit diagram shown in FIG.

This signal processing circuit 13 includes a first input terminal 28 into which a first signal (main channel signal) is introduced, and first and second differential amplifiers Al, into which the first signals from this first input terminal are respectively introduced. A2, a second input terminal 29 into which a second signal (demodulated sub-channel signal) is introduced, and third and fourth differential amplifiers A3 and A4 into which the second signal from this second input terminal is respectively introduced. , a fifth differential amplifier A5 configured in the upper stage of the third differential amplifier A3, a first output circuit 30 for deriving the output signals of the second and/or third differential amplifiers A2 and A3, 1 and/or 4th differential amplifier Al, A
a second output circuit 31 that derives the output signals of the first and fourth output signals;
second, third, and fourth differential amplifiers Al, A2, A3,
A first control circuit 21 that creates first to fourth control signals Al, a2, a3, a, which individually control the operation of A4, and the operation of the fifth differential amplifier A5 and the first control circuit 21. The second control circuit 22 controls the operation of the second control circuit 22. The first to fourth differential amplifiers Al, A2, A3, and A4 each have first to fourth constant current sources Bl, B2, B3, and B4 that share the constant voltage circuit 32, and The differential amplifiers Al and A2 are energized by a first bias circuit 33, and the third and fourth differential amplifiers A3 and A4 are energized by a second bias circuit 34.

The first differential amplifier A1 has first to fourth transistors Ql, Q2, Q3, and Q4, receives a first signal from the first input terminal 28 through an emitter-follower type transistor q, and receives the first signal from the first input terminal 28 through an emitter-follower type transistor q. The signal can be amplified by four transistors Ql and Q4 and provided to the second output circuit 31. Further, the second differential amplifier A2 has the sixth to
It has a ninth transistor Q6, Q7, Q8, 9 and transmits the first signal from the first input terminal 2' to the 10th emitter-follower type transistor.
Transistor Ql. and is amplified by the sixth and ninth transistors Q6, Q, and output to the first output circuit 3.
0. Further, the third differential amplifier A3 includes the eleventh to fourteenth transistors Qll,
Ql2, Ql3, Ql4 receives the second signal from the second input terminal 29 through the 15th transistor Ql of emitter follower type, amplifies it by the 11th and 14th transistors Qll, Ql, and further amplifies the second signal from the second input terminal 29. The signal can be supplied to the first output circuit 30 through a fifth differential amplifier A5 configured at the upper stage of the differential amplifier. Furthermore, the fourth differential amplifier A4 has 16th to 19th transistors Ql6, Ql7, Ql8, Ql9, receives the second signal from the second input terminal 29, and transmits it to the first ePS first
The signal can be amplified by nine transistors Ql6 and Ql9 and supplied to the second output circuit 31. Fifth
The differential amplifier A5 includes the 20th to 23rd transistors Q2O.
, Q2l, Q22, Q23, and when the 20th and 23rd transistors Q2O, Q23 are on, the second input terminal 2
The output signal in phase with the second signal from 9 is passed through the 14th transistor Q of the third differential amplifier A3, and is also output to the 21st
And when the 22nd transistors Q2l and Q22 are on, the output signal from the second input terminal with the opposite phase to the second signal is sent to the third input terminal.
The signals are distributed and supplied to the first output circuit 30 through the eleventh transistor Qll of the differential amplifier A3. The first output circuit 30 and the second output circuit 31 have 24th, 25th, 26th, and 27th transistors Q24, Q25, Q26, and Q27, respectively, and their respective amplified output signals are outputted from the first and second outputs. It is configured to be led out through terminals 35 and 36.

The first control circuit 21 has first to fifth control input terminals Cl,
C2, C3, C, , C5, and control output terminals Dl, d2, d3, d4 from which first to fourth control output signals Al, a2, a3, a4 are derived.

The first control input terminal C1 receives an output signal from the comparator 20, and when the output signal is at a level indicating stereo broadcast reception, the 28th and 29th transistors Q
28 and Q2 are turned on, and the 30th and 31st transistors Q3O and Q3l, respectively connected in cascade thereto, are turned off. A switch S1 constituting the mode command circuit 37 is applied to the first control circuit 21 through the second and third control input terminals FC2 and C3.
I am trying to invalidate the directive. On the other hand, when receiving dual audio broadcasting where the output of the comparator is low level, the second
The 8th and 29th transistors Q2B and Q9 are turned off so that they can provide a control output according to the command from the mode command switch S1. The fourth and fifth control input terminals C4,c receive a control output signal from the second control circuit 22, and the 32nd to 35th transistors Q3 constitute the first control circuit. , Q33, Q34, and Q35, respectively. Each control output terminal Dl, d2 of this first control circuit 21
, d3, d4, first to fourth control signals a1 to A4 as shown in the diagram of FIG. 5 are created for each control input, and these are sent to the first to fourth differential amplifiers Al, A2 ,A3,A4
each transistor pair provided for, ie, second and third transistors Q2, Q3, seventh and eighth transistors Q7, Q8,
The twelfth and thirteenth transistors Ql2, Ql3, and the first
7, the 18th transistors Ql7, Ql8. The second control circuit 22 has first to third control input terminals Fel, e2, e3, and first to fourth control outputs. It has terminals Fl, f2, f3, f4.The first
The control input terminal e1 of receives the output signal from the comparator 20, and when the output signal is at a high level indicating stereo broadcast reception, the 3rd eK 37th transistor Q6
, Q37 are turned on when the switch S2 connected to the third control input terminal Fe3 is turned off. When the first inch means S3 connected to the second control input terminal e1 is on (muted off), the first wing transistor Q3l! is on, the operation of the fifth differential amplifier A5 is controlled through the first and second control output terminals Fl and f2, and the 39th transistor Q39 is also turned off to output the third control output terminal F3 ( Fourth control input terminal F of the first control circuit
c4) to low level. Then, the level of each control output terminal of the first control circuit 21 is all set to low level. At this time, when the switch means S2 connected to the third control input terminal E3 of the second control circuit 22 is turned on, the comparator 20
Since the level to the first control input terminal OX is set to a low level, that is, equivalent to what is done when receiving a dual audio broadcast, both the 3e1S and 37th transistors Q and Q37 are turned off, and therefore the 5th The operation state of the differential amplifier A5 is inverted, and a high level signal is presented to the fourth control input terminal C4 of the first control circuit 21. By the way, at this time, the 28th and 29th transistors Q28, Q2 of the first control circuit 21 and the 38th transistor Q3B of the second control circuit 22 are all on, so the 32nd to 35th transistors of the first control circuit are turned on. All of them are turned on and the first to fourth control output signals Al, a2 of the first control circuit 21 are
, a3,a are maintained at a low level. At this time, the fifth differential amplifier A5 is connected to the first output circuit 3.
5 is provided with a signal that is in phase with the second signal from the second input terminal 29, so when this is matrixed with the first signal from the first input terminal 28, the second output circuit 36
It is possible to output only a signal of the same quality as the output signal from, that is, only one channel. By the way, when the switch means S3 connected to the second control input terminal E2 of this second control circuit 22 is turned off (muted on), the second wing transistor Q38 is turned off, so that any other control input terminal is in any state. No matter what, the first control circuit 21's . The 32nd to 35th transistors and the 3fK 37th transistor of the second control circuit 22 are placed in a floating state, and each control output signal of the first control circuit 21 is all set to a high level, thereby controlling the first to fourth differential amplifiers. All operations of A1 to A4 are stopped.

During the period in which the switch means S3 is turned off, output signals can be prevented from being derived from the first and second output circuits 35 and 36. This is useful, for example, when receiving an incoming telephone call while receiving a broadcast, or when you want to temporarily interrupt the derivation of the output signal, or when switching channels, especially when switching from a station transmitting a subchannel signal to a station not transmitting it. The switch means S3 is used to remove the hopping sound (caused by the residual sub-channel signal) that sometimes occurs, and the former is manually operated by a remote controller, and the latter is by a channel selection signal temporarily created when selecting a channel. All you have to do is control it.

Next, the operation of this signal processing circuit in each mode will be briefly explained. Since the operation when the switch means S3 is open (mute-on) and the operation when the switch means (2) is turned on have been described above, the case where these switch means are in the state shown in FIG. 4 will be described below. j (a) In the stereo mode, at this time, as mentioned above, each output signal a1 to A4 of each control output terminal, D2, d3, d4 of the first control circuit 21 is at a low level, so the first to fourth output signals a1 to A4 are at a low level. Each differential amplifier A1 to A4
Both are set to active state.

Further, in the fifth differential amplifier A5, its 21st and n-th transistors Q2l and Q22 are turned on. Therefore, the first signal, that is, the stereo sum signal (L+R) from the first input terminal 28 is sent to the second output circuit 31 via the first differential amplifier A1 and via the second differential amplifier A2. A second signal, that is, a stereo difference signal (L-
R) is the eleventh transistor Q of the third differential amplifier A3
ll, the 21st transistor Q2 of the fifth differential amplifier A5
1 to the first output circuit 30 in opposite phase and to the second output circuit 31 in phase through the fourth differential amplifier A4. Therefore, the first output circuit 30 receives the stereo sum signal (L+R) from the first input terminal 28 and the opposite phase signal (L-R) of the stereo difference signal from the second input terminal 29.
), and an output signal of -2R can be derived from the first output terminal 35. Further, since each signal from the first and second input terminals 28 and 29 is applied to the second output circuit 31 in the same phase, an output signal of -2L can be derived from the second output terminal 36. I can do it. In other words, it is possible to enjoy stereo broadcasting. A constant current from constant current circuits 8 to B flows through input terminals 38 and 39 of each output circuit 30 and 31, and the DC levels at these input terminals are El and E2, respectively. The second input terminal 29 is equipped with the stereo separation degree adjuster 12 as described above, which has a volume 40 and a coupling capacitor 41 as shown in the figure, so that the AC level of the second signal can be adjusted without changing the DC level of the second signal. so that it can be adjusted.

Through this adjustment, it is possible to control the mixing ratio of the stereo sum and difference signals and adjust the degree of stereo separation, but even with this adjustment, the above-mentioned DC levels remain unchanged. (b) When the switch S1 is set to terminal 1 (main channel mode of dual audio broadcasting), in this case, the first and second control output terminals of the first control circuit 21 are connected as shown in the diagram of FIG. ，
, D2 are at low level, and each output signal A3, a of the third and fourth control output terminals D3, d4 is low level.
4 is at high level, the first and second differential amplifiers A
l, A2 are in operation, third and fourth differential amplifiers A3, A
4 is set to the inactive state.

Therefore, only the first signal from the first input terminal 28, that is, the main channel M signal of the dual audio broadcast, is applied to the first and second output circuits 30 and 31. In this case as well, constant current circuits Bl and B are connected to the input terminals 38 and 39 of each of these output circuits.
A constant current flows from 2, and the DC levels at this input terminal are respectively El and E2 as in the case (a) above. (c) When switch S1 is set to terminal 2 (double audio broadcast sub-channel mode), the above (
Contrary to the above, the first and second differential amplifiers Al and A2 are inactive, the third and fourth differential amplifiers A3 and A4 are active, and the fifth differential amplifier A5 is The second to 23rd transistors Q2O and Q23 are in an operating state.

Therefore, the first signal from the first input terminal 28 is outputted, and the second signal from the second input terminal 29, that is, the sub-channel signal of the dual audio broadcast, is outputted to the 14th differential amplifier A3.
Channel Ql4 is applied in phase to the first output circuit 30 through the 23rd transistor Q23 of the fifth differential amplifier A5, and also applied in phase to the second output circuit 31 through the fourth differential amplifier A4. . A sub-channel signal can therefore be derived from both output circuits. (d)
When the switch S1 is set to terminal 3 (main and sub channel mode of dual audio broadcasting), the output signals shown in the diagram of FIG. 5 are applied to the first to fourth differential amplifiers A1 to A4. Then, the first and third differential amplifiers Al and A3 are rendered inactive, and the second and fourth differential amplifiers A2 and A4 are rendered operational.

The first signal from the first input terminal 2', that is, the main channel signal, is sent to the first output circuit 30 through the second differential amplifier A2, and the second signal, that is, the sub-channel signal from the second input terminal 29 is sent to the first output circuit 30 through the second differential amplifier A2. are applied in phase to the second output circuit 31 through the fourth differential amplifier A4.
Therefore, different types of dual audio broadcast programs can be individually derived from each output terminal 35, 36.

In each of the above (c) and this (d) modes, the above (
As in the modes A) and (A), each output circuit 30, 31
The DC levels of the input terminals 38 and 39 are El and E2 and remain unchanged. Note that during monaural reception, the signal from the first control input terminal of the first control circuit is set to high level,
Further, the signal from the first control input terminal e1 of the second control circuit is configured to be set to a low level, and the control output signal from each control output terminal of the first control circuit is set to a low level. Similarly, a monaural signal can be derived from each output terminal 35, 36. As described above, the present invention includes a first input terminal for introducing a first signal;
first and second differential amplifiers each introducing the first signal from the first input terminal, a second input terminal introducing the second signal, and a second signal from the second input terminal, respectively; A third and fourth differential amplifier to be introduced, a fifth differential amplifier configured on the upper stage of the third differential amplifier, and a fifth differential amplifier to derive the output signal of the second and/or third differential amplifier. 1 output circuit, a second output circuit that derives the output signals of the first and/or fourth differential amplifiers, and operations of the first to fourth differential amplifiers, respectively, are individually controlled. 1st to do
a first control circuit that generates a fourth control signal;
a second control circuit that controls the operation of the differential amplifier and the operation of the first control circuit, and controls each operation of the first to fifth differential amplifiers according to each command mode. In order to make each output circuit present an output according to the command, and to adjust the degree of stereo separation during stereo reception, the DC level of the input signal is changed by a regulator attached to the second input terminal. Since only the alternating current level is changed without changing the mode, there is no change in the direct current level at the input end of each output circuit when controlling switching between each mode, and therefore no hopping noise is generated.

Strictly speaking, it cannot be said that there is no fluctuation in the DC level at the input end of each output circuit due to the unbalance of each differential pair of transistors constituting each differential amplifier, but this is almost negligible.゛Furthermore, in the embodiment of the present invention, the first
1 a bias circuit applied to the second differential amplifier;
Since the bias circuits applied to the fourth differential amplifier are configured separately, the first and second signals may be transmitted to the transmission path of the other party, which is different from the original transmission path, causing crosstalk or separation. It is possible to effectively prevent the improvement of the degree.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a conventional circuit.

Claims (1)

[Claims] 1 A first input terminal into which a first signal is introduced, first and second differential amplifiers into which the first signal from the first input terminal is respectively introduced, and a second input terminal into which a second signal is introduced. , third and fourth differential amplifiers each introducing the second signal from the second input terminal, and a fifth differential amplifier connected in cascade to the third differential amplifier. , a first output circuit for deriving the output signal of the third differential amplifier obtained via the second and/or fifth differential amplifier; and the first and/or fourth differential amplifier. a second output circuit that derives the output signal of the differential amplifier; a constant current circuit provided in each of the first, second, third, and fourth differential amplifiers;
a first control circuit that generates first to fourth control signals for individually controlling operations of the first, second, third, and fourth differential amplifiers, and a fifth differential amplifier; a second control circuit that controls the operation of the amplifier and the operation of the first control circuit; and a regulator that adjusts the AC level of the second signal without changing the DC level of the second signal at the second input terminal; The fifth differential amplifier operates as an inverting amplifier in the stereo mode by the second control circuit, and as an in-phase amplifier in non-stereo mode, and
, the DC level of each input terminal of the second output circuit is
A signal processing circuit configured such that the signal processing circuit does not vary regardless of the mode of the first to fourth control signals from the control circuit and regardless of the adjustment of the regulator.