JPS6054061A - Interface circuit - Google Patents
Interface circuitInfo
- Publication number
- JPS6054061A JPS6054061A JP58162856A JP16285683A JPS6054061A JP S6054061 A JPS6054061 A JP S6054061A JP 58162856 A JP58162856 A JP 58162856A JP 16285683 A JP16285683 A JP 16285683A JP S6054061 A JPS6054061 A JP S6054061A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- common bus
- power supply
- circuits
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
- G06F13/4077—Precharging or discharging
Abstract
Description
【発明の詳細な説明】
発明の技術分封
本発明は、制御装置に対し、共通バスを介して複数の搬
送端局装置等を接続し、共通バスを介してデータの授受
を行なうシステムにおいて、共通バスとのインターフェ
ースを取るインターフェース回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system in which a plurality of carrier terminal devices, etc. are connected to a control device via a common bus, and data is sent and received via the common bus. This invention relates to improvements to interface circuits that interface with buses.
従来沙術及び問題点
従来から、複数の搬送端局装置を塑御するため、第1図
の如く制御装置CON Tに対し、共通バスBUSを介
して搬送端局装置T、〜Tnを接続し、データの授受を
行なっている。Conventional Techniques and Problems Traditionally, in order to control a plurality of carrier terminal devices, carrier terminal devices T, ~Tn are connected to a control device CON T via a common bus BUS, as shown in Fig. 1. , which exchanges data.
各搬送端局装置t Tl−Tnは共通バスBUSとのイ
ンターフェースのためインターフェース回路剪q戸舛=
前)を備えている。Each carrier terminal device Tl-Tn has an interface circuit for interfacing with the common bus BUS.
(before).
各インターフェース回路は、入出カポ−)IOPを構成
するレシーバRとドライバDR及びこれらに電泳を供給
する電源ユニソ)PUを含んでいる。Each interface circuit includes a receiver R and a driver DR constituting an input/output coupler IOP, and a power supply unit PU that supplies electrophoresis to these receivers R and driver DR.
この構成において、特に電源ユニットPUの断時レシー
バRとドライバDRは共通バスBUSから見て低インピ
ーダンスに見えることがあり、このだめ1つの端局の電
源ユニットが断になると、他の端局へのデータの授受が
でき在くなる欠点があった0
発明の目的
本発明は、この様な欠点を除去し、ある端局の電佇ユニ
ットが断になっても他の端局に対して影響を与えない様
にしたインターフェース回路を提供することを目的とす
る。In this configuration, especially the disconnection receiver R and driver DR of the power supply unit PU may appear to have low impedance when viewed from the common bus BUS. Object of the Invention The present invention eliminates these drawbacks, and prevents even if the power station unit of one terminal station is disconnected from affecting other terminal stations. The purpose of the present invention is to provide an interface circuit that does not cause
発明の構成
」二記目的は、本発明によれば、共通バスからのデータ
を受信し、共通バスへデータを送出する入出力ボートと
、該入出力ボートへ電源を供給する電源と、該電m電圧
が規定値であるか否かを検出し、規定値υ下であること
を検出した特技共通バスと入出力ボート間の接続を断に
するブレーク回路な壱することを特徴とするインターフ
ェース回路によって達成される。According to the present invention, an input/output boat that receives data from a common bus and sends data to the common bus, a power source that supplies power to the input/output boat, and an input/output boat that receives data from a common bus and sends data to the common bus; An interface circuit characterized in that it is a break circuit that detects whether or not the m voltage is at a specified value, and disconnects the connection between the special skill common bus and the input/output board when it is detected that it is below the specified value υ. achieved by
発明の実施例 J−゛ユ下本発明を実施例に基づいて説明する。Examples of the invention EMBODIMENT OF THE INVENTION The present invention will be explained based on examples below.
87! 2 mlは、本発明の実施例で、図中t3R1
〜BRnはブレーク回路で第1図と同一部材には同一符
号を伺与している。87! 2 ml is an example of the present invention, and t3R1 in the figure
-BRn is a break circuit, and the same members as in FIG. 1 are given the same reference numerals.
本発明におけるブレーク回路BRI〜BRnは、電源ユ
ニットPUの電圧を監視しており、所定の電圧以下であ
る時は、共通バス■3U SとレシーバR2ドライバD
IL間を開放する様にしている。The break circuits BRI to BRn in the present invention monitor the voltage of the power supply unit PU, and when the voltage is below a predetermined voltage, the common bus 3U S and the receiver R2 driver D
I am trying to keep the distance between ILs open.
具体例を第3図に示す。A specific example is shown in FIG.
ブレーク回路は、電圧監視部S−VとリレーRL及び共
通バスBUSとレシーバ、ドライバDR間に接続された
リレー接点rzとから成り、電圧監視部Svは、電源ユ
ニットの電圧が所定の値以上である時リレーI%Lを駆
動しており、所定の値以下に分った時リレーRLの駆動
を停止する。The break circuit consists of a voltage monitoring section S-V, a relay RL, and a relay contact rz connected between the common bus BUS, the receiver, and the driver DR. At a certain time, relay I%L is being driven, and when the value is found to be below a predetermined value, driving of relay RL is stopped.
これにより、リレー接点rlが開放し、共通バスBUS
とレシーバR、ドライバDR間を開放する。This opens relay contact rl and connects the common bus BUS.
, receiver R and driver DR are opened.
第4図に他の具体例を示す。FIG. 4 shows another specific example.
図では、リレーの代わりにトランジスタT Rを用いて
いる。In the figure, a transistor TR is used instead of a relay.
電圧監視部SvI′i、電Wが正′畠である岬1トラン
ジスタTRのベースに電流を流し−1、所定の値以下に
なった時ベース電流をオフにし、]・ランジスタTRを
オフする。The voltage monitoring unit SvI'i causes a current to flow through the base of the cape 1 transistor TR where the voltage W is positive (-1), and turns off the base current when the voltage falls below a predetermined value, and turns off the transistor TR.
トランジスタTRの珂フ間コレクタTRは高インピーダ
ンスになるので共通バスに影すヒを与えない0
発明の効果
以上の如く、本発明によれば、電源ユニットの電圧が所
定値以下の時共通バスとレシーバ、ドライバ間を開放す
るので、複数のユニットの内少なくともいずれか1つが
異常になることによる他のユニットへの影脣をなくすこ
とができる。Since the collector TR between the transistors TR has a high impedance, it does not affect the common bus.0 Effects of the Invention As described above, according to the present invention, when the voltage of the power supply unit is below a predetermined value, the common bus is disconnected. Since the receiver and the driver are opened, it is possible to eliminate the influence on other units due to an abnormality in at least one of the plurality of units.
第1図は従来のインターフェイス回路を示す図、第2図
は本発明のインターフェイス回路を示す図、第3図、第
4図はブレーク回路の具体例を示す図である。
図中[ti 〜BRnけブレーク回路、RLはリレ+、
rlはリレー接点、TRはトランジスタであ、る〇
$1 図
BuS
茸3mFIG. 1 is a diagram showing a conventional interface circuit, FIG. 2 is a diagram showing an interface circuit of the present invention, and FIGS. 3 and 4 are diagrams showing specific examples of break circuits. In the figure, [ti ~ BRn is the break circuit, RL is the relay +,
rl is a relay contact, TR is a transistor, 〇$1 Figure BuS Mushroom 3m
Claims (1)
出する入出力ポートと、該入出力ポートへ電源を供給す
る電源と、該電源電圧が規定値であるか否かを検出し、
規定値以下であることを検出した特技共通バスと入出力
ボート間の接続を断にするブレーク回路を有することを
特徴とするインターフェース回路。An input/output port that receives data from a common bus and sends data to the common bus, a power supply that supplies power to the input/output port, and detects whether the power supply voltage is a specified value,
An interface circuit characterized by having a break circuit that disconnects a special skill common bus and an input/output boat when it is detected that the voltage is below a specified value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58162856A JPS6054061A (en) | 1983-09-05 | 1983-09-05 | Interface circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58162856A JPS6054061A (en) | 1983-09-05 | 1983-09-05 | Interface circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6054061A true JPS6054061A (en) | 1985-03-28 |
Family
ID=15762544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58162856A Pending JPS6054061A (en) | 1983-09-05 | 1983-09-05 | Interface circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6054061A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7610521B2 (en) | 2002-05-14 | 2009-10-27 | Hitachi, Ltd. | Communication control system and method for supervising a failure |
-
1983
- 1983-09-05 JP JP58162856A patent/JPS6054061A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7610521B2 (en) | 2002-05-14 | 2009-10-27 | Hitachi, Ltd. | Communication control system and method for supervising a failure |
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