JPS6052494B2 - signal level display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal level display device that makes it easy to monitor the peak levels of digital signals that are sequentially input.

In some cases, a playback device records and plays back audio signals digitally, that is, in PCM format, instead of recording and playing back analog signals.

In such a case, if an input exceeding the clipping level of the A/D converter is input, the digital outputs will all be ``1'', for example, and faithful recording will become impossible. Therefore, it is necessary to constantly monitor the signal level. Although it is possible to monitor the signal level in the form of an analog signal, it is more convenient to monitor the signal level in the form of a digital signal, which does not require calibration of the meter. When displaying a level using a digital signal, display elements (e.g., light emitting diodes, lamps, etc.) are arranged in level order according to the digit or level of the digital signal, and the signal level is determined by emitting light from the display element corresponding to the level of the digital signal. Configure to detect. However, the retention time and luminescence time of the digital signal are usually several + μ Se
It is extremely short, about c, and difficult to recognize. Generally, in order for the human eye to accurately recognize the presence or absence of light emission, a light emission time of approximately several hundred RrLsec is required. Therefore, it is conceivable to insert a CR time constant circuit or the like to extend the signal applied to the light emitting element for a predetermined period of time. However, the method of extending the light emission holding time using a time constant circuit has the drawbacks of poor response characteristics, the drawback that it is not easy to provide CR time constant circuits with uniform characteristics in the circuits of each light emitting element, and When it is desired to change the holding time in a constant circuit, adjustment must be made for all the time constant circuits, which has the disadvantage that the adjustment is extremely complicated. Also, it would be convenient if the peak value of the signal level could be displayed in a way that could be clearly determined, but no method has yet been proposed that allows such a display to be performed with a simple configuration. do not have. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to be able to display the level before the peak value of a digital signal with little response delay, and to clearly display the peak and subsequent levels. An object of the present invention is to provide a signal level display device that can perform the following with a simple configuration. Structure of the Invention To achieve the above object, the present invention includes a storage circuit that stores three digital signals that are sequentially input at a predetermined sampling period, a storage digital signal stored in the storage circuit, and the predetermined sampling period. a comparison circuit for comparing the level of the digital signal newly inputted in the storage circuit; a table 3 indicator for displaying the level of the storage digital signal stored in the storage circuit; A clear signal corresponding to the comparison output is provided to the storage circuit substantially in synchronization with a comparison output indicating that the new power digital signal is larger than the digital signal, and the comparison output is output from the comparison circuit for a predetermined period of time or more. If the clear signal is not obtained after a while, a clear signal different from the comparison output corresponding clear signal is given to the storage circuit at predetermined time intervals, and the storage circuit is cleared based on the comparison output corresponding clear signal and the other clear signal. a control circuit for controlling the storage circuit to clear the stored digital signal, hold the new power digital signal in place of the stored digital signal, and supply the new power digital signal to the display; This relates to a signal level display device consisting of.

According to the above invention, the following effects can be obtained.

(a) The control circuit generates a comparison output corresponding clear signal based on the comparison output indicating that the new power digital signal obtained from the comparison circuit is larger than the stored digital signal, and this comparison output corresponding clear signal continues for a predetermined period of time or more. and another clear signal which is generated when the clear signal is not obtained. As a result, when the input digital signal changes toward the peak value, a clear signal corresponding to the comparison output is obtained according to the sampling period, indicating a state with little response delay, that is, tracking the actual level change relatively accurately. It becomes possible to display On the other hand, if the level of the input digital signal reaches a peak value and then decreases, the comparison output corresponding clear signal will no longer be generated after reaching the peak value. As a result, since the stored digital signal is not cleared immediately, the peak value display is maintained, making it possible to clearly display the peak value. However, when a predetermined period of time elapses after the comparison output corresponding clear signal disappears, another clear signal is generated at a predetermined time interval (τ). Therefore, level changes after the peak can also be known at predetermined time intervals (τ). Therefore, the peak level and the levels other than the peak level can be displayed using a common display. (b) Memory circuit,
It is possible to change the display form before the peak and the display form after the peak by simply clearing the comparison output corresponding clear signal and another clear signal formed separately from this.

Therefore, the two types of level display described above are possible with a simple circuit configuration. Next, with reference to the drawings, 1 of the present invention
An example will be described.

1A and 1B are circuit diagrams showing a level display device in an apparatus for recording or reproducing an audio stereo signal in PCM according to an embodiment of the present invention. Note that the circuit of FIG. 1A and the circuit of FIG. 1B are 8-Bl. The parts shown are connected to form one circuit. The 12 input terminals provided at the left end of Fig. 1A also ~All input audio signals to A.
This is a terminal into which a linearly encoded digital signal obtained by A-D conversion by a -D converter, that is, a digital signal containing level information of an analog signal is input. The above-mentioned linearly encoded digital signal consists of 12 bits and is produced, for example, as follows. When an analog signal of a certain level is input with reference to 0 dB (for example, the clipping level of an A-D converter or the maximum value of the signal), it is determined whether the 0 dB level is greater than or equal to 112 levels, that is, 1 σB or less. ,
If it is greater than or equal to ゜゜゛, if it is less than ゜゜0゛.

Now, if it is less than 1 αB, then next is the 112 level of 1 αB, i.e. -12 (judging whether it is more than or less than 1 iB, if it is more than -12 dB then ゜゛1゛, if less than ゜゛1゛)゜Suppose it is 0゛.If it is less than -12dB now,
Next, determine the level 112 of -12 dB, that is, whether it is more than or less than -18 dB, and if it is more than -18 dB, it is "1", if it is less than, it is "0". Also, if it is more than -12 dB, then , determine whether it is more than or less than -9JB, that is, between -αB and -12dB, and if it is more than ゜"1
If it is less than 112, it is set as 0.As mentioned above, a 12-bit digital signal is created by repeatedly determining whether it is greater than or equal to 112 or less than 112. The relationship is that the input terminal AO is -72dB
、． a1 is -66dB. ．． a2 is -60dB1a3 is -
54dB. ．． a4 is -48dB. ．． a5 is -42dB.
．． a6 is -36dB1a7 is -3 ＼A8 is -24dB
．． ．． a9 is -18dB1a10 is -12dB, . a11
corresponds to -6dB1.

Although not shown, it has a polarity bit and a parity check bit, making it a 14-bit digital circuit in total. M is a storage circuit or memory, and 3
A 12-bit memory is composed of 4-bit memories M1, m2, and m3.

When this memory M is cleared, the input terminal %~Al
When a 12-bit digital signal is input from 1, it is simultaneously stored. The memory state is maintained until it is cleared, and even if the next input digital signal is generated, the memory content is not rewritten unless it is cleared, and the previous memory content continues to be output. (COm) is a comparison circuit or comparator that digitally compares 12-bit input A and memory output B, and generates a comparison output on line a only when input A is greater than output B, that is, when A>B. It is something to do.

Note that this comparator (COm) also consists of three 4-bit comparators Cl, C2, and C3. (SW) is a switch for switching between the left L channel and right R channel of the stereo signal, and includes three switches Sl, S2, and S.
Consists of 3. A 12-bit digital memory output from the shown left channel memory M is input to this switch (SW), and a 12-bit digital memory output from the right channel memory (not shown) is indicated by R. input to the terminal. It should be noted that the right channel, not shown, is configured in exactly the same way as the left channel. A 50 KHz square wave channel switching signal is applied from terminal 1 to this switch (SW), and when this switching signal is at a low level, the gate of the left channel is turned on, and only the output of the left channel of memory M is connected to the line. 8~Bll
On the other hand, when the switching signal is at a high level, the gate of the right channel is turned on, the gate of the left channel is turned off, and only the memory output of the right channel is sent to the output line B of the switch (SW). - communicated to Bll. Therefore, the output stage of the switch (SW) is shared by both the left and right channels. As a result, the memory output is sent to the display intermittently at 50 KHz, but because of the high repetition rate, the display appears continuous. Control circuit 2 includes three NOR
Gates 3, 4, 5, monostable multivibrator 6,
It consists of a capacitor 7 and a resistor 8 that constitute a differential circuit, and a diode 9 for removing a negative differential signal.
The output of the comparator (COm) and the differential pulse of the trailing edge of the output pulse of the monostable multivibrator 6 are input to the R gate 3, and the NOR gate 3 is input to the NOR gates 4 and 5.
The output of the NOR gate 4 and the 50 KHz channel switching signal applied from the terminal 10 are input, and the output of the NOR gates 4 and 5 is applied as a clear signal to the memory M and as a trigger signal to the monostable multivibrator 6. I'm there.

Incidentally, a capacitor 11 and a variable resistor 12 are connected to the monostable multivibrator 6 for determining its output pulse width. In this control circuit, NOR gate 4,
5 may be one, but in this embodiment, two are used due to the capacity. Line B in the circuit of Figure 1A
.

In the circuit of FIG. 1B connected by -Bll, L is a left channel display section, which is composed of 17 light emitting diodes ~Ll2. Further, R is a right channel display section, which similarly includes 17 light emitting diodes R1 to Rl.
It consists of 2. Light emitting diode LED~Ll2 and B
The arrangement of 1 to Rl2 corresponds to the scale display by DB, and is arranged in the order of the level of the digital signal, that is, in the order of the digits, from -B to αB. Note that below -30dB is not important for level monitoring, so it is αB interval, but from -30dB to 0c1
The intervals between B and B are important for level monitoring, so they are spaced at 3 dB intervals. Further, the suffixes of the light emitting diodes L1 to Lll correspond to the suffixes of the input terminals a1 to All and the lines B1 to Bll. The N, AND gate 13 receives lines 8 to Bll as inputs, and when high level inputs are received on all of them, the output state becomes low level, and is a circuit for approximately detecting (b). It is.

Therefore, when there is a low level output from this NAND gate 13, the 0 dB light emitting diode Ll2 or Rl2 emits light and the signal level is found to be B. NOR gates N1 to Nll. 5 and 1 inverter 11-111.
5 is for causing all the light emitting diodes below the largest digit of the digital signal representing the level to emit light. Each of the above NOR gates N1 to Nll. 5 are respectively connected to the 3 dB detection lines, and are also connected to the adjacent lines via respective inverters 11 to 111.5. Therefore, if a low level output is generated from NAND gate 13, light emitting diode Ll2 or Rl2 emits light, and NOR gate Nll. 5 is given an input and its output is also at a low level, causing the light emitting diode Lll. 5 or Rll. 5 also emits light. In this way, the remaining light emitting diodes L1 to Ll
1 or R1 to Rll also emit light. Three NAND gates 14a, 15a, 16a and two inverters 17a,
18a is for displaying -3dB, and is for NAND
The input of gate 14a is connected to lines BB, B9 and N
The input of AND gate 15a is connected to the output of NAND gate 14a and to line BIO via inverter 17a, and the input of NAND gate 16a is connected to the output of NAND gate 15a and line Bll.

Therefore, when the four lines B8, B8, BIO, and Bll are at a high level, that is, the state of ``1'', the output of the inverter 18a becomes a low level, and the light emitting diode Lll.
or Rll. 5 emits light. Also at least Bll and B
Even when lO is at a high level, the light emitting diode Lll. 5 or Rll. 5 emits light. Also line Bll and line B
8, B9 are at high level, the light emitting diode Lll. 5
or Rll. 5 emits light. NAND gate 14b, 1
5b, 16b and inverters 17b, 18b are distributed in B
The light emitting diode LlO. 5 or RlO. 5 to emit light, and the NAND gates 14c and 15
c, 16c and inverters 17c, 18c are -15c1
The NAND gates 14d, 15d, 16d and inverters 17d, 18d cause the -21 dB light emitting diode L8.5 or R8.5 to emit light, N
AND gates 14e, 15e, 16e and inverter 1
7e and 18e are light emitting diodes L7.5 or R7.5 of -27 dB. Inverter 19 and transistor QL provided in the upper part of FIG. 1B,
QB selectively operates the left channel display section L and the right channel display section R, and displays lines Bl2 to Bl5.
When a 0 KHz channel switching signal is input, transistors QL and QR are turned on and off alternately.

That is, the transistor QR is turned on during the high level period of 50 KHz, and the transistor QL is turned on during the low level period.
Next, the operation of the above-mentioned level display device will be described with reference to a diagram of its principle.

FIG. 2 shows the principle of a circuit for improving the peak level display in FIG. 1A, and is substantially equivalent to FIG. 1A. In the circuit of FIG. 2, for ease of understanding, the NOR gate 3 in FIG. 1A is replaced with an 0R gate 3a, and the
The two NOR gates 4 and 5 are used as a NAND gate 4a. First, when the power is turned on, the monostable multivibrator 6 is triggered by noise and oscillates, and a pulse with a pulse width (τ) is generated from the mutual terminals as shown in FIG. 3f. Of course, the multivibrator 6 may be caused to oscillate by applying a trigger pulse from the 0R gate 3a or the like. The pulse width (τ) is adjusted by a variable resistor 12. Now, comparator (
If no output is generated from 0R gate 3a, a differential pulse is generated as shown in Figure 3b at the trailing edge of the output of pulse width (τ) obtained from the mutual terminal, and this is applied to the 0R gate 3a. The output shown in FIG. 3c is obtained, which is input to the AND gate 4a. On the other hand, from the terminal 10, a 50KHz channel switching signal shown in FIG.
It is input to the D gate 4a, and the switching signal is always input during the period of the output pulse of the 0R gate 3a shown in FIG. 3c. As a result, an AND output of the switching signal and the 0R output is obtained as shown in FIG. 3e, and the signal shown in FIG.
It is given as a clear signal to the monostable multivibrator 6, and also given as a trigger signal to the monostable multivibrator 6. During the period when the comparison output is not generated from the comparator (COm), the monostable multivibrator 6 repeats oscillation with the pulse width (τ), and the memory M is cleared every time τ elapses, and a new input digital signal is stored in the memory M. written. Memory M
A linearly encoded 12-bit digital signal consisting of one word is sent at a predetermined sampling period.

However, unless the stored digital signal in the memory M is cleared by the clear signal shown in FIG. 3e, a new input digital signal is not written and the stored state is maintained. Therefore, if no output is generated from the comparator (COm), the same memory digital output is generated during the holding time (γ), and the same display is maintained on the display section L for the time τ. τ is approximately several hundred Rrl. Since it is set to sec, the display on the display section L by the light emitting diodes L1 to Ll2 can be clearly seen. When the input digital signal of the memory M becomes larger than the output digital signal, a comparison output is generated from the comparator (COm) at t1 as shown in FIG. 3a. As a result, as shown in FIG. 3C, 0 at time t1
An output is also generated from the R gate 3a, and an AND output of the 0R output and the switching signal is generated as shown in FIG. A new input digital signal is written, and the level of the new digital signal is displayed on the display section L. At the same time, a trigger signal is also applied to the monostable multivibrator 6, as shown in FIG. 3f! From the new pulse width (
τ) starts oscillation. If a comparison output is subsequently generated, the oscillation of the pulse width (τ) is of course interrupted, and the oscillation of the pulse width (τ) is restarted. Now, if the input digital signal gradually increases toward the peak value and then gradually decreases, the input digital signal will be larger than the stored digital signal at every sampling period until the peak value is reached, so the comparator ( A comparison output is generated from COm), and a new digital signal is always written into the memory M and displayed on the display L.

Therefore, the display is performed without any response delay. When the peak value is reached from such a display and the level gradually decreases, no output is generated from the comparator (COm), so the peak value of the digital signal is held for, for example, τ time, and the peak value is The level can be clearly determined on the display section L. After τ time, the peak level display is canceled and the digital signal at that point is stored in the memory M.
is written to and held until the next clear signal occurs. The output of the memory M is interrupted by the switch (SW) shown in FIG. In some cases, it can be observed as a continuous display.

To explain this channel switching operation in more detail, during the low level period of the 50KHz square wave signal sent from terminal 1, the left channel signal is sent from the left channel memory M to wires 8 to Bll, while the right channel signal is sent from the left channel memory M to wires 8 to Bll. The signal from the memory (not shown) is cut off. During this period, the transistor QL is turned on, and the light emitting diode of the display section L is energized by the +5 power supply and emits light. At this time, the transistor QR" is off, and the line 8~Bll
The light emitting diode of the display section R does not emit light even if there is a signal. During the period when the channel switching signal is at a high level, the operation is reversed, the memory output of the right channel is transmitted, and the light emitting diode of the display section R emits light. The device is therefore simplified by sharing display control circuitry. FIG. 4 is a principle diagram for explaining the display of intervals, and only the display circuit of B1-B1-αB in FIG. 1B is shown in principle.

j In this circuit, N in Figure 1B is used for ease of understanding.
AND gate 14, NAN instead of AND gate 14a
0R gate 15 instead of D gate 15a and inverter 17a, inverter IVl instead of NAND gate 13,
An inverter I2 is provided in place of NOR gate Nll, and inverter 18a and NOR gate Nll. 5 is omitted. However, the circuit of FIG. 1B and the circuit of FIG. 4 are electrically equivalent. Input terminal A. Since a linearly encoded digital signal is input to -All, the digital signal of the D-B step is sent to the display circuit on lines 8 to Bll. If this is displayed as is, it can only be displayed in 6dB steps. What about the vicinity of αB, which is an extremely important part for monitoring signal levels? Since a rough display of the B step is inconvenient, an intermediate value is displayed. Input terminals 1 to 4 in FIG. 4 correspond to lines B8 to Bll, and input terminal 5 corresponds to the AND output of B6 to Bll, and the larger the number, the higher the level stage of the digital signal. ing. The outputs of the first to fifth level stages are -24, -1 &-
12, -6, and 0 dB, and this output can be displayed without going through an intermediate display circuit as shown in FIG. 1B. However, for example, an intermediate level display between the fourth level stage and the fifth level stage cannot be displayed unless an intermediate display circuit is provided. The output of the intermediate display times is not an exact intermediate value, but is approximately an intermediate value. FIG. 5 shows the state of each part in FIG. 4, and as is clear from this diagram, the light emitting diode Lll. 5 is when a signal enters both the fourth level stage of input terminal 4 and the third level stage of input terminal 3 at the same time, or when the signal enters both the fourth level stage of input terminal 4 and the third level stage of input terminal 2. Light is emitted when signals simultaneously enter the second level stage and the first level stage of the input terminal 1, respectively.

For example, if the digital signal is a signal representing a level of -2 dB, then... By line encoding,
Since it is more than 1 αB of the 0 dB bow corresponding to the maximum value, "1" is input to the input terminal 4 of the line Bll, and the light emitting diode Lll, which indicates that it is more than -σB, emits light.
−． Since the level of 2c1B is even higher than the level of 112 of 1σB, there is an input of ゜"1゛ on the line BIO corresponding to -12 dB, that is, input terminal 4, and the 0R gate 15
Since an output is generated from the light emitting diode Lll. and two inputs are input to the N,AND gate 16. 5 emits light, -3dB
- Let them know that you are at a higher level. Therefore, in the conventional circuit, the -6 dB light emitting diode only emitted light at the maximum level even for a -2 dB signal, whereas in this device, the -6 dB light emitting diode emitted light at the maximum level for a -2 dB signal. It emits light and allows you to know the level accurately. Now, the light emitting diode Lll. I mentioned the display in 5.
Light emitting diode LlO. 5, L9.5, L8.5, L7
．． 5 also emits light based on exactly the same principle.

That is, an intermediate level display is provided by providing a logic circuit that generates a display output when receiving signals from at least two or more adjacent lower level output lines. As a result, between -30dB and 0ciB, 3d
B. You can know the level by the interval. As can be understood from the explanation so far, according to the display device of this embodiment, the level can be displayed without any response delay until the peak value is reached, and once the peak value is reached, no larger peaks will appear. As long as the peak value is held in the memory M for a predetermined time, that is, τ, the display on the display section L or R is also substantially τ.
Since the time is maintained, peak levels can be monitored very easily.

Further, since the control circuit 2 is provided in common to each bit circuit of the digital signal, the display extension time by the light emitting diodes can be easily adjusted.

In addition, a switch (SW) is provided for channel switching.
This is driven at a high frequency to alternately send out left channel signals and right channel signals, and display section LI::. R
Since these are switched and driven by transistors QL and QR,
Both channels can be displayed simultaneously using the same display drive circuit.

Therefore, the circuit is extremely simplified. Furthermore, since an intermediate display circuit is provided, the level can be displayed accurately. Moreover, an intermediate level display can be achieved with an extremely simple circuit configuration.

Furthermore, when the light emitting diode with the highest digit of the digital signal emits light, the light emitting diodes with the lower digits also emit light, so analog display can be made in a state that is extremely easy to monitor.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and can be further modified.

For example, a display circuit near 0 dB is ANDed as shown in Figure 6.
It may be configured with gates 20 to 24, inverters 25 to 31, and light emitting diodes Llla to Llle, Lll and Ll2, and display at 1 dB intervals. It is also applicable to the case of only one channel. It is also applicable to level display of digital signals other than audio signals. Furthermore, there is no problem in increasing or decreasing the intermediate level display range. Further, the logic circuits of each part may have a configuration other than that of the embodiment. Further, a display element such as a lamp may be used instead of a light emitting diode.

[Brief explanation of drawings]

1A and 1B are circuit diagrams showing a signal level display device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the principle of a part of FIG. 1A, and FIG. 3 is a circuit diagram showing a part of FIG. Figure 4 is a circuit diagram showing the principle of a part of Figure 1B, Figure 5 is a waveform diagram of each part of
The figure is an explanatory diagram showing the operation of FIG. 4, and FIG. 6 is a circuit diagram showing a modification of the display circuit. In the symbols used in the drawings, M is memory, (
COm) is a comparator, L and R are display parts, and Ll2
, Rl to Rl2 are light emitting diodes, 2 is a control circuit, 3,
4 and 5 are NOR gates, 6 is a monostable multivibrator, 13 is a NAND gate, 14a, 15a, and 16a are N
It is an AND gate.

Claims (1)

[Scope of Claims] 1. A storage circuit that stores digital signals that are sequentially input at a predetermined sampling period, and a storage digital signal that is stored in the storage circuit and a new input digital signal that is newly input at the predetermined sampling period. a comparison circuit for comparing the signals, an indicator for displaying the level of the stored digital signal stored in the storage circuit, and the new input digital signal being larger than the stored digital signal obtained from the comparison circuit. A clear signal corresponding to the comparison output is applied to the storage circuit substantially in synchronization with a comparison output indicating the comparison output, and when the comparison output is not obtained from the comparison circuit for a predetermined period of time or more, the clear signal corresponding to the comparison output is applied to the memory circuit. Applying a clear signal different from the signal to the memory circuit at predetermined time intervals,
The stored digital signal of the storage circuit is cleared based on the comparison output corresponding clear signal and the other clear signal, and the new input digital signal is held in place of the stored digital signal, and this new input digital signal is used as the new input digital signal. a control circuit for controlling said storage circuit to supply a signal level display device. 2. The signal level display device according to claim 1, wherein the storage circuit is a memory capable of simultaneously storing all bits of a linearly encoded digital signal and simultaneously reading previous bits. 3. The signal level display device according to claim 1, wherein the indicator is a plurality of light emitting diodes arranged in order of the level of the digital signal. 4. The control circuit inputs the monostable multivibrator that generates the pulse of the predetermined time, the comparison output obtained from the comparison circuit, and the differential output of the trailing edge of the pulse of the monostable multivibrator, and outputs the output pulse. Claims 1, 2, or 3 further comprising: a logic circuit that provides a clear signal to the memory circuit and a trigger signal to the monostable multivibrator;
Signal level display device as described in section.