JPS6052144A - Reception data speed discriminating circuit - Google Patents

Abstract

PURPOSE:To discriminate the transmission speed in a short time at a receiver side without giving any trouble to the system side by using a simple circuit to discriminate automatically a data transmission speed from an input data signal. CONSTITUTION:Two kinds of data a, b having different transmission speeds are inputted from a reception data input terminal 1 of a reception data discriminating circuit and an edge detection circuit E of a clock regenerating circuit B detects an edge of each data. The number of detected edges is counted by a 3- bit binary counter C. The counter C is reset by a reset pulse (e) from a timer input terminal 3. Whether or not a specific logical value is set to a specific digit in the counter C is supervised in relation to the reset timing and the count capacity of the counter C. Further, the transmission speed of the pulse series of the reception data a, b is discriminated in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a speed determination circuit that determines the speed of received data in a data receiving device.

[Prior art and its problems]

Conventionally, when switching a receiving device connected to a transmission system that transmits data at a transmission speed to another transmission system with a different transmission speed to receive data,
Prior to switching, the system side notifies the receiving device of the data transmission speed of the next system to be connected, and the receiving device decodes it to prepare for the subsequent transmission speed switching. Ta. Therefore, it is necessary to prepare special operating procedures for switching both the systems before and after switching, which has the disadvantage of complicating system operation.

Conventionally, when the transmission speed is switched, the receiving device sets the device for each of the multiple predicted transmission speeds, attempts to receive data, and selects the transmission speed when significant data is received. There is also a method of determining the true transmission speed at that point in time, but with this method, it takes time to determine the transmission speed when there are many predicted transmission speeds, and the receiving device The disadvantage is that it takes too much time for data to be received correctly.

[Purpose of the invention]

The present invention has been made in order to eliminate the drawbacks of the prior art as described above, and therefore, an object of the present invention is to enable the switching of the receiving device side without bothering the system side when the transmission speed is changed. It is an object of the present invention to provide a reception data rate determination circuit that allows a transmission rate to be determined easily in a short time.

[Key points of the invention]

The received data rate determination circuit according to the present invention includes an edge detection circuit that receives a series of received data pulses as input, detects and outputs the edges of each pulse constituting the series, and a counter circuit that counts the number of detected edges. and a reset circuit that periodically resets the counting circuit at a certain timing, and a specific logical value is set at a specific digit in the counting circuit in relation to the reset timing in the reset circuit and the counting capacity of the counting circuit. The present invention is characterized in that the transmission rate of the received data pulse sequence is determined by monitoring whether or not the received data pulse sequence is the same.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a reception data input terminal, 2 is a phase correction layer high summing clock terminal, 3 is a timer input terminal,
4 is a transmission speed determination output terminal (connected to the most significant digit MSH of the binary counter C). Further, B is a clock regeneration circuit for reading received data in the receiving device, E is an input data pulse edge detection circuit, and D is a D
-Flip-flop, EX is exclusive OR circuit, C is 3
This is Pitt's binary counter.

FIG. 2 is a time chart of various signals in the circuit of FIG. 1.

The circuit operation will be explained with reference to FIGS. 1 and 2.

In this example, two clocks with different clock periods (that is, different transmission speeds) as shown in FIGS. 2(a) and (b) are used.
The type of data shall be determined.

Note that in Figure 2 (a) and (b), a clock is shown as representing data, but the data that can be extracted from the clock is the data per unit of time that is comparable to the transmission speed. Since the number of pulse edges of a pulse exists, there is no loss of generality in determining the data transmission rate even if the clock is referred to in place of data.

Now, when the input data signal (a) or (b) is input to the terminal 1, an edge (differential output) as shown in (C) or (d) is obtained at the output of the edge detection circuit E. This is input to the 6-bit counter CK, but as shown in (e), a reset pulse is sent to the terminal 3 by a timer (not shown).
By inputting data from the input data signal and resetting the counter C, an output like (f) or (g) is obtained at the transmission rate judgment output terminal 4, and whether the input data signal is (a) or (b) is obtained.
).

Supplement the explanation. In this case, binary counter C has a capacity of 6 bits, so the most significant digit MSB is a logic 1.
In order for this to occur, [001] or more pulses in binary must be input before the counter is reset. Since (001) is a decimal number of 4, if 4 and more pulses are input to the counter C before it is reset, the output can be seen at the decision output terminal 4.

As is clear from FIG. 2, when four edges (d) are input, the output of the most significant digit MSB of the counter C (output f of the judgment output terminal 40) rises, and then comes from the timer input terminal 6. The counter C is reset by the reset pulse (e), and the output of MSI3 also falls.

On the other hand, since the number of edges (C) is small, the MSB output never rises, so input terminal 1
Whether the data input in is (a) or (b) is,! This can be easily determined by monitoring the output of the IJ constant output terminal 4.

Here, the high sampling clock input from terminal 2 needs to have a frequency sufficiently higher than the transmission rate of input data. Also, the reset pulse interval may vary due to noise.
Even if the edge pulse pseudo increases or decreases, the output from counter C (in this case, the most significant digit MSB of the counter) is (f).
Or, as in (g), it must be set in such a way that it can be distinguished.

In this example, it has been explained that two types of transmission speeds are to be determined, but even if it is desired to judge many types of transmission speeds, the counting capacity of counter C is increased,
This can be achieved by adding a simple logic circuit after the counter C if the reset pulse intervals are set appropriately.

Note that in this embodiment, the edge detection circuit E is included in a clock recovery circuit used for regenerating a lock required for reading received data from received data on the receiving device side. However, the present invention is not limited to this, and it goes without saying that they may be prepared independently.

〔Effect of the invention〕

As explained above, according to the present invention, the data transmission speed can be automatically determined from the input data signal using a simple circuit. In a mobile radio device where communication systems are mixed in a service area and can access any system, when it becomes necessary to select the system to access as the radio device moves within the area, the input data By determining the data transmission speed from the column, it is possible to immediately and automatically determine that the system has been switched and deal with the system selection, and in each system, the transfer heat #! There is no need to modify the operating procedures of the conventional system in order to switch between systems in mobile radio equipment (and there are also advantages such as no delay time required for switching between systems in mobile radio equipment). .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart of various signals in the circuit of FIG. 1. Description of symbols 1...Input data terminal, 2...High sample printer clock terminal for phase correction, 3. Hit/timer input terminal, 4...Transmission speed judgment output terminal, B. Hitting.
Clock G main circuit (bit synchronization circuit), E/track/edge detection circuit, D...D type flip-flop, EX
...Exclusive OR circuit, C...6-bit binary counter, Agent: Patent Attorney Akio Namiki Agent: Patent Attorney Kiyoshi Matsuzaki Continuation of page 1 @ Inventor: Medium 1 ) Akira Shi Yokosuka Funugi 1cho Communication Research Institute

Claims (1)

[Claims] 1) An edge detection circuit that receives a series of received data pulses, detects and outputs the edges of each pulse constituting the series, a counting circuit that counts the number of detected edges, and performs the counting at a fixed timing. and a reset circuit that periodically resets the circuit, and by monitoring whether or not a specific logic value stands at a specific digit in the counting circuit in relation to the reset timing in the reset circuit and the counting capacity of the counting circuit. , a received data rate determination circuit, characterized in that the received data rate determination circuit is configured to determine the transmission rate of the received data sequence.