JPS6052039A - Changing method into chip of semiconductor wafer - Google Patents
Changing method into chip of semiconductor waferInfo
- Publication number
- JPS6052039A JPS6052039A JP58159353A JP15935383A JPS6052039A JP S6052039 A JPS6052039 A JP S6052039A JP 58159353 A JP58159353 A JP 58159353A JP 15935383 A JP15935383 A JP 15935383A JP S6052039 A JPS6052039 A JP S6052039A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- conductive
- chip
- grounded
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Adhesive Tapes (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体ウェハを分割し、単一素子(以下チップ
と称す)化する際、回路の静電破壊を防止するために再
剥離性の導電性積層シートを使用することt特徴とする
半導体つェノ\のチップ化方法に関する。[Detailed Description of the Invention] The present invention uses a removable conductive laminated sheet to prevent electrostatic damage to circuits when dividing a semiconductor wafer into single devices (hereinafter referred to as chips). This invention relates to a method of making semiconductor chips into chips, which is characterized by the following.
一般に半導体製品の#!造過栓において梁構回路(以下
ICと略)等のチップは、シリコン単結晶等よりなる円
板上に格子状の多数の回路パターン2同時に形成したウ
ェハ忙パターン毎に切断することによV得ら扛ている0
従来より一般にウェハ切断に際しては、切断後のチップ
飛散防止のために汎用の積層シート上に固定しダイミン
グ・ンウ等で切断しているが1回転刃の回転数が数千〜
数万RPMと尚速であるため多重の静電気が発生しウェ
ア)内に蓄積される傾向にある0この為微細な回路パタ
ーンkljするIC等の場合には、導体間などでの絶縁
破壊を起し易く特にMO5型半導体ではこの危険性が太
きい。# of semiconductor products in general! Chips such as beam-structured circuits (hereinafter abbreviated as ICs) in overfill plugs are produced by cutting a wafer into multiple circuit patterns that are simultaneously formed in a lattice-like manner on a disk made of silicon single crystal, etc. Conventionally, when cutting wafers, in order to prevent chips from scattering after cutting, wafers are fixed on a general-purpose laminated sheet and cut using a dimming machine, etc., but the number of rotations of the blade per rotation is several thousand. ~
Because the speed is tens of thousands of RPM, multiple static electricity is generated and tends to accumulate in the wear.For this reason, in the case of ICs with minute circuit patterns, dielectric breakdown may occur between conductors. This danger is especially serious in MO5 type semiconductors.
従って、か\る半導体の場合vcは積増シートr使用せ
ずにアースされ7t4体上にウェア1を固定し、飛散防
止の為に切断tウェハの表鳩の一部分にとどめ(ハーフ
カットと称す)この状態で積層シートに貼付けて、曲げ
破断じチップ化しているのが現状である。Therefore, in the case of such a semiconductor, vc is grounded without using the stacking sheet r, and the ware 1 is fixed on the 7t4 body, and in order to prevent scattering, it is limited to a part of the front surface of the cut wafer (referred to as half-cut). ) At present, they are attached to a laminated sheet in this state and then bent and broken to form chips.
し刀・しながら力為\る方法でに曲げ破断が厚み方向に
i!線的に進行せず、テップ端面の破断線が回路内にも
及びチップ寸法の精度不良を生じる欠点があった。The bending breakage occurs in the thickness direction when using force while using a sword. There is a drawback that the chip does not progress linearly, and the broken line on the tip end surface extends into the circuit, resulting in poor precision in chip dimensions.
このチップ寸法精度r向上させ、かつICの静電破壊會
防止する方法として、ウェハに4電性を付与させた状態
でウェハの厚み方向に全層切断(フルカットと称す)す
る試みもなされている。As a method to improve this chip dimensional accuracy and prevent electrostatic damage to ICs, attempts have been made to cut the entire thickness of the wafer in the thickness direction (referred to as full cut) while imparting tetraelectricity to the wafer. There is.
そのひとつの方法として、一般の絶縁性粘着シート上に
つ2ハを固定し界面活性剤寺の添加により導電性tも7
tぜたイオン水を噴霧することによって、フルカットす
る方法があるが不純物イオンを他匿にきらう牛導体つェ
八にあっては、水にイオン性を付与する界面活性剤の選
択に自ずから限!建があり、導電性も充分に得られない
ことから顕著な効果は侍られていない。One method is to fix T2 on a general insulating adhesive sheet and add a surfactant to increase the conductivity T to 7.
There is a way to completely cut the water by spraying it with ionized water, but for cattle conductors who do not want to hide impurity ions, there is a natural limitation in the selection of surfactants that impart ionicity to water. ! However, it has not been shown to have any significant effects because it has a high structure and does not provide sufficient conductivity.
′1次他の試みとして、ウェハr4電性接盾剤および導
電性粘着シート等の導電性基材で固定しフルカットする
方法もめる。'1st Another attempt is to fix the wafer with a conductive base material such as a conductive adhesive and a conductive adhesive sheet and then perform a full cut.
しかしながら従来の41i性接宥剤および導電性粘着シ
ートは永久接層を目的とするものでめり、木用途[1M
1i用した場合、次の欠点t1する(すなわち、ウェハ
の切助工程終了俊に導電性接沼剤および粘着シート面か
らチップン剥瀦することができない。また強制的に剥離
妊ぜ得ても、接着剤および粘漸炸jがチップ面に移層し
。However, conventional 41i adhesives and conductive adhesive sheets are intended for permanent adhesion, and are used for wood [1M
When using 1i, the following drawback t1 (i.e., it is not possible to remove the chips from the conductive wetting agent and the adhesive sheet surface immediately after the wafer cutting process is completed.Also, even if it is forcibly removed, Adhesive and viscous powder are transferred to the chip surface.
汚染葡極度vc嫌う半導体用としては通用でさないこと
である。This means that it cannot be used for semiconductor applications, which are extremely sensitive to contaminated VC.
一般の導電性粘着シート類においては、4電性と粘着性
を併せて付与するためにs E’S剤の凝集カケ低下さ
せ可能な〃・き゛ジ柔〃・〈シており貼付俊に再剥離す
ること筐で考慮していない。In general conductive adhesive sheets, in order to provide both 4-electroconductivity and adhesiveness, there are adhesives that can reduce agglomeration and breakage of the S E'S agent. Peeling is not considered in the casing.
また剥離後のチップ面に汚染があると、次工程でチップ
r基板土に固定する除接層性が不十分であったり、Au
Si共晶接合の場合にはチップ内部に汚染が浸透し回路
不良〒生じる欠点rもつ。In addition, if there is contamination on the chip surface after peeling, the removal layer that fixes the chip to the substrate soil in the next process may be insufficient, or the Au
In the case of Si eutectic bonding, there is a disadvantage that contamination penetrates into the inside of the chip, resulting in circuit failure.
本発明は、か\る状況に鑑みなされたものである。すな
わち不発明は、ウェハに91防しテップ化する除にウヱ
ハ叉持体として、チップに対して再剥離性忙Mする尋電
性粘瘤シートヶ使用することt特徴とするウェハのチッ
プ化方法に関するものである0
さらに絆しぐに、再剥離性の導電性粘着シートの特徴を
活かしたもので、ウェハt4電性粘看シートに貼付けて
切断することにより、該シートの導電性により切断時に
ウェハに発生する静電気の除去を可能とし、併せて導電
性粘着シートの再剥離性により切断後のチップ汚染のな
いチップ北方f、勿可能とするものであり、ウェハ2チ
ツプ化する際に大巾な不良率の低減荀可能にするもので
ある。The present invention was made in view of the above situation. That is, the non-invention relates to a method of converting a wafer into chips, which is characterized in that, in addition to forming a 91-proof tip on the wafer, an electrolytic viscous sheet, which is removable to the chips, is used as a wafer holding member. Moreover, it takes advantage of the characteristics of a removable conductive adhesive sheet, and by pasting it on a wafer T4 conductive adhesive sheet and cutting it, the conductivity of the sheet allows it to be attached to the wafer during cutting. This makes it possible to remove the static electricity that is generated, and at the same time, due to the removability of the conductive adhesive sheet, it is possible to cut the chips without contaminating the chips after cutting, and to prevent large defects when converting the wafer into two chips. It is possible to reduce the rate.
本発明に使用される導電性粘着シートとは、カーボン、
金属微粉末のような導電性光槙剤を分散させた粘着剤t
1金kA箔やプラスチックフィルム中に切断時にウェハ
に発生した静電気tアースできるS造kNL、ウェハの
厚み方向に沿っ才鉛直方向に最短距離でアースできる構
成が有利であるが、ウェハの白層方向にアースできる構
成でありても良い。The conductive adhesive sheet used in the present invention includes carbon,
Adhesive t in which conductive light-emitting agent such as fine metal powder is dispersed
Static electricity generated on the wafer during cutting in 1-gold kA foil or plastic film can be grounded.It is advantageous to have a structure that can be grounded along the thickness direction of the wafer and in the vertical direction at the shortest possible distance. The configuration may be such that it can be grounded to.
粘着層の厚め方向の電気抵抗(以下貫層抵抗)は104
Ω/−以下、好ましくrX10’0/−以下5−
が7筐しく、粘着特性としては、以下に述べる再剥離性
VWするものが良い。丁なわち本発明における再剥離性
とは、粘着シートにウヱハ〒何らかの方法で貼付けるこ
とが可能であり、切断時においてもウェハは積層Ntn
vc督層し、切断終了後に粘溜剤向から適当な手段によ
りチップが剥離可能な粘溜力忙有し、さらにチップ面に
積層刑移盾などの汚染r残さないものτい9゜適正な粘
着力に、チップサイズにより異なるために一概には規定
できないが1通常50〜600g/19fl1m(JI
S C−2107による粘増力)程度が使用可能である
。30 g/ 19mm以下では、切断時における密層
が充分でなくウェハあるいはチップが飛散し易(、60
0g/19mm以上で−は、切断終了後におけるチップ
の剥離が困JIIKなる。The electrical resistance in the thicker direction of the adhesive layer (hereinafter referred to as translayer resistance) is 104
Ω/- or less, preferably rX10'0/- or less 5-, and the adhesion property is preferably one that exhibits the removability VW described below. In other words, removability in the present invention means that the wafer can be attached to the adhesive sheet by some method, and even when cutting, the wafer is not laminated Ntn.
VC layer, and after cutting, apply a viscosity force that allows the chip to be peeled off by an appropriate means from the viscosity agent, and furthermore, do not leave any contamination such as lamination transfer on the chip surface. Adhesive strength cannot be defined unconditionally because it varies depending on the chip size, but it is usually 50 to 600 g/19 fl 1 m (JI
The viscosity increasing force by S C-2107) can be used. If the thickness is less than 30 g/19 mm, the dense layer during cutting will not be sufficient and the wafer or chips will easily scatter (60 g/19 mm or less).
If it is 0 g/19 mm or more, it becomes difficult to peel off the chip after cutting.
再剥離性忙付与する手段としては積層刑τ架橋すること
によって達成され、このための架橋手段としては、粘着
剤に官能基としてカルボキシル基、水酸基、アミン基%
酸アミド基等tM6−
するモノマーkill独るるいは畑合して共厘合させる
か、あるいはこれら官能基tもつ、たとえばポリエステ
ル樹脂やフェノール樹脂等tブレンドしイソシアネート
基、メチロール基、アルキルエーテル化メチロール基咎
葡有する架橋剤によって架橋させるのが一般的である。As a means of imparting removability, this is achieved by crosslinking the lamination process, and the crosslinking means for this purpose includes adding carboxyl groups, hydroxyl groups, and amine groups as functional groups to the adhesive.
Monomers with tM6- such as acid amide groups can be co-combined independently or in combination, or they can be blended with monomers having these functional groups, such as polyester resins and phenol resins, to form isocyanate groups, methylol groups, alkyl etherified methylols. Crosslinking is generally carried out using a crosslinking agent containing a base material.
また、天然ゴム等にあっては、艮(知られている硫黄架
橋、樹脂架橋等によっても艮い。これら架橋手段音用い
る除、金属石ケン、酸、塩化スズ等の触媒τ併用するこ
とは反応速度が尚することη為ら効果的である。In addition, in the case of natural rubber, etc., it is also possible to use sulfur cross-linking, resin cross-linking, etc., which are known. It is effective because the reaction rate is very high.
こ扛ら粘涜削中VCは、心安に応じて積層付与1#I4
.可塑剤等の枯盾性―整剤を用いることも可能である。The VC that is being cut is laminated according to your peace of mind 1#I4
.. It is also possible to use a shielding agent such as a plasticizer.
貼付の際、心安な積層力を得る刀広として、たとえば加
圧、加熱、溶剤等による積層血の活性化等の手段〒11
1独あるいは複合して用いることもできる。When pasting, as a blade to obtain safe lamination strength, for example, means such as activation of laminated blood by pressurization, heating, solvent, etc.〒11
It can be used alone or in combination.
切断時における静電除去の為のアースの*す方としては
、たとえば第1図に示すように、アース線4により接地
された金属製固定盤5に設けられた小孔(図示せず)か
ら真空吸引によりウェハ6ケ貼付けた4電性粘看シート
3’に固定する。あるいは碑電性積層シートの基材2ま
たは粘着剤1の単独もしくけ両者の周囲忙接地されπ導
電性フレームで核う方法などがある。この場合の代表例
ケ第2図〜第4図に俣弐図で示した。For example, as shown in Fig. 1, the grounding method for removing static electricity during cutting is through a small hole (not shown) provided in a metal fixed platen 5 that is grounded by a grounding wire 4. It is fixed to the 4-electroconductive adhesive sheet 3' on which six wafers are pasted by vacuum suction. Alternatively, there is a method in which the base material 2 of the electrically conductive laminated sheet or the adhesive 1 is used alone or the surroundings of both are grounded and a π conductive frame is used. Typical examples of this case are shown in Figs.
第2図は、絶縁性基材8上にウェハ6を貼付けπ4電性
粘溜シート3の周#15ケ導電性フレーム7で穆い、4
電性フレーム7に7−スW14により接地された金属製
固定盤5を介してアースされる。第6図においては、4
電性フレーム7は導電性基材2から直接アース#4によ
り接地きれる。第4図はアース線4によ!ll接地きれ
た導電性フレーム7’?!電性粘層剤1に貼付けてアー
スtとる場合である。第2図〜第4図においては、4電
性フレーム7を用いずに直接アース線4を導電性基材2
あるいa導電性積層剤1から取出すことも可能であり導
電性フレーム7は金W4製が代表的であるが、第5図に
示すように4電性粘増シート3忙固定盤5にアースの取
れるよう留意して貼付けても良い。In FIG. 2, a wafer 6 is pasted on an insulating base material 8, a circumference #15 of a π4 conductive sticky sheet 3 is covered with a conductive frame 7, and a 4
The electric frame 7 is grounded via a metal fixed platen 5 which is grounded by a 7-seat W14. In Figure 6, 4
The conductive frame 7 can be directly grounded from the conductive base material 2 by the ground #4. Figure 4 is based on ground wire 4! ll Grounded conductive frame 7'? ! This is a case where it is attached to the electric adhesive 1 to provide a ground connection. In FIGS. 2 to 4, the ground wire 4 is directly connected to the conductive base material 2 without using the 4-conductor frame 7.
Alternatively, it is also possible to take it out from the conductive laminate 1, and the conductive frame 7 is typically made of gold W4, but as shown in FIG. You may attach it with care so that it can be removed.
ウェハ切断法に関しては、ダイヤモンド等の非常に薄い
刃r高速で回転させて切断するダイシングソウによる方
法tにじめとして、一般的な牛導体ウェハの切断に用い
られる装置、方法が使用できる。As for the wafer cutting method, devices and methods commonly used for cutting conductor wafers can be used, such as a method using a dicing saw that cuts by rotating a very thin diamond blade at high speed.
なお不発明はフルカットの場合rc%vc有利でめるが
、ハーフカットにおいてもM効に通用できる。It should be noted that the rc%vc is advantageous in the case of a full cut, but it can also be applied to the M effect in a half cut.
以下実施例でg−1=細な説明留付なう。In the following examples, g-1 = detailed explanation will be attached.
100部、積層付与剤としてポリテルペン樹脂(融点1
00℃)50部、架橋剤として硫黄粉末4部からなる粘
着剤組成物50亘重%と銀粉(■徳力製、曲品名シルベ
ストTCG−1) 70ムi1%よりなる41#L性粘
看剤組成物tトルエンで希釈し固形分50%の粘yfl
剤浴液を得た。100 parts, polyterpene resin (melting point 1
A 41#L adhesive composition consisting of 50 parts by weight of 50 parts of sulfur powder as a crosslinking agent and 1% of silver powder (trade name: Silvest TCG-1, manufactured by Tokuriki Co., Ltd.). Composition t Viscous 50% solids diluted with toluene
A drug bath solution was obtained.
9−
この粘着剤溶液7厚さ50μのアルミ箔にロールコータ
−により塗布乾燥し、厚さ20μの枯看層’kNする積
層シートtえた0この積層シートの厚み方向の貫層抵抗
は101Ω/afであった。この積層シートにバイポー
ラ型の集積回路を形成せしめた75φのウェハ紫ゴムロ
ールにより2kg/cIIPの圧力″′r:索子佃が露
出するように貼付けた。この時のウェハに対する枯虐力
は80 g/ 19n+m″′Cあッ7m□ (J I
S C−21t17による該ウェハ面に対する粘眉力
)
第5図に示すように、ウェハ6オ貼付けた導電性粘層シ
ー)kアース@4Vcより接地しに金属製固定盤5に設
けられた小孔から負空吸引により固定すると共に、さら
に導電性積層シートの粘着剤1が接するようにウェハ6
の周囲を不笑施例で得た4m性粘層シート5F用いて固
定した。すなわちウェハ6で発注し7+:静電気は導電
性の粘着剤1および基材2τ経て金pA製li!I′I
冗盤5に至りアースされる1r#成とした。9- This adhesive solution was applied to aluminum foil with a thickness of 50μ by a roll coater, dried, and a laminated sheet with a 20μ thick layer was formed.The translayer resistance in the thickness direction of this laminated sheet was 101Ω/ It was af. A 75φ wafer on which a bipolar integrated circuit was formed on this laminated sheet was attached using a purple rubber roll at a pressure of 2 kg/cIIP so that the wafer was exposed. At this time, the crushing force on the wafer was 80 g. / 19n+m'''C 7m□ (J I
S The wafer 6 is fixed by negative air suction through the hole, and the wafer 6 is placed so that the adhesive 1 of the conductive laminated sheet is in contact with the wafer 6.
The periphery of the sheet was fixed using a 4m adhesive sheet 5F obtained in the Fusho Example. That is, order wafer 6 and 7+: Static electricity is made of gold pA through conductive adhesive 1 and base material 2τ! I'I
It was configured as 1r#, which is connected to redundant board 5 and grounded.
回転数30.OOORPMでダイシングソウに10−
よりウェハ厚み方向にフルカットして、5mm角のバイ
ポーラ型ICチップケ得た。この時、切断時におけるチ
ップ飛散もな(良好にウェハtチップ化することが可能
であっπ0
得られたチップは、導電性積層シートからいずれも簡J
JiLVC剥離することが可能でるり、積層シートから
剥離したチップ面紫顕微鏡で観察したところ、粘着剤の
移層等はみられなかった。Rotation speed 30. The wafer was fully cut in the thickness direction using a dicing saw using OOORPM to obtain 5 mm square bipolar type IC chips. At this time, there is no chip scattering during cutting (it is possible to successfully convert the wafer into t-chips).
JiLVC was able to be peeled off, and when the surface of the chip peeled from the laminated sheet was observed under a purple microscope, no layer shift of the adhesive was observed.
またこのチップを検査した結果、静電破壊不良率は0%
であり、チップサイズの不良もフルカットがh]nヒと
なった為皆無であった。Also, as a result of testing this chip, the failure rate due to electrostatic damage was 0%.
There were no chip size defects as the full cut was h]nhi.
実施例2〜4および比較例−1〜2
2s電性カーボンブラツク(電気化学工業峰糺商品名デ
ンカブラック)の分散tVO〜40重童%と変化式せて
、ニーダ−によりアクリル系粘着剤OiL亜合成■製5
曲品名アロンS−1511)中に分散せしめた。この数
槓の粘着剤にカーボンブラックの金型によV電気抵抗が
異なる。Examples 2 to 4 and Comparative Examples 1 to 2 The dispersion tVO of 2s conductive carbon black (DENKA BLACK, trade name of Denki Kagaku Kogyo Hoten) was changed to 40%, and the acrylic pressure-sensitive adhesive OiL was prepared using a kneader. Made of subsynthetic material 5
It was dispersed in Aron S-1511). The electrical resistance of the adhesive varies depending on the carbon black mold.
上記粘着剤100皿型部に、架橋剤(日本ポリウレタン
工業■裂、商品名コロネートL)3M童部γ固形分比で
各々配合した粘着剤葡碑電性PVCシート(理研ビニル
■製、商品名スーパーオーム100μ)上にロールコー
タにより塗布した後% 120℃−2分乾珠し粘氷剤の
厚み10μmの粘湧シーIf得た。A cross-linking agent (made by Nippon Polyurethane Kogyo, trade name: Coronate L) was added to each of the 100 trays of the above adhesive at a solid content ratio of 3M Dobe gamma. After coating with a roll coater on Super Ohm (100 .mu.m), the ice was dried at 120.degree. C. for 2 minutes to obtain a viscous ice sheet If having a thickness of 10 .mu.m.
比較?1J−1はカーボンブラックの光佃がなぐ粘着剤
に非専m性であり、比較例−2においては実施例−5と
ldl様であるが架橋剤紫使用しない粘渭剤配合とした
。Comparison? 1J-1 is non-exclusive to the adhesive used by carbon black Mitsutsukuda, and Comparative Example 2 was formulated with a sticky agent similar to Example 5 and ldl, but without using the crosslinking agent.
以−ヒよりなる4電性枯沼シ一ト面に、チップサイズ5
II1m角のC−MO3lc!回路忙形bz−cしめた
100φのウェハにゴムロールにより貼付けた。Chip size 5 is placed on the surface of the four-electrode Karenuma sheet consisting
II1m square C-MO3lc! It was attached to a 100φ wafer with a circuit pattern BZ-C using a rubber roll.
この場合、実施例−4においては積増性が不足した為に
ウェハに100℃に加熱し貼付を可能にした0ウエハを
貼付けた粘盾シート紫、4電シートの下側より真空吸引
して、4電性基材と接、tt!!された金J’Ji盤r
密看さゼてアースtとり。In this case, in Example-4, because the stackability was insufficient, the wafer was heated to 100°C and the 0 wafer was pasted, and the adhesive sheet purple and the 4-density sheet were vacuum-sucked from the bottom. , in contact with the four-electrode substrate, tt! ! Kim J'Ji board r
I'm secretly watching and I'm off to the ground.
ダイシングソウで回転数10.DOORPMでウェハr
厚み方向にフルカットしτ、5mmqのC−MOSチッ
プf得た。RPM 10 with a dicing saw. Wafer r with DOORPM
A C-MOS chip f of τ and 5 mmq was obtained by full cutting in the thickness direction.
このチップについて実施例−1と同様に粘宥シート〃1
らのテップ剥離性およびチップ面の汚染、静電破壊不良
率?測定した。これらの結果を第1表に示す。Regarding this chip, as in Example-1, sticky sheet 〃1
What about the chip peelability, chip surface contamination, and electrostatic damage failure rate? It was measured. These results are shown in Table 1.
第1表
ト
二E
て
15−
これらの結果、実施例2〜4の4電処Lfi+に施した
粘着剤においては静電破壊不良率が極端に低下するか皆
無になることがわかった。As a result, it was found that in the adhesives applied to the four-electrode treated Lfi+ of Examples 2 to 4, the failure rate due to electrostatic damage was extremely reduced or completely eliminated.
また粘着剤中に架a刑を併用することVCより、粘着剤
の再剥離性が生じ、チップ面に粘瘤沖j移行會生じない
で、簡単に剥離でさることもわかった0
以上の結果は、実施例−1と同様、切断時に発生した静
電気が、4電性粘滑シートτ弁して接地された金城盤上
にアースされた為、特に静電破壊に弱いとされるC−M
O5回路2帯電させることがなく、静電破壊不良が無か
ったものとみられる。It was also found that by using VC in combination with adhesive, re-peelability of the adhesive occurs, and the adhesive can be easily peeled off without causing any viscous migration on the chip surface. As in Example 1, the static electricity generated during cutting was grounded onto the Kinjo board, which was grounded through the 4-electrostatic viscous sheet τ valve.
The O5 circuit 2 was not charged, and it appears that there were no electrostatic breakdown defects.
実施例2〜4はいずれも、実施例−1と同様にチップサ
イズ不良、および切断時のチップ飛散はみらt″Lなか
った。In Examples 2 to 4, there were no chip size defects or chip scattering during cutting, as in Example-1.
比較例−1においては、粘着剤が非4箪性のため静電破
壊不良率は10%と高か−)だ0また比較例−2の場合
には、貼付、切断は良好で静電破壊不良も発失しなかっ
kが粘着剤が14−
再剥離性を封しないためにチップ−1’f]vc粘看剤
が移項して、チップの洗浄を心太とした。In Comparative Example-1, the adhesive was non-conductive, so the defective rate due to electrostatic damage was as high as 10%.In the case of Comparative Example-2, the pasting and cutting were good, but there was no electrostatic damage. No defects occurred, but since the adhesive did not seal the removability of the chip, the adhesive was used to clean the chip more thoroughly.
以上のように、従来問題であったウェハ切断時における
静−゛1破壊現象忙、再剥離性r有丁ゐ専篭性粘虐シー
トを用いてチップ化すゐことにより他端に減少式ゼるか
、iたは皆無とすることが可能となった。As mentioned above, by making chips using a special viscous sheet with removability, it is possible to reduce the static destructive phenomenon during wafer cutting, which has been a problem in the past. Or, it has become possible to eliminate it at all.
また得られたチップは、4電性粘眉シートが4f+ψ1
1離g、γMすることη・ら、専電性粘滑シートからの
剥醸が容易であ、す、チップ面への粘着剤等の移層かな
い。このため面例和性のテップが鉛られる。In addition, the obtained chip has a 4-electric adhesive sheet of 4f+ψ1
1 g, γM, η, etc., it is easy to remove the adhesive from the proprietary adhesive sheet, and there is no transfer of adhesive, etc. to the chip surface. For this reason, the step of surface example sumality is recommended.
匠って、不発明は半導体工業界に大巾な不良率の低減ン
生じ、高@頼件のICチップを提供丁ゐものである。The art of craftsmanship and non-invention has led to a significant reduction in defective rates in the semiconductor industry, providing highly demanded IC chips.
第1図乃至第5図はいずv2も不発明方法のためのアー
スの月νり方τ示す断面模式図でろゐ0符号のi発明
1.4電性粘看剤 2.4電性基材
6、導電性積増シート 4.アース線
5、金x製+i!Ii定盤 6.ウェハ7、 導電性フ
レーム
第1頁の続き
0発 明 者 最 上 和 親 下館市大字小川1工場
内Figures 1 to 5 are schematic cross-sectional views showing how to ground the ground for the uninvented method. 6. Conductive stacking sheet 4. Ground wire 5, gold x + i! Ii surface plate 6. Wafer 7, Conductive frame Continued from page 1 0 Inventor Kazuchika Mogami Inside the Oaza Ogawa 1 factory, Shimodate City
Claims (1)
によりチップ化する方法において。 前記粘層シートが50〜600g/19mm(JIS
C21D7)の積層力と、104Ω/al?以下の電気
抵抗r有する再剥離性積層シートであることt%徴とす
る半導体ウェハのチップ化方法0[Scope of Claims] 1. A method of making chips by dicing a beef conductor coated on a sticky sheet. The adhesive sheet has a weight of 50 to 600 g/19 mm (JIS
C21D7) lamination force and 104Ω/al? Method for converting semiconductor wafers into chips, characterized in that the removable laminated sheet has the following electrical resistance r: t%
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58159353A JPS6052039A (en) | 1983-08-31 | 1983-08-31 | Changing method into chip of semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58159353A JPS6052039A (en) | 1983-08-31 | 1983-08-31 | Changing method into chip of semiconductor wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6052039A true JPS6052039A (en) | 1985-03-23 |
JPS6330782B2 JPS6330782B2 (en) | 1988-06-21 |
Family
ID=15691986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58159353A Granted JPS6052039A (en) | 1983-08-31 | 1983-08-31 | Changing method into chip of semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6052039A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02139927A (en) * | 1988-11-21 | 1990-05-29 | Nitto Denko Corp | Attachment and removal of tape to and from semiconductor wafer |
JP2009114394A (en) * | 2007-11-08 | 2009-05-28 | Nitto Denko Corp | Adhesive sheet for inspection |
JP2011171591A (en) * | 2010-02-19 | 2011-09-01 | Disco Corp | Apparatus for carry in/carry out of wafer |
-
1983
- 1983-08-31 JP JP58159353A patent/JPS6052039A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02139927A (en) * | 1988-11-21 | 1990-05-29 | Nitto Denko Corp | Attachment and removal of tape to and from semiconductor wafer |
JP2009114394A (en) * | 2007-11-08 | 2009-05-28 | Nitto Denko Corp | Adhesive sheet for inspection |
JP2011171591A (en) * | 2010-02-19 | 2011-09-01 | Disco Corp | Apparatus for carry in/carry out of wafer |
Also Published As
Publication number | Publication date |
---|---|
JPS6330782B2 (en) | 1988-06-21 |
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