JPS6051329A - Interface circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction due to differences in earth potential between binary digital transmitting devices by the circuit constitution where the first transistor TR is provided in the transmission side and the second and the third TRs are provided in the reception side. CONSTITUTION:The emitter resistance of the first TR7 in the first transmitting device A is divided to a resistance R1 and a resistance R2 in the second transmitting device B, and the earth of the resistance R2 is looped back to an earth 9 of the first transmitting device A. A binary digital signal inputted to the first TR7 is inputted to the second TR11 through a transmission part 4, and the second TR11 is switched by the binary digital signal to which an earth potential difference DELTAV between the first and the second transmitting devices A and B is added, and the collector output switches the third TR12. Even if the differential voltage DELTAV is increased, only a voltage VCE between the collector and the emitter of the third TR12 is reduced by this increment, and switching of the third TR12 is not affected.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an interface circuit between binary digital transmission devices, and more particularly to an interface circuit composed of transistors.

(b) Prior Art and Problems Conventionally, the binary digital transmission device has malfunctioned due to a difference in ground potential between the first and second transmission devices for binary digital transmission, or external noise. Various methods have been used to prevent this malfunction. Typical conventional examples will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of a conventional interface circuit. In the same figure, A/, B/ are the first and second transmission devices, 1 is the interface circuit on the A' side of the first transmission device on the transmitting side and is a current switch, 2 is the input terminal of the interface circuit 1, and 3 is the input terminal of the interface circuit 1. Output terminal of interface circuit 1,
4 is a transmission line, 5 is a comparator of the interface circuit of the binary digital transmission device on the receiving side, 6 is an input terminal of the comparator 5, 7
' indicates earth. ΔV indicates the potential difference between the binary digital transmission devices A' and 87.

Figure 2 shows the binary digital signal used in Figure 1 and the
The potential difference ΔV between the second transmission device A' and 87 and the threshold value of the 21st digital signal are shown in full.

In FIG. 1, the binary digital signal is transmitted through the first transmission device ftA.
' is input to the input terminal 2 of the interface circuit 1 of
The input signal is input to the input terminal 6 of the interface circuit 5. In this case, a difference voltage ΔV in ground potential exists between the first and second transmission devices A' and 87 at the ground 7' of the device A'. In addition, the input terminal 6 of the interface 5 on the receiving side is connected to the ground potential △ to the binary digital signal as shown in Figure 2 (■).
V■ is added, and this binary digital signal ■10■ is input.

However, since the interface circuit 5 is a comparator, it discriminates the binary digital signal with respect to the threshold value ■, regardless of the added potential difference ΔV.

The above interface circuit consists of current switch 1 and comparator 5.
Because the circuit configuration is large-scale,
Moreover, it has the disadvantage of high cost.

(c) Purpose of the Invention In order to solve the above-mentioned drawbacks, the present invention configures an interface circuit of a binary digital transmission device on the transmitting side with a first transistor, and configures an interface circuit of a second transmission device on the receiving side with a first transistor. It is an object of the present invention to provide a simple interface circuit configured with a second transistor and a third transistor.

(d) Structure of the Invention In order to achieve the above object, the present invention provides an interface circuit between a first transmission device on a transmitting side and a second transmission device on a receiving side that transmits a binary digital signal. The output of the first transistor in the output stage of the device is connected to the input of the second transistor in the input stage of the second transmission device via a transmission line, and the bias point of the second transistor is the bias point of the first transistor. A circuit configured as a loop bank and the output of the second transistor are connected to the input of a third transistor whose bias point is the reference voltage of the ground point of the second transmission device, and the output of the second transistor is 3- The third transistor is characterized in that means is provided for absorbing the tip of the reference voltage at the bias point in the third transistor.

(e) Embodiments of the Invention Below, embodiments of the interface circuit of the present invention will be described with reference to the drawings. FIG. 3 shows a configuration diagram of an embodiment of the interface circuit of the present invention. In the figure, the same numbers as in Figure 1,
The same reference numerals indicate the same members.0 In Fig. 3, 7 indicates the first
transistor, 8 is an input terminal, 9 and 13 are ground, 10 is a diode, 11 is a second transistor, 12 is a third transistor, R1-R6 are resistors, A and B are first and second transmission devices, △V is 0 showing the difference in ground potential between devices A and 8. Is Figure 4 the same as Figure 3? Third transistor 12 for explanation
Indicates the operating voltage. In the same figure, VCC is the power supply voltage, V
cE is the collector-emitter voltage of the third transistor, VBE is the pace-emitter voltage, and ■ indicates a digital signal.0 In Figure 3, the interface circuit between the first and second transmission devices A and 8 is The transmission line 4 is composed of the first transistor 7, the second transistor 11, and the fourth to third transistors 12, and the emitter resistance of the first transistor is separated into a resistance R1 and a resistance R2 in the second transmission device B. The ground of the resistor R2 is connected to the ground 9 of the first transmission device A on the transmitting side.

The binary digital signal input to the input terminal 8 of the first transistor 7 is transmitted through the emitter resistor R1 - transmission line 4 - diode 1.
〇-Resistance R3? and is input to the second transistor 11 through the first and second transmission devices A, as shown in FIG.
The second transistor 11 is switched by the binary digital signal 2 to which the ground 1liQaV between 8 and 1liQaV is added. In this case, the second transistor 11 operates stably due to the emitter current i of the first transistor 7 and the resistor R2. The collector output of the second transistor 11 switches the third transistor. In this case, the collector of the third transistor is connected to the ground 13 on the second transmission device B side via a resistor R6.
0 connected to
In FIG. 4, the operation of the third transistor 12 is sufficient as long as the input amplitude is smaller than the base-emitter junction voltage VBE3. That is, when the second transistor 11 is on, it
The bias is set to R4> VBE3. In Figure 4, ■ indicates △V = O, and ■ indicates the second value when △V occurs.
This is related to transistor bias.

Even if ΔV increases in this way, VCE only decreases by that amount and does not affect the switching of the third transistor. Therefore, within the range of ΔV<VCE2, this interface circuit can obtain stable operation.

(f) As described in detail, in the present invention, a simple circuit configuration in which the transmitting side has a first transistor and the receiving side has second and third transistors is used to transmit data between binary digital transmission devices. It is possible to prevent mounting errors due to differences in ground potential.

[Brief explanation of drawings]

Fig. 1 shows a conventional interface circuit, Fig. 2 shows the ground potential and binary digital signal in Fig. 1, Fig. 3 shows an embodiment of the present invention, and Fig. 4 shows the output signal of the third transistor and the ground potential difference. shows the relationship between In the figure, A, A', B, and B' are binary digital transmission devices, 1 is a current switch, 2 and 8 input terminals, 3 is an output terminal, 4 is a transmission line, 5 is a comparator, and 6 is an input terminal. , 7.11
．． 12 is a transistor, 9 is ground, 10 is a diode,
7' and 9.13 are ground, R1-R6 are resistances, and ΔV is a ground potential difference. 1st Figure 193 Figure 2

Claims (1)

[Claims] In an interface circuit between a first transmission device on the transmitting side that transmits a binary digital signal and a second transmission device on the receiving side, the a1 power of the first transistor in the output stage of the first transmission device is transmitted through the transmission line. is connected to the input of a second transistor of the input stage of the second transmission device, the bias point of the second transistor is looped back to the bias point of the first transistor, and the output of the second transistor is connected to the input of the second transistor of the input stage of the second transmission device. It is connected to the input of a third transistor that uses the ground point of the second transmission device as a reference voltage of the bias point, and the difference in the reference voltage of the bias point between the first and second transmission devices is absorbed by the third transistor. An inter-seven chair circuit characterized in that it is provided with a means for.